EP0626641B1
(de)
*
|
1993-05-27 |
2003-04-09 |
Matsushita Electric Industrial Co., Ltd. |
Verbesserter Prozessor für Adressierung
|
DE69427265T2
(de)
|
1993-10-29 |
2002-05-02 |
Advanced Micro Devices, Inc. |
Superskalarbefehlsdekoder
|
US5689672A
(en)
*
|
1993-10-29 |
1997-11-18 |
Advanced Micro Devices, Inc. |
Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
|
US5630082A
(en)
*
|
1993-10-29 |
1997-05-13 |
Advanced Micro Devices, Inc. |
Apparatus and method for instruction queue scanning
|
EP0651324B1
(de)
*
|
1993-10-29 |
2006-03-22 |
Advanced Micro Devices, Inc. |
Spekulative Befehlswarteschlange für Befehle mit variabler Byteslänge
|
US5903772A
(en)
*
|
1993-10-29 |
1999-05-11 |
Advanced Micro Devices, Inc. |
Plural operand buses of intermediate widths coupling to narrower width integer and wider width floating point superscalar processing core
|
EP0651321B1
(de)
*
|
1993-10-29 |
2001-11-14 |
Advanced Micro Devices, Inc. |
Superskalarmikroprozessoren
|
US5600806A
(en)
*
|
1994-03-01 |
1997-02-04 |
Intel Corporation |
Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer
|
GB2293670A
(en)
*
|
1994-08-31 |
1996-04-03 |
Hewlett Packard Co |
Instruction cache
|
US5758116A
(en)
*
|
1994-09-30 |
1998-05-26 |
Intel Corporation |
Instruction length decoder for generating output length indicia to identity boundaries between variable length instructions
|
US5640526A
(en)
*
|
1994-12-21 |
1997-06-17 |
International Business Machines Corporation |
Superscaler instruction pipeline having boundary indentification logic for variable length instructions
|
US6006324A
(en)
*
|
1995-01-25 |
1999-12-21 |
Advanced Micro Devices, Inc. |
High performance superscalar alignment unit
|
US5819057A
(en)
*
|
1995-01-25 |
1998-10-06 |
Advanced Micro Devices, Inc. |
Superscalar microprocessor including an instruction alignment unit with limited dispatch to decode units
|
US5619408A
(en)
*
|
1995-02-10 |
1997-04-08 |
International Business Machines Corporation |
Method and system for recoding noneffective instructions within a data processing system
|
US5737550A
(en)
*
|
1995-03-28 |
1998-04-07 |
Advanced Micro Devices, Inc. |
Cache memory to processor bus interface and method thereof
|
US5822558A
(en)
*
|
1995-04-12 |
1998-10-13 |
Advanced Micro Devices, Inc. |
Method and apparatus for predecoding variable byte-length instructions within a superscalar microprocessor
|
US5991869A
(en)
*
|
1995-04-12 |
1999-11-23 |
Advanced Micro Devices, Inc. |
Superscalar microprocessor including a high speed instruction alignment unit
|
JP2931890B2
(ja)
*
|
1995-07-12 |
1999-08-09 |
三菱電機株式会社 |
データ処理装置
|
US5781789A
(en)
*
|
1995-08-31 |
1998-07-14 |
Advanced Micro Devices, Inc. |
Superscaler microprocessor employing a parallel mask decoder
|
US5819056A
(en)
*
|
1995-10-06 |
1998-10-06 |
Advanced Micro Devices, Inc. |
Instruction buffer organization method and system
|
US5920713A
(en)
*
|
1995-10-06 |
1999-07-06 |
Advanced Micro Devices, Inc. |
Instruction decoder including two-way emulation code branching
|
US5809273A
(en)
*
|
1996-01-26 |
1998-09-15 |
Advanced Micro Devices, Inc. |
Instruction predecode and multiple instruction decode
|
US6093213A
(en)
*
|
1995-10-06 |
2000-07-25 |
Advanced Micro Devices, Inc. |
Flexible implementation of a system management mode (SMM) in a processor
|
US5794063A
(en)
*
|
1996-01-26 |
1998-08-11 |
Advanced Micro Devices, Inc. |
Instruction decoder including emulation using indirect specifiers
|
JP2000506635A
(ja)
*
|
1995-10-06 |
2000-05-30 |
アドバンスト・マイクロ・デバイシズ・インコーポレイテッド |
命令プリデコード及び複数命令デコード用プロセッサ
|
US5926642A
(en)
*
|
1995-10-06 |
1999-07-20 |
Advanced Micro Devices, Inc. |
RISC86 instruction set
|
US5872947A
(en)
*
|
1995-10-24 |
1999-02-16 |
Advanced Micro Devices, Inc. |
Instruction classification circuit configured to classify instructions into a plurality of instruction types prior to decoding said instructions
|
US5796974A
(en)
*
|
1995-11-07 |
1998-08-18 |
Advanced Micro Devices, Inc. |
Microcode patching apparatus and method
|
EP0896700A1
(de)
*
|
1996-05-01 |
1999-02-17 |
Advanced Micro Devices, Inc. |
Superskalarer mikroprozessor mit hochleistungseinheit zur befehlsausrichtung
|
EP0912923A1
(de)
*
|
1996-07-16 |
1999-05-06 |
Advanced Micro Devices, Inc. |
Verfahren und vorrichtung zur vordekodierung von befehlen mit variabler bytelänge in einem superskalaren prozessor
|
JP2000515275A
(ja)
*
|
1996-07-16 |
2000-11-14 |
アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド |
高速命令整列ユニットを含むスーパースカラマイクロプロセッサ
|
US5867680A
(en)
*
|
1996-07-24 |
1999-02-02 |
Advanced Micro Devices, Inc. |
Microprocessor configured to simultaneously dispatch microcode and directly-decoded instructions
|
US6049863A
(en)
*
|
1996-07-24 |
2000-04-11 |
Advanced Micro Devices, Inc. |
Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor
|
US5872943A
(en)
*
|
1996-07-26 |
1999-02-16 |
Advanced Micro Devices, Inc. |
Apparatus for aligning instructions using predecoded shift amounts
|
US5941980A
(en)
*
|
1996-08-05 |
1999-08-24 |
Industrial Technology Research Institute |
Apparatus and method for parallel decoding of variable-length instructions in a superscalar pipelined data processing system
|
US5870576A
(en)
*
|
1996-12-16 |
1999-02-09 |
Hewlett-Packard Company |
Method and apparatus for storing and expanding variable-length program instructions upon detection of a miss condition within an instruction cache containing pointers to compressed instructions for wide instruction word processor architectures
|
US5987235A
(en)
*
|
1997-04-04 |
1999-11-16 |
Advanced Micro Devices, Inc. |
Method and apparatus for predecoding variable byte length instructions for fast scanning of instructions
|
US5872946A
(en)
*
|
1997-06-11 |
1999-02-16 |
Advanced Micro Devices, Inc. |
Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch
|
US6134649A
(en)
*
|
1997-11-17 |
2000-10-17 |
Advanced Micro Devices, Inc. |
Control transfer indication in predecode which identifies control transfer instruction and an alternate feature of an instruction
|
US6167506A
(en)
|
1997-11-17 |
2000-12-26 |
Advanced Micro Devices, Inc. |
Replacing displacement in control transfer instruction with encoding indicative of target address, including offset and target cache line location
|
US6041405A
(en)
*
|
1997-12-18 |
2000-03-21 |
Advanced Micro Devices, Inc. |
Instruction length prediction using an instruction length pattern detector
|
US6125441A
(en)
*
|
1997-12-18 |
2000-09-26 |
Advanced Micro Devices, Inc. |
Predicting a sequence of variable instruction lengths from previously identified length pattern indexed by an instruction fetch address
|
US5931944A
(en)
*
|
1997-12-23 |
1999-08-03 |
Intel Corporation |
Branch instruction handling in a self-timed marking system
|
US5941982A
(en)
*
|
1997-12-23 |
1999-08-24 |
Intel Corporation |
Efficient self-timed marking of lengthy variable length instructions
|
US6324639B1
(en)
*
|
1998-03-30 |
2001-11-27 |
Matsushita Electric Industrial Co., Ltd. |
Instruction converting apparatus using parallel execution code
|
US6061786A
(en)
*
|
1998-04-23 |
2000-05-09 |
Advanced Micro Devices, Inc. |
Processor configured to select a next fetch address by partially decoding a byte of a control transfer instruction
|
US6175908B1
(en)
|
1998-04-30 |
2001-01-16 |
Advanced Micro Devices, Inc. |
Variable byte-length instructions using state of function bit of second byte of plurality of instructions bytes as indicative of whether first byte is a prefix byte
|
US6141745A
(en)
*
|
1998-04-30 |
2000-10-31 |
Advanced Micro Devices, Inc. |
Functional bit identifying a prefix byte via a particular state regardless of type of instruction
|
US6292845B1
(en)
|
1998-08-26 |
2001-09-18 |
Infineon Technologies North America Corp. |
Processing unit having independent execution units for parallel execution of instructions of different category with instructions having specific bits indicating instruction size and category respectively
|
US6253287B1
(en)
*
|
1998-09-09 |
2001-06-26 |
Advanced Micro Devices, Inc. |
Using three-dimensional storage to make variable-length instructions appear uniform in two dimensions
|
US6460116B1
(en)
*
|
1998-09-21 |
2002-10-01 |
Advanced Micro Devices, Inc. |
Using separate caches for variable and generated fixed-length instructions
|
US6647490B2
(en)
|
1999-10-14 |
2003-11-11 |
Advanced Micro Devices, Inc. |
Training line predictor for branch targets
|
US6636959B1
(en)
|
1999-10-14 |
2003-10-21 |
Advanced Micro Devices, Inc. |
Predictor miss decoder updating line predictor storing instruction fetch address and alignment information upon instruction decode termination condition
|
US6546478B1
(en)
|
1999-10-14 |
2003-04-08 |
Advanced Micro Devices, Inc. |
Line predictor entry with location pointers and control information for corresponding instructions in a cache line
|
US6438664B1
(en)
|
1999-10-27 |
2002-08-20 |
Advanced Micro Devices, Inc. |
Microcode patch device and method for patching microcode using match registers and patch routines
|
US6738792B1
(en)
|
2001-03-09 |
2004-05-18 |
Advanced Micro Devices, Inc. |
Parallel mask generator
|
JP4542722B2
(ja)
*
|
2001-04-25 |
2010-09-15 |
富士通株式会社 |
命令処理方法
|
DE10120522A1
(de)
*
|
2001-04-26 |
2002-11-07 |
Infineon Technologies Ag |
Verfahren zum Erkennen einer korrekten Befehls-Einsprung-Adresse bei Verwendung unterschiedlich langer Befehlsworte
|
US7493470B1
(en)
|
2001-12-07 |
2009-02-17 |
Arc International, Plc |
Processor apparatus and methods optimized for control applications
|
US7278137B1
(en)
|
2001-12-26 |
2007-10-02 |
Arc International |
Methods and apparatus for compiling instructions for a data processor
|
US7568070B2
(en)
*
|
2005-07-29 |
2009-07-28 |
Qualcomm Incorporated |
Instruction cache having fixed number of variable length instructions
|
JP2007122626A
(ja)
*
|
2005-10-31 |
2007-05-17 |
Matsushita Electric Ind Co Ltd |
マイクロプロセッサ
|
US8898437B2
(en)
*
|
2007-11-02 |
2014-11-25 |
Qualcomm Incorporated |
Predecode repair cache for instructions that cross an instruction cache line
|
CN101833437B
(zh)
*
|
2009-05-19 |
2013-06-26 |
威盛电子股份有限公司 |
适用于微处理器的装置及方法
|
US8589661B2
(en)
*
|
2010-12-07 |
2013-11-19 |
Advanced Micro Devices, Inc. |
Odd and even start bit vectors
|
KR102277094B1
(ko)
*
|
2019-10-28 |
2021-07-15 |
이화여자대학교 산학협력단 |
버퍼 캐시 관리 방법 및 상기 버퍼 캐시 관리 방법이 적용된 컴퓨팅 장치
|
US11204768B2
(en)
|
2019-11-06 |
2021-12-21 |
Onnivation Llc |
Instruction length based parallel instruction demarcator
|
US20220100516A1
(en)
*
|
2020-09-26 |
2022-03-31 |
Intel Corporation |
Circuitry and methods for power efficient generation of length markers for a variable length instruction set
|