DE69026530D1 - Halbleiteranordnung mit zwei leitenden Schichten und Verfahren zu ihrer Herstellung - Google Patents

Halbleiteranordnung mit zwei leitenden Schichten und Verfahren zu ihrer Herstellung

Info

Publication number
DE69026530D1
DE69026530D1 DE69026530T DE69026530T DE69026530D1 DE 69026530 D1 DE69026530 D1 DE 69026530D1 DE 69026530 T DE69026530 T DE 69026530T DE 69026530 T DE69026530 T DE 69026530T DE 69026530 D1 DE69026530 D1 DE 69026530D1
Authority
DE
Germany
Prior art keywords
production
conductive layers
semiconductor arrangement
semiconductor
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69026530T
Other languages
English (en)
Other versions
DE69026530T2 (de
Inventor
Tatsuya Kajita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69026530D1 publication Critical patent/DE69026530D1/de
Publication of DE69026530T2 publication Critical patent/DE69026530T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/102—Mask alignment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)
  • Non-Volatile Memory (AREA)
DE69026530T 1989-05-20 1990-05-18 Halbleiteranordnung mit zwei leitenden Schichten und Verfahren zu ihrer Herstellung Expired - Fee Related DE69026530T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1127502A JP2952887B2 (ja) 1989-05-20 1989-05-20 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
DE69026530D1 true DE69026530D1 (de) 1996-05-23
DE69026530T2 DE69026530T2 (de) 1996-09-12

Family

ID=14961564

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69026530T Expired - Fee Related DE69026530T2 (de) 1989-05-20 1990-05-18 Halbleiteranordnung mit zwei leitenden Schichten und Verfahren zu ihrer Herstellung

Country Status (5)

Country Link
US (2) US5391902A (de)
EP (1) EP0399881B1 (de)
JP (1) JP2952887B2 (de)
KR (1) KR940000993B1 (de)
DE (1) DE69026530T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3115107B2 (ja) * 1992-07-02 2000-12-04 株式会社東芝 レチクルとそのレチクルを用いた半導体装置およびその製造方法
US5342801A (en) * 1993-03-08 1994-08-30 National Semiconductor Corporation Controllable isotropic plasma etching technique for the suppression of stringers in memory cells
KR0167874B1 (ko) * 1993-06-29 1999-01-15 사토 후미오 반도체 기억장치
US5604141A (en) * 1994-03-15 1997-02-18 National Semiconductor Corporation Method for forming virtual-ground flash EPROM array with reduced cell pitch in the X direction
JP2720813B2 (ja) * 1994-10-04 1998-03-04 日本電気株式会社 半導体装置の製造方法および半導体装置
KR0172255B1 (ko) * 1995-03-04 1999-03-30 김영환 반도체 소자의 금속 배선 형성방법
US6030880A (en) * 1998-04-03 2000-02-29 Sony Corporation Of Japan Alignment feature that avoids comet tail formation in spin-on materials and production method therefor
KR100293378B1 (ko) * 1999-08-31 2001-06-15 윤종용 반도체 장치의 제조방법
JP4683685B2 (ja) * 2000-01-17 2011-05-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法、フラッシュメモリの製造方法、およびスタティックランダムアクセスメモリの製造方法
US6667212B1 (en) * 2003-03-21 2003-12-23 Advanced Micro Devices, Inc. Alignment system for planar charge trapping dielectric memory cell lithography
KR100593732B1 (ko) 2003-11-18 2006-06-28 삼성전자주식회사 얼라인 키를 갖는 반도체 소자 및 그 제조방법

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4319263A (en) * 1978-05-18 1982-03-09 Texas Instruments Incorporated Double level polysilicon series transistor devices
US4213139A (en) * 1978-05-18 1980-07-15 Texas Instruments Incorporated Double level polysilicon series transistor cell
JPS56116670A (en) * 1980-02-20 1981-09-12 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
US4517729A (en) * 1981-07-27 1985-05-21 American Microsystems, Incorporated Method for fabricating MOS device with self-aligned contacts
EP0139764B1 (de) * 1983-03-31 1989-10-18 Matsushita Electric Industrial Co., Ltd. Verfahren zur herstellung von dünnschicht-integralvorrichtungen
JPS60224278A (ja) * 1984-04-20 1985-11-08 Seiko Instr & Electronics Ltd Ｎ型トランジスタ
JPS6161467A (ja) * 1984-08-31 1986-03-29 Fujitsu Ltd 半導体装置及びその製造方法
US4758529A (en) * 1985-10-31 1988-07-19 Rca Corporation Method of forming an improved gate dielectric for a MOSFET on an insulating substrate
DE3640174A1 (de) * 1985-11-27 1987-06-04 Sharp Kk Duennfilm-transistor-anordnung
JPS62265756A (ja) * 1986-05-14 1987-11-18 Oki Electric Ind Co Ltd 薄膜トランジスタマトリクス
US4886977A (en) * 1986-11-11 1989-12-12 Canon Kabushiki Kaisha Photoelectric converter provided with voltage dividing means
JPH0691252B2 (ja) * 1986-11-27 1994-11-14 日本電気株式会社 薄膜トランジスタアレイ
JPH0680685B2 (ja) * 1986-12-29 1994-10-12 日本電気株式会社 薄膜トランジスタとその製造方法
JPS63185065A (ja) * 1987-01-27 1988-07-30 Matsushita Electric Ind Co Ltd 半導体装置
JP2603247B2 (ja) * 1987-03-27 1997-04-23 キヤノン株式会社 薄膜トランジスタ
JPS63308384A (ja) * 1987-06-10 1988-12-15 Fujitsu Ltd 薄膜トランジスタ
US5061654A (en) * 1987-07-01 1991-10-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit having oxide regions with different thickness
JPS6414070A (en) * 1987-07-07 1989-01-18 Seiko Epson Corp Thermal recording medium
US4839705A (en) * 1987-12-16 1989-06-13 Texas Instruments Incorporated X-cell EEPROM array
US4861730A (en) * 1988-01-25 1989-08-29 Catalyst Semiconductor, Inc. Process for making a high density split gate nonvolatile memory cell
JP2575795B2 (ja) * 1988-04-28 1997-01-29 富士通株式会社 半導体装置の製造方法
JP2509697B2 (ja) * 1989-04-28 1996-06-26 株式会社東芝 半導体装置およびその製造方法
JP2552543B2 (ja) * 1989-05-10 1996-11-13 株式会社バルダン タオル横切り装置

Also Published As

Publication number Publication date
DE69026530T2 (de) 1996-09-12
EP0399881B1 (de) 1996-04-17
JPH02306666A (ja) 1990-12-20
EP0399881A2 (de) 1990-11-28
US5391902A (en) 1995-02-21
KR940000993B1 (ko) 1994-02-07
EP0399881A3 (de) 1991-01-30
JP2952887B2 (ja) 1999-09-27
US5468664A (en) 1995-11-21
KR900019127A (ko) 1990-12-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee