DE60336090D1 - Verfahren zur verbesserung der öberflächenrauhigkeit eines halbleiterwafers - Google Patents

Verfahren zur verbesserung der öberflächenrauhigkeit eines halbleiterwafers

Info

Publication number
DE60336090D1
DE60336090D1 DE60336090T DE60336090T DE60336090D1 DE 60336090 D1 DE60336090 D1 DE 60336090D1 DE 60336090 T DE60336090 T DE 60336090T DE 60336090 T DE60336090 T DE 60336090T DE 60336090 D1 DE60336090 D1 DE 60336090D1
Authority
DE
Germany
Prior art keywords
atmosphere
improving
semiconductor wafers
surface weight
purged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60336090T
Other languages
English (en)
Inventor
Eric Neyret
Emmanuel Arene
Ludovic Ecarnot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Application granted granted Critical
Publication of DE60336090D1 publication Critical patent/DE60336090D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Weting (AREA)
DE60336090T 2003-12-03 2003-12-03 Verfahren zur verbesserung der öberflächenrauhigkeit eines halbleiterwafers Expired - Lifetime DE60336090D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2003/006380 WO2005055308A1 (en) 2003-12-03 2003-12-03 Process for improving the surface roughness of a wafer

Publications (1)

Publication Number Publication Date
DE60336090D1 true DE60336090D1 (de) 2011-03-31

Family

ID=34640309

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60336090T Expired - Lifetime DE60336090D1 (de) 2003-12-03 2003-12-03 Verfahren zur verbesserung der öberflächenrauhigkeit eines halbleiterwafers

Country Status (7)

Country Link
EP (1) EP1690289B9 (de)
JP (1) JP4619949B2 (de)
CN (1) CN1879204B (de)
AT (1) ATE498904T1 (de)
AU (1) AU2003294166A1 (de)
DE (1) DE60336090D1 (de)
WO (1) WO2005055308A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008136126A1 (ja) * 2007-04-20 2008-11-13 Canon Anelva Corporation 炭化ケイ素基板を有する半導体デバイスのアニール方法と半導体デバイス
WO2013150636A1 (ja) * 2012-04-05 2013-10-10 国立大学法人東北大学 シリコンウェーハの原子オーダー平坦化表面処理方法及び熱処理装置
US9157681B2 (en) 2010-02-04 2015-10-13 National University Corporation Tohoku University Surface treatment method for atomically flattening a silicon wafer and heat treatment apparatus
JPWO2013150636A1 (ja) * 2012-04-05 2015-12-14 国立大学法人東北大学 シリコンウェーハの原子オーダー平坦化表面処理方法及び熱処理装置
DE102013018533B4 (de) 2013-08-23 2019-01-10 Centrotherm Photovoltaics Ag Verfahren zum Reduzieren der Oberflächenrauigkeit einer Oberfläche aus Halbleitermaterial eines Substrats mit 3-D Strukturen
CN106920746A (zh) * 2015-12-25 2017-07-04 有研半导体材料有限公司 一种改善硅片表面微缺陷的方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58192320A (ja) * 1982-05-07 1983-11-09 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
JPH07321042A (ja) * 1994-04-19 1995-12-08 Texas Instr Inc <Ti> 集積回路デバイスの製作方法
GB2312525A (en) * 1996-04-24 1997-10-29 Northern Telecom Ltd Providing cladding on planar optical waveguide by heating to flow
JP3478141B2 (ja) * 1998-09-14 2003-12-15 信越半導体株式会社 シリコンウエーハの熱処理方法及びシリコンウエーハ
JP3565068B2 (ja) * 1998-12-28 2004-09-15 信越半導体株式会社 シリコンウエーハの熱処理方法およびシリコンウエーハ
EP1061565A1 (de) * 1998-12-28 2000-12-20 Shin-Etsu Handotai Co., Ltd Verfahren zur thermischen behandlung von einem siliziumplättchen und siliziumplättchen
JP4103391B2 (ja) * 1999-10-14 2008-06-18 信越半導体株式会社 Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
JP3893608B2 (ja) * 2000-09-21 2007-03-14 信越半導体株式会社 アニールウェーハの製造方法
JP2002110949A (ja) * 2000-09-28 2002-04-12 Canon Inc Ｓｏｉの熱処理方法及び製造方法
JP2002110688A (ja) * 2000-09-29 2002-04-12 Canon Inc Ｓｏｉの熱処理方法及び製造方法
FR2827078B1 (fr) * 2001-07-04 2005-02-04 Soitec Silicon On Insulator Procede de diminution de rugosite de surface
FR2827423B1 (fr) * 2001-07-16 2005-05-20 Soitec Silicon On Insulator Procede d'amelioration d'etat de surface
US7148570B2 (en) * 2001-08-13 2006-12-12 Sandisk 3D Llc Low resistivity titanium silicide on heavily doped semiconductor
JP5052728B2 (ja) * 2002-03-05 2012-10-17 株式会社Ｓｕｍｃｏ シリコン単結晶層の製造方法
AU2003296844A1 (en) * 2003-12-03 2005-06-24 S.O.I.Tec Silicon On Insulator Technologies Process for improving the surface roughness of a semiconductor wafer

Also Published As

Publication number Publication date
ATE498904T1 (de) 2011-03-15
EP1690289B1 (de) 2011-02-16
JP4619949B2 (ja) 2011-01-26
AU2003294166A1 (en) 2005-06-24
CN1879204A (zh) 2006-12-13
EP1690289B9 (de) 2012-03-14
CN1879204B (zh) 2010-07-14
EP1690289A1 (de) 2006-08-16
JP2007516586A (ja) 2007-06-21
WO2005055308A1 (en) 2005-06-16

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