DE60220762D1 - Halbleiterbauelement und zugehöriges Herstellungsverfahren - Google Patents

Halbleiterbauelement und zugehöriges Herstellungsverfahren

Info

Publication number
DE60220762D1
DE60220762D1 DE60220762T DE60220762T DE60220762D1 DE 60220762 D1 DE60220762 D1 DE 60220762D1 DE 60220762 T DE60220762 T DE 60220762T DE 60220762 T DE60220762 T DE 60220762T DE 60220762 D1 DE60220762 D1 DE 60220762D1
Authority
DE
Germany
Prior art keywords
semiconductor component
associated manufacturing
manufacturing
semiconductor
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60220762T
Other languages
English (en)
Other versions
DE60220762T2 (de
Inventor
Kazuyuki Kumeno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE60220762D1 publication Critical patent/DE60220762D1/de
Publication of DE60220762T2 publication Critical patent/DE60220762T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8228—Complementary devices, e.g. complementary transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE60220762T 2001-12-11 2002-04-25 Halbleiterbauelement und zugehöriges Herstellungsverfahren Expired - Lifetime DE60220762T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001377623A JP4000256B2 (ja) 2001-12-11 2001-12-11 半導体装置及びその製造方法
JP2001377623 2001-12-11

Publications (2)

Publication Number Publication Date
DE60220762D1 true DE60220762D1 (de) 2007-08-02
DE60220762T2 DE60220762T2 (de) 2007-10-11

Family

ID=19185541

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60220762T Expired - Lifetime DE60220762T2 (de) 2001-12-11 2002-04-25 Halbleiterbauelement und zugehöriges Herstellungsverfahren

Country Status (7)

Country Link
US (1) US6781207B2 (de)
EP (1) EP1320130B1 (de)
JP (1) JP4000256B2 (de)
KR (1) KR100815379B1 (de)
CN (1) CN100386878C (de)
DE (1) DE60220762T2 (de)
TW (1) TW577146B (de)

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JP2004342821A (ja) * 2003-05-15 2004-12-02 Renesas Technology Corp 半導体装置
JP2005203436A (ja) * 2004-01-13 2005-07-28 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
JP2005322730A (ja) * 2004-05-07 2005-11-17 Renesas Technology Corp 半導体装置及びその製造方法
JP4268569B2 (ja) * 2004-06-16 2009-05-27 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
KR100647882B1 (ko) * 2004-07-09 2006-11-24 주식회사 마루스 접속력 향상구조를 갖는 전기접속기용 커넥터
JP4969779B2 (ja) * 2004-12-28 2012-07-04 株式会社東芝 半導体装置の製造方法
JP2006202860A (ja) * 2005-01-19 2006-08-03 Toshiba Corp 半導体装置及びその製造方法
KR100811267B1 (ko) * 2005-12-22 2008-03-07 주식회사 하이닉스반도체 반도체소자의 듀얼게이트 형성방법
JP5190189B2 (ja) * 2006-08-09 2013-04-24 パナソニック株式会社 半導体装置及びその製造方法
CN101577286B (zh) * 2008-05-05 2012-01-11 联华电子股份有限公司 复合式转移栅极及其制造方法
US11193634B2 (en) * 2012-07-03 2021-12-07 Tseng-Lu Chien LED and/or laser light source or bulb for light device
JP5559567B2 (ja) * 2010-02-24 2014-07-23 パナソニック株式会社 半導体装置
JP5857225B2 (ja) * 2011-03-25 2016-02-10 パナソニックＩｐマネジメント株式会社 半導体装置
FR2981503A1 (fr) * 2011-10-13 2013-04-19 St Microelectronics Rousset Transistor mos non sujet a l'effet hump
US9196624B2 (en) * 2012-07-10 2015-11-24 Cypress Semiconductor Corporation Leakage reducing writeline charge protection circuit
CN105206528A (zh) * 2014-06-17 2015-12-30 北大方正集团有限公司 平面vdmos器件的制造方法
JP6382025B2 (ja) * 2014-08-22 2018-08-29 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2015188103A (ja) * 2015-06-03 2015-10-29 ラピスセミコンダクタ株式会社 半導体装置の製造方法
US10446567B2 (en) * 2017-03-31 2019-10-15 Asahi Kasei Microdevices Corporation Nonvolatile storage element and reference voltage generation circuit
US10734489B2 (en) * 2018-07-31 2020-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming semiconductor device structure with metal silicide layer

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Publication number Priority date Publication date Assignee Title
JP2895166B2 (ja) * 1990-05-31 1999-05-24 キヤノン株式会社 半導体装置の製造方法
JPH06244369A (ja) 1993-02-19 1994-09-02 Sony Corp Ｃｍｏｓトランジスタおよびそのゲート電極との接続孔とその製造方法
JP3039200B2 (ja) * 1993-06-07 2000-05-08 日本電気株式会社 Ｍｏｓトランジスタおよびその製造方法
JPH0786421A (ja) 1993-09-13 1995-03-31 Fujitsu Ltd 相補型ｍｏｓトランジスタ及びその製造方法
JP3249292B2 (ja) 1994-04-28 2002-01-21 株式会社リコー デュアルゲート構造の相補形ｍｉｓ半導体装置
JPH098040A (ja) * 1995-06-16 1997-01-10 Sony Corp 配線及びその形成方法
JPH0974195A (ja) * 1995-07-06 1997-03-18 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
JPH0927555A (ja) * 1995-07-10 1997-01-28 Ricoh Co Ltd 半導体装置とその製造方法
JPH0992823A (ja) * 1995-09-26 1997-04-04 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP3393249B2 (ja) * 1995-12-27 2003-04-07 ソニー株式会社 デュアルゲート構造を有する半導体装置およびその製造方法
JPH09205152A (ja) * 1996-01-25 1997-08-05 Sony Corp ２層ゲート電極構造を有するｃｍｏｓ半導体装置及びその製造方法
TW322591B (de) * 1996-02-09 1997-12-11 Handotai Energy Kenkyusho Kk
JPH09246541A (ja) 1996-03-07 1997-09-19 Sony Corp 半導体装置の製造方法
DE69630944D1 (de) * 1996-03-29 2004-01-15 St Microelectronics Srl Hochspannungsfester MOS-Transistor und Verfahren zur Herstellung
JP2910839B2 (ja) 1996-06-25 1999-06-23 日本電気株式会社 半導体装置とその製造方法
JP4142753B2 (ja) * 1996-12-26 2008-09-03 株式会社東芝 スパッタターゲット、スパッタ装置、半導体装置およびその製造方法
EP0923116A1 (de) * 1997-12-12 1999-06-16 STMicroelectronics S.r.l. Herstellungsverfahren für polykristalline integrierte Wiederstände in MOS-Technologie und integriertes MOS-Bauelement mit polykristallinen Silizium-Widerständen
KR100255134B1 (ko) * 1997-12-31 2000-05-01 윤종용 반도체 장치 및 그 제조 방법
JP3737914B2 (ja) 1999-09-02 2006-01-25 松下電器産業株式会社 半導体装置及びその製造方法
US6191460B1 (en) * 1999-09-07 2001-02-20 Integrated Device Technology, Inc. Identical gate conductivity type static random access memory cell
JP2001156290A (ja) * 1999-11-30 2001-06-08 Nec Corp 半導体装置
KR20010066122A (ko) * 1999-12-31 2001-07-11 박종섭 반도체 소자의 폴리사이드 듀얼 게이트 형성 방법
JP2001210725A (ja) 2000-01-25 2001-08-03 Matsushita Electric Ind Co Ltd 半導体装置
JP2001332630A (ja) * 2000-05-19 2001-11-30 Sharp Corp 半導体装置の製造方法
JP2002217310A (ja) * 2001-01-18 2002-08-02 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6894356B2 (en) * 2002-03-15 2005-05-17 Integrated Device Technology, Inc. SRAM system having very lightly doped SRAM load transistors for improving SRAM cell stability and method for making the same

Also Published As

Publication number Publication date
DE60220762T2 (de) 2007-10-11
KR20030047660A (ko) 2003-06-18
KR100815379B1 (ko) 2008-03-20
EP1320130A2 (de) 2003-06-18
EP1320130B1 (de) 2007-06-20
CN1426110A (zh) 2003-06-25
EP1320130A3 (de) 2005-05-11
US6781207B2 (en) 2004-08-24
CN100386878C (zh) 2008-05-07
US20030107090A1 (en) 2003-06-12
JP4000256B2 (ja) 2007-10-31
TW577146B (en) 2004-02-21
JP2003179056A (ja) 2003-06-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE