DE602006014485D1 - Halbleiterbaustein und Testverfahren dafür - Google Patents

Halbleiterbaustein und Testverfahren dafür

Info

Publication number
DE602006014485D1
DE602006014485D1 DE602006014485T DE602006014485T DE602006014485D1 DE 602006014485 D1 DE602006014485 D1 DE 602006014485D1 DE 602006014485 T DE602006014485 T DE 602006014485T DE 602006014485 T DE602006014485 T DE 602006014485T DE 602006014485 D1 DE602006014485 D1 DE 602006014485D1
Authority
DE
Germany
Prior art keywords
semiconductor device
test method
test
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006014485T
Other languages
English (en)
Inventor
Shingo Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Publication of DE602006014485D1 publication Critical patent/DE602006014485D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE602006014485T 2005-10-14 2006-10-16 Halbleiterbaustein und Testverfahren dafür Active DE602006014485D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005300151A JP4955250B2 (ja) 2005-10-14 2005-10-14 半導体装置及びそのテスト方法

Publications (1)

Publication Number Publication Date
DE602006014485D1 true DE602006014485D1 (de) 2010-07-08

Family

ID=37708226

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006014485T Active DE602006014485D1 (de) 2005-10-14 2006-10-16 Halbleiterbaustein und Testverfahren dafür

Country Status (5)

Country Link
US (1) US7940071B2 (de)
EP (1) EP1777534B1 (de)
JP (1) JP4955250B2 (de)
KR (1) KR100876567B1 (de)
DE (1) DE602006014485D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101803200A (zh) 2008-10-06 2010-08-11 松下电器产业株式会社 差动开关、d/a转换器、半导体集成电路及通信机器
WO2011016090A1 (ja) * 2009-08-06 2011-02-10 富士通株式会社 位相インタポレータ、半導体装置及びその試験方法
JP5292243B2 (ja) 2009-09-28 2013-09-18 株式会社日立製作所 半導体集積回路
US8184029B1 (en) * 2010-06-16 2012-05-22 Xilinx, Inc. Phase interpolator
RU2546071C1 (ru) * 2013-11-07 2015-04-10 Федеральное государственное унитарное предприятие "Научно-производственный центр автоматики и приборостроения имени академика Н.А. Пилюгина" (ФГУП "НПЦАП") Устройство контроля протекания тока
TWI634334B (zh) * 2016-10-21 2018-09-01 新特系統股份有限公司 探針卡模組
JP6835573B2 (ja) * 2016-12-27 2021-02-24 日本電気株式会社 電圧調整回路、及び電圧調整方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08179009A (ja) 1994-12-21 1996-07-12 Yamaha Corp テスト回路
FR2757712B1 (fr) * 1996-12-19 1999-01-22 Sgs Thomson Microelectronics Dispositif de controle de mise sous tension ou hors tension d'un circuit integre
US6247138B1 (en) 1997-06-12 2001-06-12 Fujitsu Limited Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system
JP3955150B2 (ja) * 1998-01-08 2007-08-08 富士通株式会社 位相インターポレータ、タイミング信号発生回路、および、該タイミング信号発生回路が適用される半導体集積回路装置並びに半導体集積回路システム
GB2338311B (en) * 1997-11-20 2002-04-17 Advantest Corp IC testing apparatus
US6397042B1 (en) 1998-03-06 2002-05-28 Texas Instruments Incorporated Self test of an electronic device
US6348826B1 (en) 2000-06-28 2002-02-19 Intel Corporation Digital variable-delay circuit having voltage-mixing interpolator and methods of testing input/output buffers using same
US7309998B2 (en) * 2002-12-02 2007-12-18 Burns Lawrence M Process monitor for monitoring an integrated circuit chip
KR100532447B1 (ko) * 2003-07-11 2005-11-30 삼성전자주식회사 높은 테스트 전류 주입이 가능한 집적 회로 소자의 병렬테스트 장치 및 방법
JP3857696B2 (ja) 2004-03-10 2006-12-13 株式会社東芝 半導体集積回路およびその検査方法
US7609079B2 (en) * 2006-03-02 2009-10-27 Dialog Semiconductor Gmbh Probeless DC testing of CMOS I/O circuits

Also Published As

Publication number Publication date
US20070091701A1 (en) 2007-04-26
US7940071B2 (en) 2011-05-10
JP2007108055A (ja) 2007-04-26
JP4955250B2 (ja) 2012-06-20
EP1777534A1 (de) 2007-04-25
KR20070041400A (ko) 2007-04-18
EP1777534B1 (de) 2010-05-26
KR100876567B1 (ko) 2008-12-31

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: RENESAS ELECTRONICS CORPORATION, KAWASAKI, KAN, JP

8364 No opposition during term of opposition