DE602006011003D1 - Schaltkreis zur Datenreproduktion - Google Patents

Schaltkreis zur Datenreproduktion

Info

Publication number
DE602006011003D1
DE602006011003D1 DE602006011003T DE602006011003T DE602006011003D1 DE 602006011003 D1 DE602006011003 D1 DE 602006011003D1 DE 602006011003 T DE602006011003 T DE 602006011003T DE 602006011003 T DE602006011003 T DE 602006011003T DE 602006011003 D1 DE602006011003 D1 DE 602006011003D1
Authority
DE
Germany
Prior art keywords
circuit
data reproduction
reproduction
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006011003T
Other languages
English (en)
Inventor
Hirotaka Tamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE602006011003D1 publication Critical patent/DE602006011003D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
DE602006011003T 2005-09-16 2006-02-21 Schaltkreis zur Datenreproduktion Active DE602006011003D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005271024A JP4668750B2 (ja) 2005-09-16 2005-09-16 データ再生回路

Publications (1)

Publication Number Publication Date
DE602006011003D1 true DE602006011003D1 (de) 2010-01-21

Family

ID=37420862

Family Applications (2)

Application Number Title Priority Date Filing Date
DE602006017484T Active DE602006017484D1 (de) 2005-09-16 2006-02-21 Schaltkreis zur Datenreproduktion
DE602006011003T Active DE602006011003D1 (de) 2005-09-16 2006-02-21 Schaltkreis zur Datenreproduktion

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE602006017484T Active DE602006017484D1 (de) 2005-09-16 2006-02-21 Schaltkreis zur Datenreproduktion

Country Status (4)

Country Link
US (2) US7940873B2 (de)
EP (2) EP1890418B1 (de)
JP (1) JP4668750B2 (de)
DE (2) DE602006017484D1 (de)

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US7446699B2 (en) * 2006-03-10 2008-11-04 Mcewan Thomas Edward Error corrector for radar timing systems
TWI316257B (en) * 2006-11-21 2009-10-21 Realtek Semiconductor Corp Data reading circuit and data reading method
US8243869B2 (en) * 2006-11-28 2012-08-14 Broadlight Ltd. Burst mode clock and data recovery circuit and method
US7925156B2 (en) * 2007-01-16 2011-04-12 Broadlight, Ltd. Apparatus and method for measuring the quality of burst signals and performing optical line diagnostics
FR2914807B1 (fr) * 2007-04-06 2012-11-16 Centre Nat Detudes Spatiales Cnes Dispositif d'extraction d'horloge a asservissement numerique de phase sans reglage externe
US7777581B2 (en) * 2007-10-19 2010-08-17 Diablo Technologies Inc. Voltage Controlled Oscillator (VCO) with a wide tuning range and substantially constant voltage swing over the tuning range
TWI380597B (en) * 2009-04-08 2012-12-21 Univ Nat Taiwan Signal generating circuits
GB2469473A (en) * 2009-04-14 2010-10-20 Cambridge Silicon Radio Ltd Digital phase locked loop
US8831073B2 (en) * 2009-08-31 2014-09-09 Sony Corporation Wireless transmission system, wireless communication device, and wireless communication method
JP5363967B2 (ja) * 2009-12-22 2013-12-11 ルネサスエレクトロニクス株式会社 クロックデータリカバリ回路、表示装置用データ転送装置及び表示装置用データ転送方法
JP5495316B2 (ja) * 2010-03-31 2014-05-21 Ｎｅｃネットワーク・センサ株式会社 Ｐｃｍ信号復調回路、該復調回路に用いられるｐｃｍ信号復調方法及びｐｃｍ信号復調プログラム
WO2011151922A1 (ja) * 2010-06-04 2011-12-08 三菱電機株式会社 受信装置、データ識別再生装置、ｐｏｎシステムおよびデータ識別再生方法
US8804888B2 (en) * 2010-07-12 2014-08-12 Ensphere Solutions, Inc. Wide band clock data recovery
JP5494323B2 (ja) * 2010-07-21 2014-05-14 富士通株式会社 受信回路
JP5605064B2 (ja) * 2010-08-04 2014-10-15 富士通株式会社 判定帰還等化回路、受信回路、及び判定帰還等化処理方法
JP5625596B2 (ja) * 2010-08-04 2014-11-19 富士通株式会社 受信装置
TWI436630B (zh) * 2010-11-16 2014-05-01 Etron Technology Inc 可容忍擾動之相位選擇器與相關方法、以及時脈與資料恢復電路
US8850259B2 (en) 2011-01-07 2014-09-30 Anue Systems, Inc. Systems and methods for precise generation of phase variation in digital signals
US8683254B2 (en) * 2011-01-07 2014-03-25 Anue Systems, Inc. Systems and methods for precise event timing measurements
US8788867B2 (en) 2011-01-07 2014-07-22 Anue Systems, Inc. Systems and methods for playback of detected timing events
US9124413B2 (en) * 2011-10-26 2015-09-01 Qualcomm Incorporated Clock and data recovery for NFC transceivers
US8571159B1 (en) * 2011-12-02 2013-10-29 Altera Corporation Apparatus and methods for high-speed interpolator-based clock and data recovery
JP6075191B2 (ja) * 2013-04-30 2017-02-08 富士通株式会社 補間回路および受信回路
KR102193681B1 (ko) * 2014-01-28 2020-12-21 삼성전자주식회사 Ｄｌｌ을 이용한 ｉｌｐｌｌ 회로
EP3143603B1 (de) * 2014-05-16 2024-02-21 Analog Devices International Unlimited Company Konfiguration von signalverarbeitungssystemen
KR20160037656A (ko) * 2014-09-29 2016-04-06 삼성전자주식회사 에러 검출기 및 발진기의 에러 검출 방법
WO2016134524A1 (en) * 2015-02-27 2016-09-01 Lattice Semiconductor Corporation Phase tracking for clock and data recovery
TWI718808B (zh) * 2019-12-16 2021-02-11 瑞昱半導體股份有限公司 干擾消除器與干擾消除方法
US11522573B1 (en) * 2021-11-05 2022-12-06 Realtek Semiconductor Corporation Transceiver apparatus and transceiver apparatus operation method thereof having phase-tracking mechanism

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JPH05167570A (ja) * 1991-12-12 1993-07-02 Fujitsu Ltd クロック再生回路
JP2959286B2 (ja) * 1992-07-02 1999-10-06 株式会社村田製作所 Ｄｑｐｓｋ遅延検波回路
JP3005495B2 (ja) 1997-05-13 2000-01-31 福島日本電気株式会社 Ｐｌｌ回路
JP4344475B2 (ja) 1998-01-20 2009-10-14 シリコン・イメージ，インコーポレーテッド ギガボー速度のデータ通信用のｃｍｏｓドライバとオンチップ終端器
JP3077661B2 (ja) 1998-03-12 2000-08-14 日本電気株式会社 オーバーサンプリング型クロックリカバリ回路
JP2000174736A (ja) * 1998-12-08 2000-06-23 Sharp Corp ビット同期回路
KR100287887B1 (ko) 1999-02-19 2001-04-16 김영환 데이터/클럭 복원 회로
US6606364B1 (en) * 1999-03-04 2003-08-12 Harris Corporation Multiple data rate bit synchronizer having phase/frequency detector gain constant proportional to PLL clock divider ratio
JP4425426B2 (ja) 2000-05-11 2010-03-03 Ｎｅｃエレクトロニクス株式会社 オーバーサンプリング型クロックリカバリ回路
JP2002025202A (ja) * 2000-07-06 2002-01-25 Matsushita Electric Ind Co Ltd クロック抽出回路
KR100346837B1 (ko) * 2000-09-02 2002-08-03 삼성전자 주식회사 클럭 스큐에 의한 에러를 최소화하는 데이타 복원 장치 및그 방법
JP3636657B2 (ja) * 2000-12-21 2005-04-06 Ｎｅｃエレクトロニクス株式会社 クロックアンドデータリカバリ回路とそのクロック制御方法
US7315594B2 (en) * 2001-07-27 2008-01-01 International Business Machines Corporation Clock data recovering system with external early/late input
JP4099994B2 (ja) * 2002-01-07 2008-06-11 富士通株式会社 位相ロック・ループ回路
DE10207315B4 (de) * 2002-02-21 2007-01-04 Infineon Technologies Ag Vorrichtung zur Datenrückgewinnung aus einem empfangenen Datensignal
JP3802447B2 (ja) * 2002-05-17 2006-07-26 Ｎｅｃエレクトロニクス株式会社 クロックアンドデータリカバリ回路とそのクロック制御方法
JP2004088386A (ja) 2002-08-27 2004-03-18 Rohm Co Ltd シリアルデータの再生回路及び再生方法
US7245682B2 (en) * 2002-09-30 2007-07-17 Intel Corporation Determining an optimal sampling clock
US7457391B2 (en) * 2003-03-26 2008-11-25 Infineon Technologies Ag Clock and data recovery unit
US7236553B1 (en) * 2004-01-23 2007-06-26 Silicon Image, Inc. Reduced dead-cycle, adaptive phase tracking method and apparatus
US7436920B2 (en) * 2004-06-17 2008-10-14 Matisse Networks Burst mode receiver based on charge pump PLL with idle-time loop stabilizer
KR100570632B1 (ko) * 2004-07-06 2006-04-12 삼성전자주식회사 클록복원회로 및 방법과 이를 이용한 고속 데이터송수신회로
TWI241776B (en) * 2004-10-11 2005-10-11 Realtek Semiconductor Corp Clock generator and data recovery circuit
US7492849B2 (en) * 2005-05-10 2009-02-17 Ftd Solutions Pte., Ltd. Single-VCO CDR for TMDS data at gigabit rate

Also Published As

Publication number Publication date
US7940873B2 (en) 2011-05-10
JP2007082154A (ja) 2007-03-29
DE602006017484D1 (de) 2010-11-25
EP1764945A1 (de) 2007-03-21
EP1890418A1 (de) 2008-02-20
EP1764945B1 (de) 2010-10-13
US8559578B2 (en) 2013-10-15
JP4668750B2 (ja) 2011-04-13
EP1890418B1 (de) 2009-12-09
US20070064850A1 (en) 2007-03-22
US20110249519A1 (en) 2011-10-13

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8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

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