DE602006019994D1 - Leiterplatte - Google Patents

Leiterplatte

Info

Publication number
DE602006019994D1
DE602006019994D1 DE602006019994T DE602006019994T DE602006019994D1 DE 602006019994 D1 DE602006019994 D1 DE 602006019994D1 DE 602006019994 T DE602006019994 T DE 602006019994T DE 602006019994 T DE602006019994 T DE 602006019994T DE 602006019994 D1 DE602006019994 D1 DE 602006019994D1
Authority
DE
Germany
Prior art keywords
circuit board
board
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006019994T
Other languages
English (en)
Inventor
Yoshihiko Takeuchi
Mitsuru Honjo
Tetsuya Ohsawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Publication of DE602006019994D1 publication Critical patent/DE602006019994D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/0989Coating free areas, e.g. areas other than pads or lands free of solder resist
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10689Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
DE602006019994T 2005-05-24 2006-05-08 Leiterplatte Active DE602006019994D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005151426A JP3828917B1 (ja) 2005-05-24 2005-05-24 配線回路基板

Publications (1)

Publication Number Publication Date
DE602006019994D1 true DE602006019994D1 (de) 2011-03-24

Family

ID=37026579

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006019994T Active DE602006019994D1 (de) 2005-05-24 2006-05-08 Leiterplatte

Country Status (5)

Country Link
US (1) US7288725B2 (de)
EP (1) EP1727407B1 (de)
JP (1) JP3828917B1 (de)
CN (1) CN100576968C (de)
DE (1) DE602006019994D1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4438006B2 (ja) * 2007-03-30 2010-03-24 Okiセミコンダクタ株式会社 半導体装置及び半導体装置の製造方法
JP2009206286A (ja) * 2008-02-27 2009-09-10 Kyocera Corp プリント基板及びこれを用いた携帯電子機器
US8766099B2 (en) * 2009-09-29 2014-07-01 Apple Inc. Component mounting structures for electronic devices
CN102148456B (zh) * 2010-12-06 2012-12-19 中国航空工业集团公司第六三一研究所 电连接器保护方法及其保护装置
JP5954075B2 (ja) * 2012-09-21 2016-07-20 ソニー株式会社 半導体装置及び半導体装置の製造方法
DE102015224422A1 (de) * 2015-12-07 2017-06-08 Robert Bosch Gmbh Elektronische Schaltungseinheit
KR102059478B1 (ko) 2017-09-15 2019-12-26 스템코 주식회사 회로 기판 및 그 제조 방법
US11282717B2 (en) 2018-03-30 2022-03-22 Intel Corporation Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap
CN113557798A (zh) * 2019-03-13 2021-10-26 株式会社自动网络技术研究所 带电子部件的柔性印刷基板及电池布线模块
JP2021012963A (ja) * 2019-07-08 2021-02-04 沖電気工業株式会社 プリント回路板及びその製造方法並びにプリント配線板
JP7493951B2 (ja) 2020-02-13 2024-06-03 イビデン株式会社 配線板及びその製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5218234A (en) * 1991-12-23 1993-06-08 Motorola, Inc. Semiconductor device with controlled spread polymeric underfill
JPH1032221A (ja) * 1996-07-12 1998-02-03 Nec Corp プリント配線基板
JP3032964B2 (ja) * 1996-12-30 2000-04-17 アナムインダストリアル株式会社 ボールグリッドアレイ半導体のパッケージ及び製造方法
JP2001244384A (ja) 2000-02-28 2001-09-07 Matsushita Electric Works Ltd ベアチップ搭載プリント配線基板
US6614122B1 (en) * 2000-09-29 2003-09-02 Intel Corporation Controlling underfill flow locations on high density packages using physical trenches and dams
KR20020069288A (ko) * 2001-02-24 2002-08-30 삼성전자 주식회사 봉합재 범람 방지홈이 형성된 테이프 배선기판을 이용한반도체 패키지 및 그의 제조 방법
JP2006041239A (ja) * 2004-07-28 2006-02-09 Toshiba Corp 配線基板及び磁気ディスク装置

Also Published As

Publication number Publication date
JP2006332203A (ja) 2006-12-07
CN1870856A (zh) 2006-11-29
CN100576968C (zh) 2009-12-30
US20060266545A1 (en) 2006-11-30
US7288725B2 (en) 2007-10-30
EP1727407A3 (de) 2008-06-11
EP1727407A2 (de) 2006-11-29
JP3828917B1 (ja) 2006-10-04
EP1727407B1 (de) 2011-02-09

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