DE3582828D1 - Dynamischer speicheraufbau mit segmentierten und quasi-gefalteten bitzeilen. - Google Patents

Dynamischer speicheraufbau mit segmentierten und quasi-gefalteten bitzeilen.

Info

Publication number
DE3582828D1
DE3582828D1 DE8585108720T DE3582828T DE3582828D1 DE 3582828 D1 DE3582828 D1 DE 3582828D1 DE 8585108720 T DE8585108720 T DE 8585108720T DE 3582828 T DE3582828 T DE 3582828T DE 3582828 D1 DE3582828 D1 DE 3582828D1
Authority
DE
Germany
Prior art keywords
segmented
quasi
bit lines
dynamic memory
memory structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585108720T
Other languages
English (en)
Inventor
David J Mcelroy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/634,899 external-priority patent/US4701885A/en
Priority claimed from US06/634,898 external-priority patent/US4658377A/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE3582828D1 publication Critical patent/DE3582828D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
DE8585108720T 1984-07-26 1985-07-12 Dynamischer speicheraufbau mit segmentierten und quasi-gefalteten bitzeilen. Expired - Lifetime DE3582828D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/634,899 US4701885A (en) 1984-07-26 1984-07-26 Dynamic memory array with quasi-folded bit lines
US06/634,898 US4658377A (en) 1984-07-26 1984-07-26 Dynamic memory array with segmented bit lines

Publications (1)

Publication Number Publication Date
DE3582828D1 true DE3582828D1 (de) 1991-06-20

Family

ID=27092256

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585108720T Expired - Lifetime DE3582828D1 (de) 1984-07-26 1985-07-12 Dynamischer speicheraufbau mit segmentierten und quasi-gefalteten bitzeilen.

Country Status (3)

Country Link
EP (1) EP0169460B1 (de)
JP (1) JPS63127490A (de)
DE (1) DE3582828D1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2246001B (en) * 1990-04-11 1994-06-15 Digital Equipment Corp Array architecture for high speed cache memory
JP3464803B2 (ja) * 1991-11-27 2003-11-10 株式会社東芝 半導体メモリセル
US5646893A (en) * 1995-09-07 1997-07-08 Advanced Micro Devices, Inc. Segmented read line circuit particularly useful for multi-port storage arrays
US7110319B2 (en) 2004-08-27 2006-09-19 Micron Technology, Inc. Memory devices having reduced coupling noise between wordlines

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57198592A (en) * 1981-05-29 1982-12-06 Hitachi Ltd Semiconductor memory device
JPS5873095A (ja) * 1981-10-23 1983-05-02 Toshiba Corp ダイナミツク型メモリ装置
JPS60234296A (ja) * 1984-05-07 1985-11-20 Hitachi Ltd 半導体記憶装置
JPS60253096A (ja) * 1984-05-30 1985-12-13 Fujitsu Ltd 半導体記憶装置

Also Published As

Publication number Publication date
EP0169460A3 (en) 1988-05-18
JPS63127490A (ja) 1988-05-31
EP0169460A2 (de) 1986-01-29
JPH0542077B2 (de) 1993-06-25
EP0169460B1 (de) 1991-05-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition