DE3581797D1 - Misfet mit niedrigdotiertem drain und verfahren zu seiner herstellung. - Google Patents
Misfet mit niedrigdotiertem drain und verfahren zu seiner herstellung.Info
- Publication number
- DE3581797D1 DE3581797D1 DE8585309209T DE3581797T DE3581797D1 DE 3581797 D1 DE3581797 D1 DE 3581797D1 DE 8585309209 T DE8585309209 T DE 8585309209T DE 3581797 T DE3581797 T DE 3581797T DE 3581797 D1 DE3581797 D1 DE 3581797D1
- Authority
- DE
- Germany
- Prior art keywords
- misfet
- production
- low
- doped drain
- doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/90—MOSFET type gate sidewall insulating spacer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59278225A JPS61154173A (ja) | 1984-12-27 | 1984-12-27 | Mis型半導体装置 |
JP5172185A JPH067556B2 (ja) | 1985-03-15 | 1985-03-15 | Mis型半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3581797D1 true DE3581797D1 (de) | 1991-03-28 |
Family
ID=26392281
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585309209T Expired - Lifetime DE3581797D1 (de) | 1984-12-27 | 1985-12-18 | Misfet mit niedrigdotiertem drain und verfahren zu seiner herstellung. |
Country Status (3)
Country | Link |
---|---|
US (1) | US4935379A (de) |
EP (1) | EP0187016B1 (de) |
DE (1) | DE3581797D1 (de) |
Families Citing this family (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61263137A (ja) * | 1985-05-07 | 1986-11-21 | Hitachi Ltd | 半導体装置 |
IT1201856B (it) * | 1986-11-10 | 1989-02-02 | Microelettronica Spa | Integrazione monolitica di transistori vdmos di poternza isolati ad alta prestazione e di transistori mos a canale p per alta tensione assieme a transistori csmo, npn, pnp e diodi a bassa perdita |
US5328976A (en) * | 1987-01-09 | 1994-07-12 | Allied-Signal Inc. | Carbon-containing black glass monoliths |
US5236867A (en) * | 1987-11-13 | 1993-08-17 | Matsushita Electronics Corporation | Manufacturing method of contact hole arrangement of a semiconductor device |
JPH01128568A (ja) * | 1987-11-13 | 1989-05-22 | Matsushita Electron Corp | 半導体装置 |
JPH01173756A (ja) * | 1987-12-28 | 1989-07-10 | Toshiba Corp | 半導体装置の製造方法 |
GB2215515A (en) * | 1988-03-14 | 1989-09-20 | Philips Electronic Associated | A lateral insulated gate field effect transistor and a method of manufacture |
JP2508818B2 (ja) * | 1988-10-03 | 1996-06-19 | 三菱電機株式会社 | 半導体装置の製造方法 |
US5170232A (en) * | 1989-08-24 | 1992-12-08 | Nec Corporation | MOS field-effect transistor with sidewall spacers |
JPH03155662A (ja) * | 1989-08-24 | 1991-07-03 | Nec Corp | Mos電界効果トランジスタ |
JPH0834313B2 (ja) * | 1989-10-09 | 1996-03-29 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6078079A (en) * | 1990-04-03 | 2000-06-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
KR950000141B1 (ko) * | 1990-04-03 | 1995-01-10 | 미쓰비시 뎅끼 가부시끼가이샤 | 반도체 장치 및 그 제조방법 |
JPH04206933A (ja) * | 1990-11-30 | 1992-07-28 | Nec Corp | 半導体装置 |
US5171700A (en) * | 1991-04-01 | 1992-12-15 | Sgs-Thomson Microelectronics, Inc. | Field effect transistor structure and method |
US5424234A (en) * | 1991-06-13 | 1995-06-13 | Goldstar Electron Co., Ltd. | Method of making oxide semiconductor field effect transistor |
KR100274555B1 (ko) * | 1991-06-26 | 2000-12-15 | 윌리엄 비. 켐플러 | 절연 게이트 전계 효과 트랜지스터 구조물 및 이의 제조 방법 |
EP0549055A3 (en) * | 1991-12-23 | 1996-10-23 | Koninkl Philips Electronics Nv | Method of manufacturing a semiconductor device provided with a field effect transistor, and such a semiconductor device |
US5432103A (en) * | 1992-06-22 | 1995-07-11 | National Semiconductor Corporation | Method of making semiconductor ROM cell programmed using source mask |
EP0789399B1 (de) * | 1993-01-12 | 2001-11-07 | Sony Corporation | Ausgangsschaltung für Ladungsübertragungselement |
US5994718A (en) * | 1994-04-15 | 1999-11-30 | National Semiconductor Corporation | Trench refill with selective polycrystalline materials |
KR970701932A (ko) * | 1995-01-17 | 1997-04-12 | 클라크 3세 존엠. | 고전압 nmos 장치의 개선된 수행을 위한 연장된 드레인 영역에 인과 비소의 공통 주입(co-implantation of arsenic and phosphorus in extended drain region for improved performance of high voltage nmos device) |
US6346439B1 (en) * | 1996-07-09 | 2002-02-12 | Micron Technology, Inc. | Semiconductor transistor devices and methods for forming semiconductor transistor devices |
EP0891635A1 (de) * | 1996-03-25 | 1999-01-20 | Advanced Micro Devices, Inc. | Verminderung des des umgekehrten kurz-kanal-effekts mit niedriger dosis aus p und hoher dosis aus a in n-kanal ldd |
KR100277911B1 (ko) * | 1996-06-10 | 2001-02-01 | 김영환 | 반도체소자 제조방법 |
US5668024A (en) * | 1996-07-17 | 1997-09-16 | Taiwan Semiconductor Manufacturing Company | CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation process |
US5874340A (en) * | 1996-07-17 | 1999-02-23 | Advanced Micro Devices, Inc. | Method for fabrication of a non-symmetrical transistor with sequentially formed gate electrode sidewalls |
US6051471A (en) * | 1996-09-03 | 2000-04-18 | Advanced Micro Devices, Inc. | Method for making asymmetrical N-channel and symmetrical P-channel devices |
US5677224A (en) * | 1996-09-03 | 1997-10-14 | Advanced Micro Devices, Inc. | Method of making asymmetrical N-channel and P-channel devices |
US5877050A (en) * | 1996-09-03 | 1999-03-02 | Advanced Micro Devices, Inc. | Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals |
US5648286A (en) * | 1996-09-03 | 1997-07-15 | Advanced Micro Devices, Inc. | Method of making asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region |
US20010003666A1 (en) * | 1996-09-27 | 2001-06-14 | Thomas C. Holloway | Lightly doped drain extension process to minimize source/drain resistance while maintaining hot carrier lifetime |
WO1998032176A1 (en) * | 1997-01-21 | 1998-07-23 | Advanced Micro Devices, Inc. | As/P HYBRID nLDD JUNCTION AND MEDIUM Vdd OPERATION FOR HIGH SPEED MICROPROCESSORS |
US6027978A (en) * | 1997-01-28 | 2000-02-22 | Advanced Micro Devices, Inc. | Method of making an IGFET with a non-uniform lateral doping profile in the channel region |
US5923982A (en) * | 1997-04-21 | 1999-07-13 | Advanced Micro Devices, Inc. | Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps |
US6004849A (en) * | 1997-08-15 | 1999-12-21 | Advanced Micro Devices, Inc. | Method of making an asymmetrical IGFET with a silicide contact on the drain without a silicide contact on the source |
US5904529A (en) * | 1997-08-25 | 1999-05-18 | Advanced Micro Devices, Inc. | Method of making an asymmetrical IGFET and providing a field dielectric between active regions of a semiconductor substrate |
US6096588A (en) * | 1997-11-01 | 2000-08-01 | Advanced Micro Devices, Inc. | Method of making transistor with selectively doped channel region for threshold voltage control |
JP3147847B2 (ja) * | 1998-02-24 | 2001-03-19 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US6576521B1 (en) * | 1998-04-07 | 2003-06-10 | Agere Systems Inc. | Method of forming semiconductor device with LDD structure |
US6187645B1 (en) * | 1999-01-19 | 2001-02-13 | United Microelectronics Corp. | Method for manufacturing semiconductor device capable of preventing gate-to-drain capacitance and eliminating birds beak formation |
TW451317B (en) * | 2000-03-24 | 2001-08-21 | Vanguard Int Semiconduct Corp | Manufacturing method of asymmetrical source/drain of DRAM cell |
US6911695B2 (en) * | 2002-09-19 | 2005-06-28 | Intel Corporation | Transistor having insulating spacers on gate sidewalls to reduce overlap between the gate and doped extension regions of the source and drain |
US6913980B2 (en) * | 2003-06-30 | 2005-07-05 | Texas Instruments Incorporated | Process method of source drain spacer engineering to improve transistor capacitance |
JP4408679B2 (ja) * | 2003-10-09 | 2010-02-03 | 三洋電機株式会社 | 半導体装置の製造方法 |
KR100575333B1 (ko) * | 2003-12-15 | 2006-05-02 | 에스티마이크로일렉트로닉스 엔.브이. | 플래쉬 메모리소자의 제조방법 |
CN102214696B (zh) * | 2011-05-27 | 2016-06-22 | 上海华虹宏力半导体制造有限公司 | 功率mos器件及功率mos器件制造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5232277A (en) * | 1975-09-05 | 1977-03-11 | Toshiba Corp | Insulated gate type field-effect transistor |
JPS5368581A (en) * | 1976-12-01 | 1978-06-19 | Hitachi Ltd | Semiconductor device |
DE2802838A1 (de) * | 1978-01-23 | 1979-08-16 | Siemens Ag | Mis-feldeffekttransistor mit kurzer kanallaenge |
US4402761A (en) * | 1978-12-15 | 1983-09-06 | Raytheon Company | Method of making self-aligned gate MOS device having small channel lengths |
US4735914A (en) * | 1979-03-28 | 1988-04-05 | Honeywell Inc. | FET for high reverse bias voltage and geometrical design for low on resistance |
US4514897A (en) * | 1979-09-04 | 1985-05-07 | Texas Instruments Incorporated | Electrically programmable floating gate semiconductor memory device |
DE2947350A1 (de) * | 1979-11-23 | 1981-05-27 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von mnos-speichertransistoren mit sehr kurzer kanallaenge in silizium-gate-technologie |
US4356623A (en) * | 1980-09-15 | 1982-11-02 | Texas Instruments Incorporated | Fabrication of submicron semiconductor devices |
US4442591A (en) * | 1982-02-01 | 1984-04-17 | Texas Instruments Incorporated | High-voltage CMOS process |
US4590663A (en) * | 1982-02-01 | 1986-05-27 | Texas Instruments Incorporated | High voltage CMOS technology with N-channel source/drain extensions |
JPS60136376A (ja) * | 1983-12-26 | 1985-07-19 | Hitachi Ltd | 半導体装置の製造方法 |
US4680603A (en) * | 1985-04-12 | 1987-07-14 | General Electric Company | Graded extended drain concept for reduced hot electron effect |
US4691433A (en) * | 1985-04-12 | 1987-09-08 | General Electric Company | Hybrid extended drain concept for reduced hot electron effect |
US4649629A (en) * | 1985-07-29 | 1987-03-17 | Thomson Components - Mostek Corp. | Method of late programming a read only memory |
US4703551A (en) * | 1986-01-24 | 1987-11-03 | Ncr Corporation | Process for forming LDD MOS/CMOS structures |
US4746624A (en) * | 1986-10-31 | 1988-05-24 | Hewlett-Packard Company | Method for making an LDD MOSFET with a shifted buried layer and a blocking region |
-
1985
- 1985-12-18 DE DE8585309209T patent/DE3581797D1/de not_active Expired - Lifetime
- 1985-12-18 EP EP85309209A patent/EP0187016B1/de not_active Expired
-
1989
- 1989-03-01 US US07/319,873 patent/US4935379A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0187016A2 (de) | 1986-07-09 |
US4935379A (en) | 1990-06-19 |
EP0187016A3 (en) | 1987-04-29 |
EP0187016B1 (de) | 1991-02-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8320 | Willingness to grant licences declared (paragraph 23) |