DE3484180D1 - Halbleiterspeicheranordnung. - Google Patents
Halbleiterspeicheranordnung.Info
- Publication number
- DE3484180D1 DE3484180D1 DE8484308634T DE3484180T DE3484180D1 DE 3484180 D1 DE3484180 D1 DE 3484180D1 DE 8484308634 T DE8484308634 T DE 8484308634T DE 3484180 T DE3484180 T DE 3484180T DE 3484180 D1 DE3484180 D1 DE 3484180D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor memory
- memory arrangement
- arrangement
- semiconductor
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
- G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/14—Dummy cell management; Sense reference voltage generators
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58234014A JPS60125998A (ja) | 1983-12-12 | 1983-12-12 | 半導体記憶装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE3484180D1 true DE3484180D1 (de) | 1991-04-04 |
Family
ID=16964199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE8484308634T Expired - Fee Related DE3484180D1 (de) | 1983-12-12 | 1984-12-12 | Halbleiterspeicheranordnung. |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4644501A (de) |
| EP (1) | EP0145488B1 (de) |
| JP (1) | JPS60125998A (de) |
| KR (1) | KR900006154B1 (de) |
| DE (1) | DE3484180D1 (de) |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6221357A (ja) * | 1985-07-22 | 1987-01-29 | Toshiba Corp | メモリシステム |
| US4727519A (en) * | 1985-11-25 | 1988-02-23 | Motorola, Inc. | Memory device including a clock generator with process tracking |
| US4819212A (en) * | 1986-05-31 | 1989-04-04 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device with readout test circuitry |
| JPS6378394A (ja) * | 1986-09-19 | 1988-04-08 | Fujitsu Ltd | プリチヤ−ジクロツク発生回路 |
| JPS6390096A (ja) * | 1986-10-01 | 1988-04-20 | Nec Corp | 半導体記憶装置 |
| JPS63108596A (ja) * | 1986-10-27 | 1988-05-13 | Nec Corp | 読み出し専用メモリ装置 |
| JPS63237296A (ja) * | 1987-03-25 | 1988-10-03 | Toshiba Corp | 半導体記憶装置 |
| US4845677A (en) * | 1987-08-17 | 1989-07-04 | International Business Machines Corporation | Pipelined memory chip structure having improved cycle time |
| JPH0775119B2 (ja) * | 1987-09-30 | 1995-08-09 | 日本電気株式会社 | 読出し専用メモリ |
| JPH0194592A (ja) * | 1987-10-06 | 1989-04-13 | Fujitsu Ltd | 半導体メモリ |
| JPH0642318B2 (ja) * | 1988-01-18 | 1994-06-01 | 株式会社東芝 | 半導体メモリ |
| KR930000963B1 (ko) * | 1988-03-09 | 1993-02-11 | 가부시기가이샤 도오시바 | 불휘발성 메모리 회로장치 |
| JPH0212693A (ja) * | 1988-06-30 | 1990-01-17 | Fujitsu Ltd | 半導体記憶装置 |
| US5018111A (en) * | 1988-12-27 | 1991-05-21 | Intel Corporation | Timing circuit for memory employing reset function |
| JPH02201797A (ja) * | 1989-01-31 | 1990-08-09 | Toshiba Corp | 半導体メモリ装置 |
| FR2656455B1 (fr) * | 1989-12-21 | 1992-03-13 | Bull Sa | Circuit de precharge d'un bus de memoire. |
| JP2573380B2 (ja) * | 1989-12-22 | 1997-01-22 | 株式会社東芝 | 不揮発性半導体メモリ |
| KR940005688B1 (ko) * | 1991-09-05 | 1994-06-22 | 삼성전자 주식회사 | 메모리 소자에 있어서 데이터 라인의 프리챠아지 자동 검사 장치 |
| JP2692596B2 (ja) * | 1994-07-19 | 1997-12-17 | 日本電気株式会社 | 記憶装置 |
| US5701269A (en) * | 1994-11-28 | 1997-12-23 | Fujitsu Limited | Semiconductor memory with hierarchical bit lines |
| KR0147706B1 (ko) * | 1995-06-30 | 1998-09-15 | 김주용 | 고속 동기형 마스크 롬 |
| DE69631821D1 (de) * | 1996-04-09 | 2004-04-15 | St Microelectronics Srl | Schaltung zur Bestimmung der vollständigen Aufladung einer generischen Bitleitung, insbesondere für nichtflüchtige Speicher |
| FR2755286B1 (fr) * | 1996-10-25 | 1999-01-22 | Sgs Thomson Microelectronics | Memoire a temps de lecture ameliore |
| JP5774458B2 (ja) * | 2011-12-02 | 2015-09-09 | 株式会社ソシオネクスト | 半導体メモリおよびシステム |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4045811A (en) * | 1975-08-04 | 1977-08-30 | Rca Corporation | Semiconductor integrated circuit device including an array of insulated gate field effect transistors |
| US4044341A (en) * | 1976-03-22 | 1977-08-23 | Rca Corporation | Memory array |
| US4207585A (en) * | 1976-07-01 | 1980-06-10 | Texas Instruments Incorporated | Silicon gate MOS ROM |
| US4192014A (en) * | 1978-11-20 | 1980-03-04 | Ncr Corporation | ROM memory cell with 2n FET channel widths |
| JPS5693363A (en) * | 1979-12-04 | 1981-07-28 | Fujitsu Ltd | Semiconductor memory |
| JPS6032917B2 (ja) * | 1980-03-10 | 1985-07-31 | 日本電気株式会社 | 半導体回路 |
| EP0052604A1 (de) * | 1980-06-02 | 1982-06-02 | Mostek Corporation | Vorladeschaltung für halbleiterspeicher |
| JPS57123596A (en) * | 1981-01-20 | 1982-08-02 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor storage circuit device |
-
1983
- 1983-12-12 JP JP58234014A patent/JPS60125998A/ja active Granted
-
1984
- 1984-12-10 US US06/680,125 patent/US4644501A/en not_active Expired - Fee Related
- 1984-12-12 KR KR1019840007845A patent/KR900006154B1/ko not_active IP Right Cessation
- 1984-12-12 DE DE8484308634T patent/DE3484180D1/de not_active Expired - Fee Related
- 1984-12-12 EP EP84308634A patent/EP0145488B1/de not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0145488A3 (en) | 1988-01-20 |
| JPH0140437B2 (de) | 1989-08-29 |
| US4644501A (en) | 1987-02-17 |
| EP0145488B1 (de) | 1991-02-27 |
| KR850004855A (ko) | 1985-07-27 |
| JPS60125998A (ja) | 1985-07-05 |
| EP0145488A2 (de) | 1985-06-19 |
| KR900006154B1 (ko) | 1990-08-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |