DE3483842D1 - Ausgangspufferschaltung. - Google Patents

Ausgangspufferschaltung.

Info

Publication number
DE3483842D1
DE3483842D1 DE8484103372T DE3483842T DE3483842D1 DE 3483842 D1 DE3483842 D1 DE 3483842D1 DE 8484103372 T DE8484103372 T DE 8484103372T DE 3483842 T DE3483842 T DE 3483842T DE 3483842 D1 DE3483842 D1 DE 3483842D1
Authority
DE
Germany
Prior art keywords
output buffer
buffer switching
switching
output
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484103372T
Other languages
English (en)
Inventor
Hiroshi Yasuda
Kiyofumi Ochii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3483842D1 publication Critical patent/DE3483842D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
DE8484103372T 1983-03-31 1984-03-27 Ausgangspufferschaltung. Expired - Lifetime DE3483842D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58056028A JPS59181829A (ja) 1983-03-31 1983-03-31 半導体素子の出力バツフア回路

Publications (1)

Publication Number Publication Date
DE3483842D1 true DE3483842D1 (de) 1991-02-07

Family

ID=13015607

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484103372T Expired - Lifetime DE3483842D1 (de) 1983-03-31 1984-03-27 Ausgangspufferschaltung.

Country Status (4)

Country Link
US (1) US4570091A (de)
EP (1) EP0121217B1 (de)
JP (1) JPS59181829A (de)
DE (1) DE3483842D1 (de)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4687954A (en) * 1984-03-06 1987-08-18 Kabushiki Kaisha Toshiba CMOS hysteresis circuit with enable switch or natural transistor
US4710648A (en) * 1984-05-09 1987-12-01 Hitachi, Ltd. Semiconductor including signal processor and transient detector for low temperature operation
EP0194939B1 (de) * 1985-03-14 1992-02-05 Fujitsu Limited Halbleiterspeicheranordnung
JPS6214520A (ja) * 1985-07-12 1987-01-23 Sony Corp メモリの出力バツフア回路
JPH0720060B2 (ja) * 1985-08-14 1995-03-06 株式会社東芝 出力回路装置
JPS62167698A (ja) * 1986-01-20 1987-07-24 Fujitsu Ltd 半導体記億装置
US4692635A (en) * 1986-06-26 1987-09-08 National Semiconductor Corp. Self-timed logic level transition detector
JPS63112893A (ja) * 1986-10-28 1988-05-17 Mitsubishi Electric Corp 半導体集積回路
FR2614743A1 (fr) * 1987-04-29 1988-11-04 Matra Harris Semiconducteurs Circuit integre numerique a prechargement
US4806794A (en) * 1987-07-22 1989-02-21 Advanced Micro Devices, Inc. Fast, low-noise CMOS output buffer
JPH0799639B2 (ja) * 1987-07-31 1995-10-25 株式会社東芝 半導体集積回路
JPH0817037B2 (ja) * 1987-12-03 1996-02-21 松下電子工業株式会社 スタティックｒａｍの出力回路
US4959816A (en) * 1987-12-28 1990-09-25 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
KR910002748B1 (ko) * 1988-04-12 1991-05-04 삼성 반도체통신 주식회사 반도체장치에 있어서 데이타 출력 버퍼회로
US4851720A (en) * 1988-09-02 1989-07-25 Cypress Semiconductor Corporation Low power sense amplifier for programmable logic device
US4965474A (en) * 1988-09-16 1990-10-23 Texas Instruments Incorporated Glitch suppression circuit
JP2754603B2 (ja) * 1988-10-14 1998-05-20 日本電気株式会社 メモリデータ出力回路
US5036223A (en) * 1989-05-22 1991-07-30 Kabushiki Kaisha Toshiba Inverter circuit and chopper type comparator circuit using the same
KR920000962B1 (ko) * 1989-05-26 1992-01-31 삼성전자 주식회사 반도체 메모리 장치의 데이터 출력단 전압레벨 조절회로
KR910005602B1 (ko) * 1989-06-15 1991-07-31 삼성전자 주식회사 어드레스 변환 검출에 따른 출력버퍼의 프리챠아지 제어방법
JPH03219495A (ja) * 1990-01-24 1991-09-26 Sony Corp 出力回路
JPH03268298A (ja) * 1990-03-16 1991-11-28 Fujitsu Ltd 半導体集積回路装置
IT1240012B (it) * 1990-04-27 1993-11-27 St Microelectronics Srl Stadio d'uscita dati, del tipo cosiddetto buffer,a ridotto rumore verso massa per circuiti logici di tipo cmos
US5241221A (en) * 1990-07-06 1993-08-31 North American Philips Corp., Signetics Div. CMOS driver circuit having reduced switching noise
JP2900559B2 (ja) * 1990-08-09 1999-06-02 日本電気株式会社 データ出力回路
JPH04150224A (ja) * 1990-10-15 1992-05-22 Internatl Business Mach Corp <Ibm> 集積回路
JP2690624B2 (ja) * 1991-01-30 1997-12-10 日本電気株式会社 バッファ回路
KR940010838B1 (ko) * 1991-10-28 1994-11-17 삼성전자 주식회사 데이타 출력 콘트롤 회로
US5331228A (en) * 1992-07-31 1994-07-19 Sgs-Thomson Microelectronics, Inc. Output driver circuit
JP2599196Y2 (ja) * 1992-09-14 1999-08-30 本田技研工業株式会社 車両のエンジンマウント
KR960006911B1 (ko) * 1992-12-31 1996-05-25 현대전자산업주식회사 데이타 출력버퍼
US5423030A (en) * 1993-09-13 1995-06-06 Unisys Corporation Bus station abort detection
DE4441523C1 (de) * 1994-11-22 1996-05-15 Itt Ind Gmbh Deutsche Digitale Treiberschaltung für eine integrierte Schaltung
JP2743878B2 (ja) * 1995-08-30 1998-04-22 日本電気株式会社 入力バッファ回路
US5633603A (en) * 1995-12-26 1997-05-27 Hyundai Electronics Industries Co., Ltd. Data output buffer using pass transistors biased with a reference voltage and a precharged data input
US5867038A (en) * 1996-12-20 1999-02-02 International Business Machines Corporation Self-timed low power ratio-logic system having an input sensing circuit
ITTO20010531A1 (it) * 2001-06-01 2002-12-01 St Microelectronics Srl Buffer di uscita per una memoria non volatile con controllo dello slew rate ottimizzato.
GB2416080A (en) * 2002-05-20 2006-01-11 Micron Technology Inc Increasing Drive Strength and reducing propagation delays through the use of feedback
US7741879B2 (en) * 2007-02-22 2010-06-22 Avago Technologies Enterprise IP (Singapore) Pte. Ltd. Apparatus and method for generating a constant logical value in an integrated circuit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3909631A (en) * 1973-08-02 1975-09-30 Texas Instruments Inc Pre-charge voltage generating system
US3937988A (en) * 1974-04-05 1976-02-10 Fairchild Camera And Instrument Corporation Active termination network for clamping a line signal
US3935476A (en) * 1974-12-13 1976-01-27 Mostek Corporation Combination output/input logic for integrated circuit
JPS5247365A (en) * 1975-10-13 1977-04-15 Mitsubishi Electric Corp Inverter circuit
US4208730A (en) * 1978-08-07 1980-06-17 Rca Corporation Precharge circuit for memory array
GB2070372B (en) * 1980-01-31 1983-09-28 Tokyo Shibaura Electric Co Semiconductor memory device
JPS57166733A (en) * 1981-04-06 1982-10-14 Matsushita Electric Ind Co Ltd Electronic circuit
US4498021A (en) * 1982-07-13 1985-02-05 Matsushita Electric Industrial Co., Ltd. Booster for transmitting digital signal
US4465945A (en) * 1982-09-03 1984-08-14 Lsi Logic Corporation Tri-state CMOS driver having reduced gate delay
US4488066A (en) * 1982-11-08 1984-12-11 At&T Bell Laboratories Databus coupling arrangement using transistors of complementary conductivity type

Also Published As

Publication number Publication date
EP0121217B1 (de) 1990-12-27
JPS59181829A (ja) 1984-10-16
EP0121217A2 (de) 1984-10-10
US4570091A (en) 1986-02-11
EP0121217A3 (en) 1987-01-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee