DE3177250D1 - Verfahren zur herstellung einer halbleiteranordnung mit dielektrischen isolationszonen. - Google Patents
Verfahren zur herstellung einer halbleiteranordnung mit dielektrischen isolationszonen.Info
- Publication number
- DE3177250D1 DE3177250D1 DE8686116670T DE3177250T DE3177250D1 DE 3177250 D1 DE3177250 D1 DE 3177250D1 DE 8686116670 T DE8686116670 T DE 8686116670T DE 3177250 T DE3177250 T DE 3177250T DE 3177250 D1 DE3177250 D1 DE 3177250D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- semiconductor arrangement
- dielectric insulation
- insulation zones
- zones
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9722380A JPS5723239A (en) | 1980-07-16 | 1980-07-16 | Manufacture of semiconductor device |
JP9722480A JPS5723240A (en) | 1980-07-16 | 1980-07-16 | Manufacture of semiconductor device |
JP16858280A JPS5791535A (en) | 1980-11-29 | 1980-11-29 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3177250D1 true DE3177250D1 (de) | 1991-08-14 |
Family
ID=27308349
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8686116670T Expired - Lifetime DE3177250D1 (de) | 1980-07-16 | 1981-07-14 | Verfahren zur herstellung einer halbleiteranordnung mit dielektrischen isolationszonen. |
DE8181105523T Expired DE3177018D1 (en) | 1980-07-16 | 1981-07-14 | Method of manufacturing a semiconductor device comprising a dielectric insulating region |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8181105523T Expired DE3177018D1 (en) | 1980-07-16 | 1981-07-14 | Method of manufacturing a semiconductor device comprising a dielectric insulating region |
Country Status (3)
Country | Link |
---|---|
US (1) | US4394196A (de) |
EP (2) | EP0245538B1 (de) |
DE (2) | DE3177250D1 (de) |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4532701A (en) * | 1981-08-21 | 1985-08-06 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of manufacturing semiconductor device |
US4563227A (en) * | 1981-12-08 | 1986-01-07 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing a semiconductor device |
JPS58132946A (ja) * | 1982-02-03 | 1983-08-08 | Toshiba Corp | 半導体装置の製造方法 |
JPS58165341A (ja) * | 1982-03-26 | 1983-09-30 | Toshiba Corp | 半導体装置の製造方法 |
JPS58171832A (ja) * | 1982-03-31 | 1983-10-08 | Toshiba Corp | 半導体装置の製造方法 |
JPS58210634A (ja) * | 1982-05-31 | 1983-12-07 | Toshiba Corp | 半導体装置の製造方法 |
FR2529714A1 (fr) * | 1982-07-01 | 1984-01-06 | Commissariat Energie Atomique | Procede de realisation de l'oxyde de champ d'un circuit integre |
US4444605A (en) * | 1982-08-27 | 1984-04-24 | Texas Instruments Incorporated | Planar field oxide for semiconductor devices |
JPS5943545A (ja) * | 1982-09-06 | 1984-03-10 | Hitachi Ltd | 半導体集積回路装置 |
JPS6088468A (ja) * | 1983-10-13 | 1985-05-18 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | 半導体集積装置の製造方法 |
US4609413A (en) * | 1983-11-18 | 1986-09-02 | Motorola, Inc. | Method for manufacturing and epitaxially isolated semiconductor utilizing etch and refill technique |
US4456501A (en) * | 1983-12-22 | 1984-06-26 | Advanced Micro Devices, Inc. | Process for dislocation-free slot isolations in device fabrication |
JPS6269520A (ja) * | 1985-09-21 | 1987-03-30 | Semiconductor Energy Lab Co Ltd | 光cvd法により凹部を充填する方法 |
US5462767A (en) * | 1985-09-21 | 1995-10-31 | Semiconductor Energy Laboratory Co., Ltd. | CVD of conformal coatings over a depression using alkylmetal precursors |
US4729006A (en) * | 1986-03-17 | 1988-03-01 | International Business Machines Corporation | Sidewall spacers for CMOS circuit stress relief/isolation and method for making |
FR2598557B1 (fr) * | 1986-05-09 | 1990-03-30 | Seiko Epson Corp | Procede de fabrication d'une region d'isolation d'element d'un dispositif a semi-conducteurs |
US4980311A (en) * | 1987-05-05 | 1990-12-25 | Seiko Epson Corporation | Method of fabricating a semiconductor device |
JPH0290617A (ja) * | 1988-09-28 | 1990-03-30 | Nec Corp | 半導体装置の製造方法 |
JPH05109762A (ja) * | 1991-05-16 | 1993-04-30 | Internatl Business Mach Corp <Ibm> | 半導体装置及びその製造方法 |
US5395790A (en) * | 1994-05-11 | 1995-03-07 | United Microelectronics Corp. | Stress-free isolation layer |
US5374583A (en) * | 1994-05-24 | 1994-12-20 | United Microelectronic Corporation | Technology for local oxidation of silicon |
US5577309A (en) * | 1995-03-01 | 1996-11-26 | Texas Instruments Incorporated | Method for forming electrical contact to the optical coating of an infrared detector |
KR0147630B1 (ko) * | 1995-04-21 | 1998-11-02 | 김광호 | 반도체 장치의 소자분리방법 |
US5725739A (en) * | 1996-07-08 | 1998-03-10 | Micron Technology, Inc. | Low angle, low energy physical vapor deposition of alloys |
JP3417767B2 (ja) * | 1996-08-29 | 2003-06-16 | 株式会社東芝 | 単結晶部品の製造方法 |
US6333274B2 (en) | 1998-03-31 | 2001-12-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device including a seamless shallow trench isolation step |
US6265282B1 (en) | 1998-08-17 | 2001-07-24 | Micron Technology, Inc. | Process for making an isolation structure |
JP2005008909A (ja) * | 2003-06-16 | 2005-01-13 | Canon Inc | 構造体の製造方法 |
KR101575818B1 (ko) * | 2009-08-18 | 2015-12-08 | 삼성전자주식회사 | 활성 영역 구조물의 형성방법 |
US8633077B2 (en) | 2012-02-15 | 2014-01-21 | International Business Machines Corporation | Transistors with uniaxial stress channels |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1461943A (en) * | 1973-02-21 | 1977-01-19 | Raytheon Co | Semi-conductor devices |
US4032373A (en) * | 1975-10-01 | 1977-06-28 | Ncr Corporation | Method of manufacturing dielectrically isolated semiconductive device |
US4104086A (en) * | 1977-08-15 | 1978-08-01 | International Business Machines Corporation | Method for forming isolated regions of silicon utilizing reactive ion etching |
US4139442A (en) * | 1977-09-13 | 1979-02-13 | International Business Machines Corporation | Reactive ion etching method for producing deep dielectric isolation in silicon |
US4140558A (en) * | 1978-03-02 | 1979-02-20 | Bell Telephone Laboratories, Incorporated | Isolation of integrated circuits utilizing selective etching and diffusion |
US4264382A (en) * | 1978-05-25 | 1981-04-28 | International Business Machines Corporation | Method for making a lateral PNP or NPN with a high gain utilizing reactive ion etching of buried high conductivity regions |
US4209350A (en) * | 1978-11-03 | 1980-06-24 | International Business Machines Corporation | Method for forming diffusions having narrow dimensions utilizing reactive ion etching |
US4209349A (en) * | 1978-11-03 | 1980-06-24 | International Business Machines Corporation | Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching |
US4255207A (en) * | 1979-04-09 | 1981-03-10 | Harris Corporation | Fabrication of isolated regions for use in self-aligning device process utilizing selective oxidation |
US4211582A (en) * | 1979-06-28 | 1980-07-08 | International Business Machines Corporation | Process for making large area isolation trenches utilizing a two-step selective etching technique |
US4252582A (en) * | 1980-01-25 | 1981-02-24 | International Business Machines Corporation | Self aligned method for making bipolar transistor having minimum base to emitter contact spacing |
US4318751A (en) * | 1980-03-13 | 1982-03-09 | International Business Machines Corporation | Self-aligned process for providing an improved high performance bipolar transistor |
US4274909A (en) * | 1980-03-17 | 1981-06-23 | International Business Machines Corporation | Method for forming ultra fine deep dielectric isolation |
US4307180A (en) * | 1980-08-22 | 1981-12-22 | International Business Machines Corp. | Process of forming recessed dielectric regions in a monocrystalline silicon substrate |
-
1981
- 1981-07-13 US US06/282,642 patent/US4394196A/en not_active Expired - Lifetime
- 1981-07-14 EP EP86116670A patent/EP0245538B1/de not_active Expired
- 1981-07-14 DE DE8686116670T patent/DE3177250D1/de not_active Expired - Lifetime
- 1981-07-14 DE DE8181105523T patent/DE3177018D1/de not_active Expired
- 1981-07-14 EP EP81105523A patent/EP0044082B1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
DE3177018D1 (en) | 1989-04-27 |
EP0044082A3 (en) | 1984-09-26 |
US4394196A (en) | 1983-07-19 |
EP0245538A2 (de) | 1987-11-19 |
EP0044082B1 (de) | 1989-03-22 |
EP0044082A2 (de) | 1982-01-20 |
EP0245538B1 (de) | 1991-07-10 |
EP0245538A3 (en) | 1988-02-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8320 | Willingness to grant licences declared (paragraph 23) |