DE3582453D1 - Verfahren zur herstellung einer dielektrischen isolation. - Google Patents
Verfahren zur herstellung einer dielektrischen isolation.Info
- Publication number
- DE3582453D1 DE3582453D1 DE8585105717T DE3582453T DE3582453D1 DE 3582453 D1 DE3582453 D1 DE 3582453D1 DE 8585105717 T DE8585105717 T DE 8585105717T DE 3582453 T DE3582453 T DE 3582453T DE 3582453 D1 DE3582453 D1 DE 3582453D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- dielectric insulation
- dielectric
- insulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000009413 insulation Methods 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/626,280 US4663832A (en) | 1984-06-29 | 1984-06-29 | Method for improving the planarity and passivation in a semiconductor isolation trench arrangement |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3582453D1 true DE3582453D1 (de) | 1991-05-16 |
Family
ID=24509729
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585105717T Expired - Fee Related DE3582453D1 (de) | 1984-06-29 | 1985-05-10 | Verfahren zur herstellung einer dielektrischen isolation. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4663832A (de) |
EP (1) | EP0166141B1 (de) |
JP (1) | JPS6115344A (de) |
DE (1) | DE3582453D1 (de) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6083346A (ja) * | 1983-10-14 | 1985-05-11 | Hitachi Ltd | 半導体集積回路装置 |
US4589193A (en) * | 1984-06-29 | 1986-05-20 | International Business Machines Corporation | Metal silicide channel stoppers for integrated circuits and method for making the same |
US4549927A (en) * | 1984-06-29 | 1985-10-29 | International Business Machines Corporation | Method of selectively exposing the sidewalls of a trench and its use to the forming of a metal silicide substrate contact for dielectric filled deep trench isolated devices |
US4811067A (en) * | 1986-05-02 | 1989-03-07 | International Business Machines Corporation | High density vertically structured memory |
US4983537A (en) * | 1986-12-29 | 1991-01-08 | General Electric Company | Method of making a buried oxide field isolation structure |
US4876214A (en) * | 1988-06-02 | 1989-10-24 | Tektronix, Inc. | Method for fabricating an isolation region in a semiconductor substrate |
US5106777A (en) * | 1989-09-27 | 1992-04-21 | Texas Instruments Incorporated | Trench isolation process with reduced topography |
JP2671529B2 (ja) * | 1989-11-28 | 1997-10-29 | 日本電気株式会社 | 半導体集積回路 |
FR2683944B1 (fr) * | 1991-11-14 | 1994-02-18 | Sgs Thomson Microelectronics Sa | Procede de gravure d'un sillon profond. |
US5561073A (en) * | 1992-03-13 | 1996-10-01 | Jerome; Rick C. | Method of fabricating an isolation trench for analog bipolar devices in harsh environments |
US5356513A (en) * | 1993-04-22 | 1994-10-18 | International Business Machines Corporation | Polishstop planarization method and structure |
BE1007588A3 (nl) * | 1993-09-23 | 1995-08-16 | Philips Electronics Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een halfgeleiderlichaam met veldisolatiegebieden gevormd door met isolerend materiaal gevulde groeven. |
JP2955459B2 (ja) * | 1993-12-20 | 1999-10-04 | 株式会社東芝 | 半導体装置の製造方法 |
US5681776A (en) * | 1994-03-15 | 1997-10-28 | National Semiconductor Corporation | Planar selective field oxide isolation process using SEG/ELO |
US5641705A (en) * | 1994-06-08 | 1997-06-24 | Samsung Electronics Co., Ltd. | Device isolation method of semiconductor device |
US5395786A (en) * | 1994-06-30 | 1995-03-07 | International Business Machines Corporation | Method of making a DRAM cell with trench capacitor |
EP0735580B1 (de) * | 1995-03-31 | 2004-11-17 | Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Verfahren zur Herstellung von Isolationsgraben |
US5712185A (en) * | 1996-04-23 | 1998-01-27 | United Microelectronics | Method for forming shallow trench isolation |
US6060728A (en) * | 1998-01-12 | 2000-05-09 | Fed Corporation | Organic light emitting device structure and process |
US6372601B1 (en) | 1998-09-03 | 2002-04-16 | Micron Technology, Inc. | Isolation region forming methods |
US6274498B1 (en) * | 1998-09-03 | 2001-08-14 | Micron Technology, Inc. | Methods of forming materials within openings, and method of forming isolation regions |
US6127215A (en) | 1998-10-29 | 2000-10-03 | International Business Machines Corp. | Deep pivot mask for enhanced buried-channel PFET performance and reliability |
US6277707B1 (en) | 1998-12-16 | 2001-08-21 | Lsi Logic Corporation | Method of manufacturing semiconductor device having a recessed gate structure |
US6869888B1 (en) * | 2001-07-11 | 2005-03-22 | Advanced Micro Devices, Inc. | E-beam flood exposure of spin-on material to eliminate voids in vias |
US7129149B1 (en) | 2004-06-07 | 2006-10-31 | Integrated Device Technology, Inc. | Method for forming shallow trench isolation structure with anti-reflective liner |
US7176104B1 (en) | 2004-06-08 | 2007-02-13 | Integrated Device Technology, Inc. | Method for forming shallow trench isolation structure with deep oxide region |
JP2009302222A (ja) * | 2008-06-12 | 2009-12-24 | Sanyo Electric Co Ltd | メサ型半導体装置及びその製造方法 |
JP2010021532A (ja) * | 2008-06-12 | 2010-01-28 | Sanyo Electric Co Ltd | メサ型半導体装置及びその製造方法 |
US10665665B2 (en) | 2018-10-22 | 2020-05-26 | Micron Technology, Inc. | Passivation material for a pillar adjacent a trench |
CN110491833B (zh) * | 2019-08-30 | 2021-12-03 | 上海华力微电子有限公司 | 金属互连线填充方法 |
EP3813101A1 (de) * | 2019-10-25 | 2021-04-28 | Ams Ag | Verfahren zur herstellung eines halbleiterkörpers mit einem graben, halbleiterkörper mit mindestens einem graben und halbleitervorrichtung |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US433794A (en) * | 1890-08-05 | Wrench | ||
FR2358748A1 (fr) * | 1976-07-15 | 1978-02-10 | Radiotechnique Compelec | Procede d'autoalignement des elements d'un dispositif semi-conducteur et dispositif realise suivant ce procede |
US4238278A (en) * | 1979-06-14 | 1980-12-09 | International Business Machines Corporation | Polycrystalline silicon oxidation method for making shallow and deep isolation trenches |
US4271583A (en) * | 1980-03-10 | 1981-06-09 | Bell Telephone Laboratories, Incorporated | Fabrication of semiconductor devices having planar recessed oxide isolation region |
DE3174468D1 (en) * | 1980-09-17 | 1986-05-28 | Hitachi Ltd | Semiconductor device and method of manufacturing the same |
DE3170644D1 (en) * | 1980-11-29 | 1985-06-27 | Toshiba Kk | Method of filling a groove in a semiconductor substrate |
JPS57170548A (en) * | 1981-04-13 | 1982-10-20 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
US4493740A (en) * | 1981-06-01 | 1985-01-15 | Matsushita Electric Industrial Company, Limited | Method for formation of isolation oxide regions in semiconductor substrates |
JPS57204133A (en) * | 1981-06-10 | 1982-12-14 | Hitachi Ltd | Manufacture of semiconductor integrated circuit |
US4466180A (en) * | 1981-06-25 | 1984-08-21 | Rockwell International Corporation | Method of manufacturing punch through voltage regulator diodes utilizing shaping and selective doping |
US4563227A (en) * | 1981-12-08 | 1986-01-07 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing a semiconductor device |
DE3242113A1 (de) * | 1982-11-13 | 1984-05-24 | Ibm Deutschland Gmbh, 7000 Stuttgart | Verfahren zur herstellung einer duennen dielektrischen isolation in einem siliciumhalbleiterkoerper |
JPS60851A (ja) * | 1983-06-17 | 1985-01-05 | Hitachi Koki Co Ltd | 遠心機の制御回路 |
US4589193A (en) * | 1984-06-29 | 1986-05-20 | International Business Machines Corporation | Metal silicide channel stoppers for integrated circuits and method for making the same |
-
1984
- 1984-06-29 US US06/626,280 patent/US4663832A/en not_active Expired - Lifetime
-
1985
- 1985-04-16 JP JP60079461A patent/JPS6115344A/ja active Granted
- 1985-05-10 EP EP85105717A patent/EP0166141B1/de not_active Expired - Lifetime
- 1985-05-10 DE DE8585105717T patent/DE3582453D1/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0166141A3 (en) | 1988-09-28 |
US4663832A (en) | 1987-05-12 |
JPS6115344A (ja) | 1986-01-23 |
EP0166141A2 (de) | 1986-01-02 |
EP0166141B1 (de) | 1991-04-10 |
JPH0526337B2 (de) | 1993-04-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |