JPS5723239A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5723239A
JPS5723239A JP9722380A JP9722380A JPS5723239A JP S5723239 A JPS5723239 A JP S5723239A JP 9722380 A JP9722380 A JP 9722380A JP 9722380 A JP9722380 A JP 9722380A JP S5723239 A JPS5723239 A JP S5723239A
Authority
JP
Japan
Prior art keywords
substrate
oxide film
field oxide
vertical grooves
cvdsio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9722380A
Other languages
Japanese (ja)
Other versions
JPS6119111B2 (en
Inventor
Hiroshi Iwai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9722380A priority Critical patent/JPS5723239A/en
Priority to US06/282,642 priority patent/US4394196A/en
Priority to EP86116670A priority patent/EP0245538B1/en
Priority to EP81105523A priority patent/EP0044082B1/en
Priority to DE8181105523T priority patent/DE3177018D1/en
Priority to DE8686116670T priority patent/DE3177250D1/en
Publication of JPS5723239A publication Critical patent/JPS5723239A/en
Publication of JPS6119111B2 publication Critical patent/JPS6119111B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To make a highly integrated and efficient device, by providing a wide field oxide film which self-aligns with vertical grooves provided on a main surface of an Si substrate, whose surface is on the same level with the substrate main surface. CONSTITUTION:A resist mask 102 is provided on a P type Si substrate 101, and vertical grooves are provided adjacent to each other by reactive ion etching, and ions are injected to make a P<+> layer 104. Then, the mask 102 is removed, and a CVDSiO2 105 is formed which is thicker than half of te groove's opening width, and etched down to the surface of the substrate. An element forming regin is covered with a resist mask 106 to form vertical grooves 17 by reactive ion etching, and a P<+> layer 104 is formed by injecting ions, thus a channel stopper is completed. Then, After a CVDSiO2 108 of the same thickness has been formed, a field oxide film 109 is completed by etching down to the surface. Said method provides a highly integrated and efficient device without producing any iregularities on the field oxide film end.
JP9722380A 1980-07-16 1980-07-16 Manufacture of semiconductor device Granted JPS5723239A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP9722380A JPS5723239A (en) 1980-07-16 1980-07-16 Manufacture of semiconductor device
US06/282,642 US4394196A (en) 1980-07-16 1981-07-13 Method of etching, refilling and etching dielectric grooves for isolating micron size device regions
EP86116670A EP0245538B1 (en) 1980-07-16 1981-07-14 Method for manufacturing a semiconductor device comprising dielectric isolation regions
EP81105523A EP0044082B1 (en) 1980-07-16 1981-07-14 Method of manufacturing a semiconductor device comprising a dielectric insulating region
DE8181105523T DE3177018D1 (en) 1980-07-16 1981-07-14 Method of manufacturing a semiconductor device comprising a dielectric insulating region
DE8686116670T DE3177250D1 (en) 1980-07-16 1981-07-14 METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT WITH DIELECTRIC INSULATION ZONES.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9722380A JPS5723239A (en) 1980-07-16 1980-07-16 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5723239A true JPS5723239A (en) 1982-02-06
JPS6119111B2 JPS6119111B2 (en) 1986-05-15

Family

ID=14186628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9722380A Granted JPS5723239A (en) 1980-07-16 1980-07-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5723239A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6034034A (en) * 1983-08-05 1985-02-21 Hitachi Ltd Semiconductor device
JPH02272745A (en) * 1989-04-14 1990-11-07 Nec Corp Semiconductor device
US6426305B1 (en) 2001-07-03 2002-07-30 International Business Machines Corporation Patterned plasma nitridation for selective epi and silicide formation
JP2005303253A (en) * 2004-03-18 2005-10-27 Fuji Electric Device Technology Co Ltd Manufacturing method of semiconductor device
US8420453B2 (en) 2009-08-18 2013-04-16 Samsung Electronics Co., Ltd. Method of forming active region structure

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6034034A (en) * 1983-08-05 1985-02-21 Hitachi Ltd Semiconductor device
JPH02272745A (en) * 1989-04-14 1990-11-07 Nec Corp Semiconductor device
US6426305B1 (en) 2001-07-03 2002-07-30 International Business Machines Corporation Patterned plasma nitridation for selective epi and silicide formation
JP2005303253A (en) * 2004-03-18 2005-10-27 Fuji Electric Device Technology Co Ltd Manufacturing method of semiconductor device
US8420453B2 (en) 2009-08-18 2013-04-16 Samsung Electronics Co., Ltd. Method of forming active region structure

Also Published As

Publication number Publication date
JPS6119111B2 (en) 1986-05-15

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