DE102012106566A1 - Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche - Google Patents
Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche Download PDFInfo
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- DE102012106566A1 DE102012106566A1 DE102012106566A DE102012106566A DE102012106566A1 DE 102012106566 A1 DE102012106566 A1 DE 102012106566A1 DE 102012106566 A DE102012106566 A DE 102012106566A DE 102012106566 A DE102012106566 A DE 102012106566A DE 102012106566 A1 DE102012106566 A1 DE 102012106566A1
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- metal layer
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- power semiconductor
- load electrode
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Abstract
Ein Halbleiterchip beinhaltet eine Leistungstransistorschaltung mit mehreren aktiven Transistorzellen. Eine erste Lastelektrode und eine Steuerelektrode sind auf einer ersten Fläche des Halbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht beinhaltet. Eine zweite Lastelektrode ist auf einer zweiten Fläche des Halbleiterchips angeordnet. Eine zweite Metallschicht ist über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht elektrisch gegenüber der Leistungstransistorschaltung isoliert ist und die zweite Metallschicht über einen Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst.
Description
- Die vorliegende Erfindung betrifft einen Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche des Leistungshalbleiterchips.
- Ein Leistungshalbleiterchip ist eine spezifische Art von Halbleiterchip, der so ausgelegt ist, dass er signifikante Leistungsniveaus verarbeiten kann. Leistungshalbleiterchips eignen sich insbesondere für das Schalten oder Steuern von Strömen und/oder Spannungen. Sie können als Leistungs-MOSFETs, IGBTs, JFETs oder Leistungsbipolartransistoren implementiert werden. Leistungshalbleiterchips findet man in den meisten Stromversorgungen, DC-DC-Wandlern und Motorsteuerungen.
- Die beiliegenden Zeichnungen sind aufgenommen, um ein eingehenderes Verständnis von Ausführungsformen zu übermitteln, und sind in diese Beschreibung aufgenommen und stellen einen Teil dieser dar. Die Zeichnungen veranschaulichen Ausführungsformen und dienen zusammen mit der Beschreibung der Erläuterung von Prinzipien von Ausführungsformen. Andere Ausführungsformen und viele der beabsichtigten Vorteile von Ausführungsformen sind ohne weiteres ersichtlich, wenn sie durch Bezugnahme auf die folgende ausführliche Beschreibung besser verstanden werden. Die Elemente der Zeichnungen sind relativ zueinander nicht notwendigerweise maßstabsgetreu. Gleiche Bezugszeichen bezeichnen entsprechende ähnliche Teile.
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1 zeigt schematisch eine Querschnittsansicht und eine Draufsicht auf eine Ausführungsform eines Halbleiterchips mit einer Leistungstransistorschaltung mit zwei Metallschichten, die über aktiven Transistorzellen abgeschieden sind; -
2 zeigt schematisch eine Querschnittsansicht einer Ausführungsform einer Transistorzelle; -
3A –3F zeigen schematisch eine Querschnittsansicht und eine Draufsicht auf eine Ausführungsform eines Verfahrens zum Herstellen eines Bauelements (oder einer Vorrichtung), einschließlich Montieren eines ersten Leistungshalbleiterchips auf einem Systemträger (engl. leadframe) und Stapeln eines zweiten Leistungshalbleiterchips auf dem ersten Leistungshalbleiterchip; -
4 zeigt schematisch eine Querschnittsansicht einer Ausführungsform eines Bauelements mit zwei auf einem Systemträger gestapelten Leistungshalbleiterchips und Bonddrähten, die die beiden Leistungshalbleiterchips elektrisch an den Systemträger koppeln; -
5 zeigt schematisch eine Querschnittsansicht einer Ausführungsform eines Systems mit einem auf einer Leiterplatte (engl. circuit board) montierten Halbleiterbauelement; und -
6 zeigt eine schematische Basisschaltung einer Halbbrückenschaltung. - In der folgenden ausführlichen Beschreibung wird auf die beiliegenden Zeichnungen Bezug genommen, die einen Teil hiervon bilden und in denen als Veranschaulichung spezifische Ausführungsformen gezeigt sind, in denen die Erfindung praktiziert werden kann. In dieser Hinsicht wird Richtungsterminologie wie etwa „Oberseite“, „Unterseite“, „Vorderseite“, „Rückseite“, „vorderer“, „hinterer“ usw. unter Bezugnahme auf die Orientierung der beschriebenen Figur(en) verwendet. Da Komponenten von Ausführungsformen in einer Reihe verschiedener Orientierungen positioniert sein können, wird die Richtungsterminologie zu Zwecken der Darstellung verwendet und ist in keinerlei Weise beschränkend. Es versteht sich, dass andere Ausführungsformen genutzt und strukturelle oder logische Änderungen vorgenommen werden können, ohne von dem Konzept der vorliegenden Erfindung abzuweichen. Die folgende ausführliche Beschreibung ist deshalb nicht in einem beschränkenden Sinne zu verstehen, und das Konzept der vorliegenden Erfindung wird durch die beigefügten Ansprüche definiert.
- Es versteht sich, dass die Merkmale der verschiedenen hierin beschriebenen Ausführungsbeispiele miteinander kombiniert werden können, sofern nicht spezifisch etwas anderes angegeben ist.
- Die Ausdrücke „gekoppelt“ und/oder „elektrisch gekoppelt“ sollen, wie sie in dieser Beschreibung verwendet werden, nicht bedeuten, dass die Elemente direkt zusammengekoppelt sein müssen; dazwischenliegende Elemente können zwischen den „gekoppelten“ oder „elektrisch gekoppelten“ Elementen vorgesehen sein.
- Bauelemente, die einen oder mehrere Halbleiterchips enthalten, sind unten beschrieben. Die Halbleiterchips können von verschiedenen Arten sein, können durch unterschiedliche Technologien hergestellt sein und können beispielsweise integrierte elektrische, elektrooptische oder elektromechanische Schaltungen oder passive Elemente enthalten. Die integrierten Schaltungen können beispielsweise als integrierte Logikschaltungen, integrierte Analogschaltungen, integrierte Mischsignalschaltungen, integrierte Leistungsschaltungen, Speicherschaltungen oder integrierte passive Elemente ausgelegt sein. Weiterhin können die Halbleiterchips als sogenannte MEMS (Micro-Electro Mechanical Systems – mikroelektromechanische Systeme) konfiguriert sein und können mikromechanische Strukturen wie etwa Brücken, Membranen oder Zungenstrukturen enthalten. Die Halbleiterchips können als Sensoren oder Aktuatoren konfiguriert sein, beispielsweise Drucksensoren, Beschleunigungssensoren, Rotationssensoren, Magnetfeldsensoren, Sensoren für elektromagnetische Felder, Mikrofone usw. Die Halbleiterchips brauchen nicht aus einem spezifischen Halbleitermaterial hergestellt zu sein, beispielsweise Si, SiC, SiGe, GaAs, und können darüber hinaus anorganische und/oder organische Materialien enthalten, die keine Halbleiter sind, wie etwa beispielsweise Isolatoren, Kunststoffe oder Metalle. Außerdem können die Halbleiterchips gekapselt (engl. packaged) oder ungekapselt sein.
- Insbesondere können Halbleiterchips mit einer vertikalen Struktur involviert sein, das heißt, die Halbleiterchips können derart hergestellt sein, dass elektrische Ströme in einer Richtung senkrecht zu den Hauptflächen der Halbleiterchips fließen können. Ein Halbleiterchip mit einer vertikalen Struktur weist Elektroden auf seinen beiden Hauptflächen auf, das heißt auf seiner Oberseite und Unterseite. Insbesondere können Leistungshalbleiterchips eine vertikale Struktur aufweisen. Die vertikalen Leistungshalbleiterchips können beispielsweise als Leistungs-MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Gate Field Effect Transistors) oder Leistungsbipolartransistoren konfiguriert sein. Beispielhaft können sich die Source-Elektrode und Gate-Elektrode eines Leistungs-MOSFET auf einer Hauptfläche befinden, während die Drain-Elektrode des Leistungs-MOSFET auf der anderen Hauptfläche angeordnet ist. Weiterhin können die unten beschriebenen Bauelemente integrierte Schaltungen zum Steuern der integrierten Schaltungen von Leistungshalbleiterchips enthalten.
- Die Halbleiterchips können Elektroden (oder Kontaktelemente oder Kontaktpads) aufweisen, die das Herstellen eines elektrischen Kontakts mit den in den Halbleiterchips enthaltenen integrierten Schaltungen gestatten. Die Elektroden können eine oder mehrere Metallschichten enthalten, die auf das Halbleitersubstrat aufgebracht sind. Die Metallschichten können mit einer beliebigen gewünschten geometrischen Gestalt und einer beliebigen gewünschten Materialzusammensetzung hergestellt werden. Die Metallschichten können beispielsweise in Form einer einen Bereich bedeckenden Schicht vorliegen. Als das Material kann ein beliebiges gewünschtes Metall oder eine beliebige gewünschte Metalllegierung, beispielsweise Aluminium, Titan, Gold, Silber, Kupfer, Palladium, Platin, Nickel, Chrom oder Nickel-Vanadium, verwendet werden. Die Metallschichten brauchen nicht homogen zu sein oder aus nur einem Material hergestellt zu sein, das heißt, verschiedene Zusammensetzungen und Konzentrationen der in den Metallschichten enthaltenen Materialien sind möglich.
- Die Halbleiterchips können auf Systemträgern (engl. leadframes) platziert werden. Die Systemträger können von beliebiger Gestalt oder Größe sein und aus einem beliebigen Material bestehen. Die Systemträger können Die-Pads und Zuleitungen (engl. leads) enthalten. Während der Herstellung der Bauelemente können die Die-Pads und die Zuleitungen miteinander verbunden werden. Die Die-Pads und Zuleitungen können auch aus einem Stück hergestellt werden. Die Die-Pads und Zuleitungen können untereinander durch Verbindungsmittel verbunden werden mit dem Zweck, einige der Die-Pads und Zuleitungen im Verlauf der Herstellung zu trennen. Das Trennen der Die-Pads und Zuleitungen kann durch mechanisches Sägen, einen Laserstrahl, Schneiden, Stanzen, Fräsen, Ätzen oder ein beliebiges anderes angebrachtes Verfahren ausgeführt werden. Die Systemträger können elektrisch leitend sein. Sie können ganz aus Metallen oder Metalllegierungen hergestellt sein, insbesondere Kupfer, Kupferlegierungen, Eisen-Nickel, Aluminium, Aluminiumlegierungen, Stahl, rostfreiem Stahl oder anderen angemessenen Materialien. Die Systemträger können mit einem elektrisch leitenden Material plattiert sein, beispielsweise Kupfer, Silber, Eisen-Nickel oder Nickelphosphor. Die Zuleitungen der Systemträger können während der Fabrikation beispielsweise auf S-förmige Weise gebogen werden.
- Die unten beschriebenen Bauelemente enthalten externe Kontaktelemente (oder externe Kontaktpads), die von beliebiger Gestalt und Größe sein können. Die externen Kontaktelemente können von außerhalb des Bauelements zugänglich sein und können somit das Herstellen eines elektrischen Kontakts mit den Halbleiterchips von außerhalb des Bauelements gestatten. Aus diesem Grund können die externen Kontaktelemente externe Kontaktoberflächen aufweisen, auf die von außerhalb des Bauelements zugegriffen werden kann. Weiterhin können die externen Kontaktelemente wärmeleitend sein und als Kühlkörper (oder Wärmesenke) zum Ableiten der von den Halbleiterchips erzeugten Wärme dienen. Die externen Kontaktelemente können aus einem beliebigen gewünschten, elektrisch leitenden Material bestehen, beispielsweise aus einem Metall wie etwa Kupfer, Aluminium oder Gold, einer Metalllegierung oder aus einem elektrisch leitenden organischen Material. Die externen Kontaktelemente können Zuleitungen eines Systemträgers sein.
- Die Bauelemente können ein Kapselungsmaterial enthalten, beispielsweise ein mindestens Teile der Komponenten der Bauelemente bedeckendes Formmaterial (oder Vergussmaterial, engl. mold material). Das Formmaterial kann ein beliebiges angemessenes thermoplastisches oder wärmehärtendes Material sein. Verschiedene Techniken können verwendet werden, um die Komponenten mit dem Formmaterial zu bedecken, beispielsweise Formpressen, Spritzgießen, Pulversintern oder Liquid Molding.
-
1 zeigt schematisch einen Leistungshalbleiterchip10 in einer Draufsicht (unten) und einer Querschnittsansicht (oben) entlang einer in der Draufsicht gezeigten Linie A-A‘. Der Leistungshalbleiterchip10 weist eine erste Fläche11 und eine zweite Fläche12 gegenüber der ersten Fläche11 auf. Der Leistungshalbleiterchip10 enthält ein Halbleitersubstrat13 und eine Leistungstransistorschaltung, die in das Halbleitersubstrat13 integriert ist und mehrere aktive Transistorzellen14 enthält. Außerdem enthält der Leistungshalbleiterchip10 eine erste Lastelektrode15 (engl. load electrode) und eine auf der ersten Fläche11 angeordnete Steuerelektrode16 und eine auf der zweiten Fläche12 angeordnete zweite Lastelektrode17 . Die erste Lastelektrode15 enthält eine erste Metallschicht18 . Eine zweite Metallschicht19 ist über der ersten Metallschicht18 angeordnet und ist elektrisch von der Leistungstransistorschaltung isoliert. Weiterhin ist die zweite Metallschicht19 über einem Bereich20 der Leistungstransistorschaltung angeordnet, die eine oder mehrere der aktiven Transistorzellen14 enthält. Mit anderen Worten befinden sich eine oder mehrere der aktiven Transistorzellen14 innerhalb einer Projektion der zweiten Metallschicht19 auf das Halbleitersubstrat13 orthogonal zu der ersten Fläche11 . - Bei einer Ausführungsform weist die erste Metallschicht
18 einen ersten Abschnitt21 mit einer ersten Dicke d1 auf, die kleiner ist als eine zweite Dicke d2 eines zweiten Abschnitts22 der ersten Metallschicht18 . Die erste Dicke d1 liegt im Bereich von 1 bis 10 mm (Mikrometer) und insbesondere im Bereich von 5 bis 10 mm (Mikrometer). Die zweite Dicke d2 liegt im Bereich von 5 bis 15 mm (Mikrometer), und insbesondere im Bereich von 10 bis 15 mm (Mikrometer). Bei einer Ausführungsform liegt die Differenz d2 – d1 der beiden Dicken d1 und d2 im - Bereich von 3 bis 8 mm (Mikrometer) und insbesondere im Bereich von 4 bis 6 mm (Mikrometer).
- Die erste Metallschicht
18 kann eine oder mehrere Metallschichten enthalten, die auf das Halbleitersubstrat13 aufgebracht sind. Als das Material kann ein beliebiges gewünschtes Metall oder eine beliebige gewünschte Metalllegierung, beispielsweise Aluminium, Nickel oder Kupfer, verwendet werden. Die erste Metallschicht18 braucht nicht homogen oder aus nur einem Material hergestellt zu sein, das heißt, verschiedene Zusammensetzungen und Konzentrationen der in der ersten Metallschicht18 enthaltenen Materialien sind möglich. - Eine Dielektrikumsschicht
23 ist auf der ersten Metallschicht18 abgeschieden. Bei einer Ausführungsform bedeckt die Dielektrikumsschicht23 die ganze erste Metallschicht18 , lässt aber eine obere Oberfläche des zweiten Abschnitts22 der ersten Metallschicht18 exponiert (oder freiliegend). Die Dielektrikumsschicht23 ist aus einem angemessenen, elektrisch isolierenden Material hergestellt, beispielsweise Siliziumoxid, Siliziumnitrid oder einem organischen Material. Die Dielektrikumsschicht23 weist eine Dicke d3 über dem ersten Abschnitt21 der ersten Metallschicht18 in dem Bereich von 0,5 bis 5 mm (Mikrometer) und insbesondere im Bereich von 2 bis 3 mm (Mikrometer) auf. Die Dielektrikumsschicht23 isoliert die erste Metallschicht18 elektrisch von der zweiten Metallschicht19 . - Die zweite Metallschicht
19 ist über dem ersten Abschnitt21 der ersten Metallschicht18 aufgebracht. Bei einer Ausführungsform weist die zweite Metallschicht19 eine Dicke d4 im Bereich von 1 bis 10 mm (Mikrometer) und insbesondere im Bereich von 5 bis 10 mm (Mikrometer) auf. Für die zweite Metallschicht19 kann ein beliebiges gewünschtes Metall oder eine beliebige gewünschte Metalllegierung, beispielsweise Aluminium, Nickel oder Kupfer, verwendet werden. Die zweite Metallschicht19 braucht nicht homogen oder aus nur einem Material hergestellt sein, das heißt, verschiedene Zusammensetzungen und Konzentrationen der in der zweiten Metallschicht19 enthaltenen Materialien sind möglich. - Bei einer Ausführungsform wird eine Passivierungsschicht
25 über der Dielektrikumsschicht23 abgeschieden. Die Passivierungsschicht25 lässt zumindest Abschnitte (oder Teile) der oberen Oberflächen des zweiten Abschnitts22 der ersten Metallschicht18 , der zweiten Metallschicht19 und der Steuerelektrode16 exponiert (oder freiliegend). Die Passivierungsschicht25 besteht aus einem angebrachten elektrisch isolierenden Material, beispielsweise Siliziumoxid, Siliziumnitrid oder einem organischen Material. Da die Passivierungsschicht25 die obere Oberfläche des zweiten Abschnitts22 der ersten Metallschicht18 und die obere Oberfläche der zweiten Metallschicht19 überlappt, ist der Kriechabstand (engl. creepage distance) zwischen der ersten Metallschicht18 und der zweiten Metallschicht19 vergrößert. - Die Steuerelektrode
16 und die zweite Lastelektrode17 können eine oder mehrere Metallschichten enthalten, die auf das Halbleitersubstrat13 (in1 nicht gezeigt) aufgebracht sind. Die Metallschichten können mit einer beliebigen gewünschten geometrischen Gestalt und einer beliebigen gewünschten Materialzusammensetzung hergestellt werden. Als das Material kann ein beliebiges gewünschtes Metall oder eine beliebige gewünschte Metalllegierung, beispielsweise Aluminium, Titan, Gold, Silber, Kupfer, Palladium, Platin, Nickel, Chrom oder Nickel-Vanadium, verwendet werden. - Der Leistungshalbleiterchip
10 ist als ein Leistungstransistor konfiguriert, beispielsweise ein Leistungs-MOSFET, IGBT, JFET oder ein Leistungsbipolartransistor. Im Fall eines Leistungs-MOSFET oder eines JFET ist die erste Lastelektrode15 eine Source-Elektrode, die zweite Lastelektrode17 ist eine Drain-Elektrode und die Steuerelektrode16 ist eine Gate-Elektrode. Im Fall eines IGBT ist die erste Lastelektrode15 eine Emitterelektrode, die zweite Lastelektrode17 ist eine Kollektorelektrode und die Steuerelektrode16 ist eine Gate-Elektrode. Im Fall eines Leistungsbipolartransistors ist die erste Lastelektrode15 eine Emitterelektrode, die zweite Lastelektrode17 ist eine Kollektorelektrode und die Steuerelektrode16 ist eine Basiselektrode. Während des Betriebs können Spannungen über 5, 50, 100, 500 oder 1000 V zwischen der ersten und zweiten Lastelektrode15 ,17 angelegt werden. Die an die Steuerelektrode16 angelegte Schaltfrequenz kann im Bereich von 1 kHz bis 100 MHz liegen, kann aber auch außerhalb dieses Bereichs liegen. -
2 zeigt schematisch eine Querschnittsansicht einer aktiven Transistorzelle14 , wie in dem Halbleitersubstrat13 des Leistungshalbleiterchips10 enthalten. Die in2 gezeigte Transistorzelle14 ist eine VDMOS-Zelle (Vertical Diffused MOS). Die Transistorzelle14 weist n- oder p-dotierte Gebiete auf, wie in2 gezeigt. Die Transistorzelle14 kann sich von der oberen Fläche zu der unteren Fläche des Halbleitersubstrats13 erstrecken (der Einfachheit halber sind die Transistorzellen14 nur auf der oberen Oberfläche des Halbleitersubstrats13 in1 gezeigt). Die Transistorzelle14 weist einen Source-Kontakt S und einen Source-Kontakt G auf der oberen Fläche des Halbleitersubstrats13 und einen Drain-Kontakt D auf der unteren Fläche des Halbleitersubstrats13 auf. Die in dem Leistungshalbleiterchip10 von1 enthaltene Leistungstransistorschaltung besteht aus mehreren Hunderten oder mehreren Tausenden der in2 gezeigten aktiven Transistorzellen14 . Die Source-Kontakte S und die Drain-Kontakte D der Transistorzellen14 sind elektrisch an die erste bzw. zweite Lastelektrode15 und17 gekoppelt. Die Gate-Kontakte G der Transistorzellen14 sind elektrisch an die Steuerelektrode16 gekoppelt. - Die
3A –3F , Kollektiv3 , zeigen schematisch eine Ausführungsform eines Verfahrens zum Herstellen eines Bauelements300 , das in3F gezeigt ist. -
3A zeigt schematisch einen Systemträger30 , der in einer Draufsicht (unten) und einer Querschnittsansicht (oben) entlang einer in der Draufsicht gezeigten Linie A-A‘ gezeigt ist. Der Systemträger30 enthält ein Die-Pad31 , eine erste Zuleitung32 , eine zweite Zuleitung33 , eine dritte Zuleitung34 und eine vierte Zuleitung35 . Das Die-Pad31 und die Zuleitungen32 –35 können durch Dämme (Tie Bars) verbunden sein, die aus Gründen der Übersichtlichkeit in3A nicht dargestellt sind. Bei einer Ausführungsform enthält der Systemträger30 weitere Die-Pads und Zuleitungen. - Der Systemträger
30 wird aus Metallen oder Metalllegierungen, insbesondere Kupfer, Kupferlegierungen, Eisen-Nickel, Aluminium, Aluminiumlegierungen oder anderen elektrisch leitenden Materialien hergestellt. Bei einer Ausführungsform wird der Systemträger30 mit einem elektrisch leitenden Material, beispielsweise Kupfer, Silber, Eisen-Nickel oder Nickelphosphor, plattiert. Die Gestalt des Systemträgers30 ist nicht auf irgendeine Größe oder geometrische Gestalt beschränkt. Beispielsweise kann der Systemträger30 eine Dicke im Bereich von 100 mm (Mikrometer) bis 1 mm sein oder sogar noch dicker sein. Der Systemträger30 kann durch Stanzen, Fräsen oder Prägen einer metallischen Platte hergestellt worden sein. -
3B zeigt schematisch einen ersten Leistungshalbleiterchip10 , der mit dem in1 gezeigten Leistungshalbleiterchip10 identisch ist und auf dem Die-Pad31 montiert ist. Bei einer Ausführungsform sind weitere Leistungshalbleiterchips auf weiteren Die-Pads des Systemträgers30 montiert, die in3B nicht gezeigt sind. - Der erste Leistungshalbleiterchip
10 ist so auf dem Die-Pad31 montiert, dass seine zweite Fläche12 dem Die-Pad31 zugewandt ist und seine erste Fläche11 vom Die-Pad31 abgewandt ist. Bei einer Ausführungsform ist die zweite Lastelektrode17 des ersten Leistungshalbleiterchips10 durch Diffusionslöten elektrisch und mechanisch an das Die-Pad31 gekoppelt. Dazu wird Lotmaterial auf der zweiten Lastelektrode17 oder der oberen Oberfläche des Die-Pad31 beispielsweise durch Sputtern oder durch (in3B nicht gezeigte) andere angemessene physikalische oder chemische Abscheidungsverfahren abgeschieden. Bei einer Ausführungsform wird das Lotmaterial auf der zweiten Lastelektrode17 abgeschieden, wenn sich der erste Leistungshalbleiterchip10 in einem Wafer-Bond befindet, was bedeutet, dass das Lotmaterial auf dem Halbleiter-Wafer abgeschieden wird, bevor der Halbleiter-Wafer vereinzelt wird, um individuelle Halbleiterchips herzustellen. Bei einer Ausführungsform besteht das Lotmaterial aus AuSn, AgSn, CuSn, Sn, AuIn, AgIn, AuSi oder CuIn. - Zum Herstellen der gelöteten Fügestelle (engl. soldered joint) wird der Systemträger
30 durch eine Heizplatte auf eine Temperatur über dem Schmelzpunkt des Lotmaterials erhitzt. Beispielsweise wird der Systemträger30 auf eine Temperatur im Bereich von 200°C bis 400°C und insbesondere im Bereich von 280 bis 320°C erhitzt. Bei einer Ausführungsform werden sowohl der Systemträger30 als auch der erste Leistungshalbleiterchip10 in einem Ofen platziert und auf eine entsprechende Temperatur erhitzt. Eine Pick-and-Place-Anlage wird verwendet, die den ersten Leistungshalbleiterchip10 aufgreifen und ihn auf dem Die-Pad31 platzieren kann. Während des Lötprozesses kann der erste Leistungshalbleiterchip10 für eine entsprechende Zeit im Bereich von 10 bis 200 ms, insbesondere etwa 50 ms, auf das Die-Pad31 gedrückt werden. - Während des Diffusionslötprozesses erzeugt das Lotmaterial eine metallische Fügestelle zwischen dem Die-Pad
31 und dem ersten Leistungshalbleiterchip10 , die aufgrund der Tatsache, dass das Lotmaterial mit hochschmelzenden Materialien des Die-Pad31 und des ersten Halbleiterchips10 eine temperaturbeständige und mechanisch hochstabile intermetallische Phase bildet, hohen Temperaturen standhalten kann. Die intermetallische Phase weist eine höhere Schmelztemperatur als das zum Erzeugen der intermetallischen Phase verwendete Lotmaterial auf. Im Prozess wird das niedrigschmelzende Lotmaterial vollständig umgewandelt, d. h. es geht vollständig in die intermetallische Phase über. - Bei einer Ausführungsform wird ein elektrisch leitender Kleber verwendet, um den ersten Leistungshalbleiterchip
10 an dem Die-Pad31 anzubringen. Der Kleber kann auf gefüllten oder ungefüllten Polyimiden, Epoxidharzen, Acrylatharzen, Silikonharzen oder Mischungen davon basieren und kann mit Gold-, Silber-, Nickel- oder Kupferpartikeln angereichert werden, um die elektrische Leitfähigkeit herzustellen. -
3C zeigt schematisch die Schichten40 ,41 und42 aus Lotmaterial, die auf zumindest Abschnitten (oder Teilen) des zweiten Abschnitts22 der ersten Metallschicht18 , der ersten Zuleitung32 bzw. der zweiten Metallschicht19 abgeschieden sind. Bei einer Ausführungsform werden die Schichten40 –42 aus Lotmaterial abgeschieden, nachdem die gelötete Fügestelle zwischen dem Die-Pad31 und dem ersten Leistungshalbleiterchip10 ausgebildet worden ist. Die Schichten40 –42 aus Lotmaterial werden unter Einsatz von Druck-, Dispensier- oder einer beliebigen anderen angebrachten Technik abgeschieden. Bei einer Ausführungsform werden die erste und zweite Metallschicht18 ,19 des ersten Leistungshalbleiterchips10 mindestens mit einer Schicht aus Nickel oder Kupfer oder irgendeinem anderen Metall oder irgendeiner anderen Metalllegierung beschichtet, das oder die das Herstellen einer gelöteten Fügestelle in einem Diffusionslötprozess gestattet. Außerdem kann eine Schicht aus Silber oder Gold auf der Nickel- oder Kupferschicht mit einer Dicke im Bereich von 10 bis 200 nm abgeschieden werden. Die Silber- oder Goldschicht verhindert die Oxidation der Nickel- oder Kupferschicht. -
3D zeigt schematisch einen Kontaktclip50 , der auf dem ersten Leistungshalbleiterchip10 und der ersten Zuleitung32 montiert ist. Der Kontaktclip50 weist einen ersten Kontaktbereich51 auf, der dem zweiten Abschnitt22 der ersten Metallschicht18 zugewandt ist, und einen zweiten Kontaktbereich52 , der der ersten Zuleitung32 zugewandt ist. Außerdem ist ein zweiter Leistungshalbleiterchip60 auf der zweiten Metallschicht19 des ersten Leistungshalbleiterchips10 montiert. Wegen der zweiten Metallschicht19 , die elektrisch von der ersten Metallschicht18 isoliert ist, kann der zweite Leistungshalbleiterchip60 auf den ersten Leistungshalbleiterchip10 gestapelt werden, und außerdem können aktive Transistorzellen14 in dem Halbleitersubstrat13 in dem Bereich20 unter dem zweiten Leistungshalbleiterchip60 angeordnet werden. - Der Kontaktclip
50 wird aus einem Metall oder einer Metalllegierung, insbesondere Kupfer, Kupferlegierungen, Eisen-Nickel oder anderen angebrachten elektrisch leitenden Materialien hergestellt. Die Gestalt des Kontaktclips50 ist nicht auf irgendeine Größe oder geometrische Gestalt beschränkt. Der Kontaktclip50 kann die Gestalt aufweisen, wie sie beispielhaft in3D gezeigt ist, jedoch ist auch eine beliebige andere Gestalt möglich. Der Kontaktclip50 wird durch Prägen, Stanzen, Pressen, Schneiden, Sägen, Fräsen oder irgendeine andere angebrachte Technik hergestellt. - Der zweite Leistungshalbleiterchip
60 weist eine erste Fläche61 und eine zweite Fläche62 gegenüber der ersten Fläche61 auf. Der zweite Leistungshalbleiterchip60 enthält ein Halbleitersubstrat63 und eine Leistungstransistorschaltung, die in das Halbleitersubstrat63 integriert ist und mehrere aktive Transistorzellen64 enthält. Außerdem enthält der zweite Leistungshalbleiterchip60 eine erste Lastelektrode65 und eine auf der ersten Fläche61 angeordnete Steuerelektrode66 und eine auf der zweiten Fläche62 angeordnete zweite Lastelektrode67 . Der zweite Leistungshalbleiterchip60 ist als ein Leistungstransistor konfiguriert, beispielsweise ein Leistungs-MOSFET, IGBT, JFET oder ein Leistungsbipolartransistor. Im Fall eines Leistungs-MOSFET oder eines JFET ist die erste Lastelektrode65 eine Sourcelektrode, die zweite Lastelektrode67 ist eine Drain-Elektrode und die Steuerelektrode66 ist eine Gate-Elektrode. Im Fall eines IGBT ist die erste Lastelektrode65 eine Emitterelektrode, die zweite Lastelektrode67 ist eine Kollektorelektrode und die Steuerelektrode66 ist eine Gate-Elektrode. Im Fall eines Leistungsbipolartransistors ist die erste Lastelektrode65 eine Emitterelektrode, die zweite Lastelektrode67 ist eine Kollektorelektrode und die Steuerelektrode66 ist eine Basiselektrode. Während des Betriebs können Spannungen über 5, 50, 100, 500 oder 1000 V zwischen der ersten und zweiten Lastelektrode65 ,67 angelegt werden. Die an die Steuerelektrode66 angelegte Schaltfrequenz kann im Bereich von 1 kHz bis 100 MHz liegen, kann aber auch außerhalb dieses Bereichs liegen. - Jede der ersten und zweiten Lastelektrode
65 ,67 und die Steuerelektrode66 können eine oder mehrere Metallschichten enthalten, die auf das Halbleitersubstrat63 aufgebracht sind. Die Metallschichten können mit einer beliebigen gewünschten geometrischen Gestalt und einer beliebigen gewünschten Materialzusammensetzung hergestellt werden. Ein beliebiges gewünschtes Metall oder eine beliebige gewünschte Metalllegierung, beispielsweise Aluminium, Titan, Gold, Silber, Kupfer, Palladium, Platin, Nickel, Chrom oder Nickel-Vanadium, können als das Material verwendet werden. Weiterhin ist der Basisbereich des zweiten Leistungshalbleiterchips60 kleiner als die exponierte (oder freiliegende) obere Oberfläche der zweiten Metallschicht19 , so dass der zweite Leistungshalbleiterchip60 vollständig innerhalb des Umrisses des Abschnitts der zweiten Metallschicht19 platziert wird, die gegenüber der Passivierungsschicht25 exponiert (oder freigelegt) wird. - Der Kontaktclip
50 und der zweite Leistungshalbleiterchip60 sind auf dem ersten Leistungshalbleiterchip10 und der ersten Zuleitung32 platziert, so dass der erste und der zweite Kontaktbereich51 ,52 über den Schichten40 bzw.41 aus Lotmaterial platziert sind, und die zweite Fläche62 des zweiten Leistungshalbleiterchips60 wird über der Schicht42 aus Lotmaterial platziert. Danach werden der Systemträger30 zusammen mit dem ersten und zweiten Leistungshalbleiterchip10 ,60 und Kontaktclip50 in einem Ofen platziert. In dem Ofen werden die Komponenten einer Temperatur ausgesetzt, die über der Schmelztemperatur des Lotmaterials der Schichten40 –42 liegt. Die Schmelztemperatur des Lotmaterials kann unter 260°C liegen und insbesondere etwa 230°C betragen. Die Temperatur im Ofen kann im Bereich von 280 bis 320°C liegen und insbesondere etwa 300°C betragen. - Im Ofen wird ein Diffusionslötprozess ausgeführt. Während des Diffusionslötprozesses erzeugt das Lotmaterial metallische Fügestellen zwischen dem ersten Kontaktbereich
51 und der ersten Metallschicht18 , zwischen dem zweiten Kontaktbereich52 und der ersten Zuleitung32 und zwischen dem zweiten Leistungshalbleiterchip60 und der zweiten Metallschicht19 . - Bei einer Ausführungsform wird ein elektrisch leitender Kleber verwendet, um den Kontaktclip
50 und den zweiten Leistungshalbleiterchip60 an dem ersten Halbleiterchip10 und der ersten Zuleitung32 anzubringen. Der Kleber kann auf gefüllten oder ungefüllten Polyimiden, Epoxidharzen, Acrylatharzen, Silikonharzen oder Mischungen davon basieren und kann mit Gold-, Silber-, Nickel- oder Kupferpartikeln angereichert werden, um die elektrische Leitfähigkeit herzustellen. -
3E zeigt schematisch Bonddrähte70 –73 , die eine elektrische Verbindung zwischen dem ersten und zweiten Leistungshalbleiterchip10 ,60 und dem Systemträger30 herstellen. Der Bonddraht70 koppelt die erste Lastelektrode65 des zweiten Leistungshalbleiterchips60 elektrisch an das Die-Pad31 , der Bonddraht71 koppelt die zweite Metallschicht19 (und somit die zweite Lastelektrode67 des zweiten Leistungshalbleiterchips60 ) elektrisch an die zweite Zuleitung33 , der Bonddraht72 koppelt die Steuerelektrode66 des zweiten Leistungshalbleiterchips60 elektrisch an die vierte Zuleitung35 , und der Bonddraht73 koppelt die Steuerelektrode16 des ersten Leistungshalbleiterchips10 elektrisch an die dritte Zuleitung34 . Beispielsweise wird Ball-Bonden oder Wedge-Bonden als die Zwischenverbindungstechnik verwendet, um die Bonddrähte70 –73 herzustellen. Die Bonddrähte70 –73 bestehen aus Gold, Aluminium, Kupfer oder irgendeinem anderen angebrachten elektrisch leitenden Material. -
3F zeigt schematisch ein Formmaterial74 , das die auf dem Systemträger30 angeordneten Komponenten kapselt. Das Formmaterial74 kann einen beliebigen Abschnitt (oder Teil) des Bauelements300 kapseln, lässt aber die unteren Oberflächen des Die-Pad31 und der Zuleitungen32 –35 unbedeckt. Die unbedeckten Oberflächen des Die-Pad31 und der Zuleitungen32 –35 können als externe Kontaktoberflächen zum elektrischen Koppeln des Bauelements300 an andere Komponenten, beispielsweise eine Leiterplatte wie etwa eine PCB (Printed Circuit Board – gedruckte Leiterplatte), dienen. Das Formmaterial74 kann aus einem beliebigen angebrachten thermoplastischen oder wärmehärtenden Material bestehen, insbesondere kann es aus einem Material bestehen, das üblicherweise in der gegenwärtigen Halbleiter-Packaging-Technologie verwendet wird. Verschiedene Techniken können eingesetzt werden, um die Komponenten des Bauelements300 mit dem Formmaterial74 zu bedekken, beispielsweise Formpressen, Spritzgießen, Pulversintern oder Liquid Molding. - Vor oder nach der Kapselung mit dem Formmaterial
74 werden die individuellen Bauelemente300 voneinander durch Trennung des Systemträgers30 beispielsweise durch Sägen oder Schneiden der Dämme (engl. dams) des Systemträgers30 getrennt. Andere Trennverfahren wie etwa Ätzen, Fräsen, Laserabtragung oder Prägen können ebenfalls verwendet werden. - Für einen Fachmann ist es offensichtlich, dass das Bauelement
300 nur ein Ausführungsbeispiel sein soll und viele Variationen möglich sind. Wenngleich das Bauelement300 in der in Figur 3F gezeigten Ausführungsform genau zwei Halbleiterchips enthält, kann das Bauelement300 weitere Halbleiterchips und/oder passive Elemente enthalten. Die Halbleiterchips und passiven Elemente können sich hinsichtlich Funktion, Größe, Herstellungstechnologie usw. unterscheiden. Beispielsweise kann ein Halbleiterchip, der den ersten und zweiten Leistungshalbleiterchip10 ,60 steuert, in dem Bauelement300 enthalten sein. -
4 zeigt schematisch eine Querschnittsansicht eines Bauelements400 , das mit dem in3F gezeigten Bauelement300 fast identisch ist. Der Unterschied besteht darin, dass das Bauelement400 einen Bonddraht75 anstatt des Kontaktclips50 enthält, um die erste Lastelektrode15 des ersten Leistungshalbleiterchips10 elektrisch an die erste Zuleitung32 zu koppeln. Es kann auch vorgesehen sein, dass weitere Bonddrähte zwischen die erste Lastelektrode15 und die erste Zuleitung32 geschaltet werden. -
5 zeigt schematisch eine Querschnittsansicht eines Systems500 , das das auf einer Leiterplatte80 , beispielsweise einer PCB, montierte Bauelement300 enthält. Die Leiterplatte80 enthält Kontaktpads81 , an denen die exponierten (oder freigelegten) Oberflächen des Die-Pad31 und die Zuleitungen32 –35 unter Verwendung von Lotabscheidungen82 angebracht sind. -
6 zeigt eine schematische Basisschaltung einer Halbbrückenschaltung600 mit zwei Schaltern, einem High-Side-Schalter HSS und einem Low-Side-Schalter LSS, die zwischen einer Versorgungsspannung VS und einem Massepotential V0 in Reihe geschaltet sind. Bei einer Ausführungsform wird die Halbbrückenschaltung600 unter Verwendung des Bauelements300 oder400 implementiert. Bei dieser Ausführungsform ist der erste Leistungshalbleiterchip10 der Low-Side-Schalter LSS, und der zweite Leistungshalbleiterchip60 ist der High-Side-Schalter HSS. Der High-Side-Schalter HSS ist durch seine zweite Lastelektrode67 (die in dem Fall, dass der zweite Leistungshalbleiterchip60 ein Leistungs-MOSFET ist, eine Drain-Elektrode ist) mit der Versorgungsspannung VS verbunden und wird mit Hilfe seiner Steuerelektrode66 (im Fall eines Leistungs-MOSFET einer Gate-Elektrode) geschaltet. Die erste Lastelektrode65 des High-Side-Schalters HSS (im Fall eines Leistungs-MOSFET eine Source-Elektrode) bildet zusammen mit der zweiten Lastelektrode17 des Low-Side-Schalters LSS (der für den Fall, dass der erste Leistungshalbleiterchip10 ein Leistungs-MOSFET ist, eine Drain-Elektrode ist) einen Reihenknoten, der über den Low-Side-Schalter LSS mit der ersten Lastelektrode15 davon (im Fall eines Leistungs-MOSFET eine Source-Elektrode) mit dem Massepotential V0 gekoppelt ist, falls die Steuerelektrode16 den Low-Side-Schalter LSS (im Fall eines Leistungs-MOSFET eine Gate-Elektrode) durchschaltet. Der an die erste Lastelektrode65 des High-Side-Schalters HSS und an die zweite Lastelektrode17 des Low-Side-Schalters LSS gekoppelte Knoten ist über einen Tiefpassfilter, der eine Induktivität L und einen Glättkondensator (engl. smoothing capacitor) C enthält, an einen Spannungsausgang DV gekoppelt. Die Induktivität L und der Glättkondensator C können innerhalb oder außerhalb der Bauelemente300 und400 implementiert werden. - Die Halbbrückenschaltung
600 kann beispielsweise in Elektronikschaltungen zum Umwandeln von Gleichspannungen implementiert werden, sogenannten DC-DC-Wandlern. DC-DC-Wandler können zum Umwandeln einer von einer Batterie oder von einer wiederaufladbaren Batterie (oder Akkumulator) gelieferten Eingangsgleichspannung in eine Ausgangsgleichspannung verwendet werden, die an die Anforderung von nachgeschalteten Elektronikschaltungen angepasst ist. DC-DC-Wandler können als Step-Down-Wandler ausgeführt werden, bei denen die Ausgangsspannung kleiner ist als die Eingangsspannung, oder als Stepup-Wandler, bei denen die Ausgangspannung größer ist als die Eingangsspannung. Frequenzen von mehreren MHz oder höher können an DC-DC-Wandler angelegt werden. Weiterhin können Ströme von bis zu 50 A oder noch höher durch die DC-DC-Wandler fließen. - Wenngleich ein bestimmtes Merkmal oder ein bestimmter Aspekt einer Ausführungsform der Erfindung bezüglich nur einer von mehreren Implementierungen offenbart worden sein mag, kann außerdem ein derartiges Merkmal oder ein derartiger Aspekt mit einem oder mehreren anderen Merkmalen oder Aspekten der anderen Implementierungen kombiniert werden, wie für eine gegebene oder bestimmte Anwendung erwünscht und vorteilhaft sein kann. Weiterhin sollen in dem Ausmaß, in dem die Ausdrücke „enthalten“, „haben“, „mit“ oder andere Varianten davon entweder in der ausführlichen Beschreibung oder den Ansprüchen verwendet werden, solche Ausdrücke auf eine Weise ähnlich dem Ausdruck „umfassen“ einschließend sein. Weiterhin versteht es sich, dass Ausführungsformen der Erfindung in diskreten Schaltungen, teilweise integrierten Schaltungen oder ganz integrierten Schaltungen oder Programmierungsmitteln implementiert sein können. Außerdem ist der Ausdruck „beispielhaft“ lediglich als ein Beispiel anstatt das Beste oder Optimale gemeint. Es ist auch zu verstehen, dass hierin dargestellte Merkmale und/oder Elemente mit bestimmten Abmessungen relativ zueinander zum Zweck der Vereinfachung und zum leichten Verständnis dargestellt worden sind und dass tatsächliche Abmessungen von den hierin dargestellten wesentlich abweichen können.
- Wenngleich hierin spezifische Ausführungsformen dargestellt und beschrieben worden sind, versteht der Durchschnittsfachmann, dass eine Vielzahl alternativer und/oder äquivalenter Implementierungen für die gezeigten und beschriebenen spezifischen Ausführungsformen substituiert werden können, ohne von dem Konzept der vorliegenden Erfindung abzuweichen. Die vorliegende Anmeldung soll alle Adaptationen oder Variationen der hierin erörterten spezifischen Ausführungsformen abdekken.
Claims (24)
- Halbleiterchip, umfassend: eine Leistungstransistorschaltung, die mehrere aktive Transistorzellen umfasst; eine erste Lastelektrode und eine Steuerelektrode, auf einer ersten Fläche des Halbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht umfasst; eine zweite Lastelektrode, auf einer zweiten Fläche des Halbleiterchips angeordnet; und eine zweite Metallschicht, über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht gegenüber der Leistungstransistorschaltung elektrisch isoliert ist und die zweite Metallschicht über einem Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst.
- Halbleiterchip nach Anspruch 1, wobei die erste Metallschicht einen ersten Abschnitt mit einer ersten Dicke und einen zweiten Abschnitt mit einer zweiten Dicke aufweist, wobei die erste Dicke kleiner ist als die zweite Dicke.
- Halbleiterchip nach Anspruch 2, wobei die zweite Metallschicht über dem ersten Abschnitt der ersten Metallschicht angeordnet ist.
- Halbleiterchip nach Anspruch 2 oder 3, wobei eine Differenz zwischen der ersten Dicke und der zweiten Dicke zwischen 3 mm (Mikrometer) und 8 mm (Mikrometer) beträgt.
- Halbleiterchip nach einem der Ansprüche 2 bis 4, wobei eine Oberfläche des zweiten Abschnitts der ersten Metallschicht koplanar mit einer Oberfläche der zweiten Metallschicht ist.
- Halbleiterchip nach einem der vorhergehenden Ansprüche, ferner umfassend eine zwischen der ersten Metallschicht und der zweiten Metallschicht angeordnete dielektrische Schicht.
- Halbleiterchip nach einem der vorhergehenden Ansprüche, wobei der Halbleiterchip ein Leistungs-MOSFET, ein IGBT, ein JFET oder ein Leistungsbipolartransistor ist.
- Vorrichtung, umfassend: einen ersten Leistungshalbleiterchip, umfassend: eine Leistungstransistorschaltung, die mehrere aktive Transistorzellen umfasst; eine erste Lastelektrode und eine Steuerelektrode, auf einer ersten Fläche des ersten Leistungshalbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht umfasst; eine zweite Lastelektrode, auf einer zweiten Fläche des ersten Leistungshalbleiterchips angeordnet; eine zweite Metallschicht, über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht über einem Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst; und eine zwischen der ersten Metallschicht und der zweiten Metallschicht angeordnete dielektrische Schicht, wobei die dielektrische Schicht die erste Metallschicht elektrisch gegenüber der zweiten Metallschicht isoliert; und einen zweiten Leistungshalbleiterchip, auf der zweiten Metallschicht montiert.
- Vorrichtung nach Anspruch 8, wobei der zweite Leistungshalbleiterchip eine erste Lastelektrode und eine Steuerelektrode auf einer ersten Fläche und eine zweite Lastelektrode auf einer zweiten Fläche umfasst.
- Vorrichtung nach Anspruch 9, wobei der zweite Leistungshalbleiterchip auf der zweiten Metallschicht montiert ist, wobei seine zweite Fläche der zweiten Metallschicht zugewandt ist.
- Vorrichtung nach einem der Ansprüche 8 bis 10, wobei die zweite Lastelektrode des ersten Leistungshalbleiterchips elektrisch an die erste Lastelektrode des zweiten Leistungshalbleiterchips gekoppelt ist.
- Vorrichtung nach einem der Ansprüche 8 bis 11, ferner umfassend ein Die-Pad, wobei der erste Leistungshalbleiterchip auf dem Die-Pad montiert ist, wobei seine zweite Fläche dem Die-Pad zugewandt ist.
- Vorrichtung nach Anspruch 12, wobei der zweite Leistungshalbleiterchip eine erste Lastelektrode und eine Steuerelektrode auf einer ersten Fläche und eine zweite Lastelektrode auf einer zweiten Fläche umfasst, wobei das Bauelement ferner einen Bonddraht umfasst, der die erste Lastelektrode des zweiten Leistungshalbleiterchips elektrisch an das Die-Pad koppelt.
- Vorrichtung nach einem der Ansprüche 8 bis 13, wobei die erste Metallschicht einen ersten Abschnitt mit einer ersten Dicke und einen zweiten Abschnitt mit einer zweiten Dicke aufweist, wobei die erste Dicke kleiner ist als die zweite Dicke.
- Vorrichtung nach Anspruch 14, wobei die zweite Metallschicht über dem ersten Abschnitt der ersten Metallschicht angeordnet ist.
- Vorrichtung nach Anspruch 14 oder 15, wobei eine Differenz zwischen der ersten Dicke und der zweiten Dicke zwischen 3 mm (Mikrometer) und 8 mm (Mikrometer) beträgt.
- Vorrichtung nach einem der Ansprüche 14 bis 16, wobei eine Oberfläche des zweiten Abschnitts der ersten Metallschicht koplanar mit einer Oberfläche der zweiten Metallschicht ist.
- Halbbrückenschaltung, umfassend: einen Low-Side-Schalter, umfassend: ein Halbleitersubstrat; eine Leistungstransistorschaltung, in das Halbleitersubstrat eingebettet und mehrere aktive Transistorzellen umfassend; eine erste Lastelektrode und eine Steuerelektrode, auf einer ersten Fläche des Halbleitersubstrats angeordnet, wobei die erste Lastelektrode eine erste Metallschicht umfasst; eine zweite Lastelektrode, auf einer zweiten Fläche des Halbleitersubstrats angeordnet; eine zweite Metallschicht, über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht über einem Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst; und eine zwischen der ersten Metallschicht und der zweiten Metallschicht angeordnete dielektrische Schicht, wobei die dielektrische Schicht die erste Metallschicht elektrisch gegenüber der zweiten Metallschicht isoliert; und einen High-Side-Schalter, auf der zweiten Metallschicht montiert.
- Halbbrückenschaltung nach Anspruch 18, wobei der Low-Side-Schalter und der High-Side-Schalter Leistungs-MOSFETs, IGBTs, JFETs oder Leistungsbipolartransistoren sind.
- Verfahren zum Herstellen einer Vorrichtung, wobei das Verfahren umfasst: Bereitstellen eines Leadframe, der ein Die-Pad und mehrere Leads umfasst; Montieren eines ersten Leistungshalbleiterchips auf dem Die-Pad, wobei der erste Leistungshalbleiterchip umfasst: eine Leistungstransistorschaltung, die mehrere aktive Transistorzellen umfasst; eine erste Lastelektrode und eine Steuerelektrode, auf einer ersten Fläche des ersten Leistungshalbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht umfasst; eine zweite Lastelektrode, auf einer zweiten Fläche des ersten Leistungshalbleiterchips angeordnet; und eine zweite Metallschicht, über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht gegenüber der Leistungstransistorschaltung elektrisch isoliert ist und die zweite Metallschicht über einem Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst; und Montieren eines zweiten Leistungshalbleiterchips auf der zweiten Metallschicht.
- Verfahren nach Anspruch 20, ferner umfassend: Abscheiden von Lotmaterial auf der zweiten Metallschicht nach dem Montieren des ersten Leistungshalbleiterchips auf dem Die-Pad und vor dem Montieren des zweiten Leistungshalbleiterchips auf der zweiten Metallschicht.
- Verfahren nach Anspruch 21, wobei ein Diffusionslötprozess zum Montieren des zweiten Leistungshalbleiterchips auf der zweiten Metallschicht verwendet wird.
- Verfahren nach einem der Ansprüche 20 bis 22, ferner umfassend: Bereitstellen eines Kontaktclips, der einen ersten Kontaktbereich und einen zweiten Kontaktbereich umfasst; Anbringen des ersten Kontaktbereichs an der ersten Metallschicht; und Anbringen des zweiten Kontaktbereichs an einer der mehreren Leads.
- Verfahren nach Anspruch 23, ferner umfassend: Abscheiden von Lotmaterial auf der ersten Metallschicht und den Zuleitungen nach dem Montieren des ersten Leistungshalbleiterchips auf dem Die-Pad und vor dem Anbringen des Kontaktclips an der ersten Metallschicht und den Leads.
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US13/191,891 US8643176B2 (en) | 2011-07-27 | 2011-07-27 | Power semiconductor chip having two metal layers on one face |
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DE102014117086B4 (de) * | 2013-11-22 | 2020-08-27 | Infineon Technologies Austria Ag | Elektronisches Bauteil mit elektronischem Chip zwischen Umverteilungsstruktur und Montagestruktur |
DE102020106929B4 (de) | 2019-03-15 | 2024-01-25 | Infineon Technologies Ag | Halbleitervorrichtung mit einem die-pad mit einer dammartigen konfiguration und verfahren zur herstellung einer halbleitervorrichtung |
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US9257375B2 (en) * | 2009-07-31 | 2016-02-09 | Alpha and Omega Semiconductor Inc. | Multi-die semiconductor package |
US9385070B2 (en) * | 2013-06-28 | 2016-07-05 | Delta Electronics, Inc. | Semiconductor component having a lateral semiconductor device and a vertical semiconductor device |
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JP6338937B2 (ja) * | 2014-06-13 | 2018-06-06 | ローム株式会社 | パワーモジュールおよびその製造方法 |
US9245837B1 (en) * | 2014-07-07 | 2016-01-26 | Infineon Technologies Ag | Radio frequency power device |
DE102015122259B4 (de) * | 2015-12-18 | 2020-12-24 | Infineon Technologies Austria Ag | Halbleitervorrichtungen mit einer porösen Isolationsschicht |
DE102016101801B4 (de) * | 2016-02-02 | 2021-01-14 | Infineon Technologies Ag | Lastanschluss eines leistungshalbleiterbauelements, leistungshalbleitermodul damit und herstellungsverfahren dafür |
JP7437582B2 (ja) * | 2018-04-11 | 2024-02-26 | ヒタチ・エナジー・リミテッド | パワー半導体チップ上の材料減少金属板 |
DE102018212438A1 (de) * | 2018-07-25 | 2020-01-30 | Infineon Technologies Ag | Halbleitergehäuse mit elektromagnetischer abschirmstruktur und verfahren zu dessen herstellung |
US20230178457A1 (en) * | 2021-12-08 | 2023-06-08 | Nxp B.V. | Semiconductor package having lead frame with semiconductor die and component module mounted on opposite surfaces of the lead frame and methods of manufacture thereof |
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JP3480771B2 (ja) * | 1995-12-20 | 2003-12-22 | 三菱電機株式会社 | 半導体装置 |
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JP4383257B2 (ja) * | 2004-05-31 | 2009-12-16 | 三洋電機株式会社 | 回路装置およびその製造方法 |
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- 2012-07-19 DE DE102012106566.7A patent/DE102012106566B4/de not_active Expired - Fee Related
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DE102014117086B4 (de) * | 2013-11-22 | 2020-08-27 | Infineon Technologies Austria Ag | Elektronisches Bauteil mit elektronischem Chip zwischen Umverteilungsstruktur und Montagestruktur |
DE102020106929B4 (de) | 2019-03-15 | 2024-01-25 | Infineon Technologies Ag | Halbleitervorrichtung mit einem die-pad mit einer dammartigen konfiguration und verfahren zur herstellung einer halbleitervorrichtung |
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CN102903694B (zh) | 2017-09-08 |
US8643176B2 (en) | 2014-02-04 |
DE102012106566B4 (de) | 2016-06-23 |
US20130027113A1 (en) | 2013-01-31 |
CN102903694A (zh) | 2013-01-30 |
DE102012106566A9 (de) | 2014-03-13 |
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