DE10084500T1 - Frequenzvervielfachende Delay Locked Loop - Google Patents
Frequenzvervielfachende Delay Locked LoopInfo
- Publication number
- DE10084500T1 DE10084500T1 DE2000184500 DE10084500T DE10084500T1 DE 10084500 T1 DE10084500 T1 DE 10084500T1 DE 2000184500 DE2000184500 DE 2000184500 DE 10084500 T DE10084500 T DE 10084500T DE 10084500 T1 DE10084500 T1 DE 10084500T1
- Authority
- DE
- Germany
- Prior art keywords
- locked loop
- delay locked
- frequency multiplying
- multiplying delay
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/00006—Changing the frequency
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
- H03K5/15046—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a tapped delay line
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Dram (AREA)
- Manipulation Of Pulses (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA2,270,516 | 1999-04-30 | ||
CA002270516A CA2270516C (en) | 1999-04-30 | 1999-04-30 | Frequency-doubling delay locked loop |
PCT/CA2000/000468 WO2000067381A1 (en) | 1999-04-30 | 2000-05-01 | Frequency-multiplying delay locked loop |
Publications (2)
Publication Number | Publication Date |
---|---|
DE10084500T1 true DE10084500T1 (de) | 2002-06-27 |
DE10084500B3 DE10084500B3 (de) | 2014-02-13 |
Family
ID=4163496
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10084500.2T Expired - Fee Related DE10084500B3 (de) | 1999-04-30 | 2000-05-01 | Frequenzvervielfachende Delay Locked Loop |
DE2000185617 Pending DE10085617A5 (de) | 1999-04-30 | 2000-05-01 | Frequenzvervielfachende Delay Locked Loop (DLL) |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE2000185617 Pending DE10085617A5 (de) | 1999-04-30 | 2000-05-01 | Frequenzvervielfachende Delay Locked Loop (DLL) |
Country Status (9)
Country | Link |
---|---|
US (7) | US6441659B1 (de) |
JP (3) | JP2002543732A (de) |
KR (1) | KR100811766B1 (de) |
CN (1) | CN1190012C (de) |
AU (1) | AU4280300A (de) |
CA (1) | CA2270516C (de) |
DE (2) | DE10084500B3 (de) |
GB (1) | GB2363684B (de) |
WO (1) | WO2000067381A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10249886A1 (de) * | 2002-10-25 | 2004-05-13 | Sp3D Chip Design Gmbh | Verfahren und Vorrichtung zum Erzeugen eines Taktsignals mit vorbestimmten Taktsingaleigenschaften |
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JPH10215153A (ja) * | 1997-01-30 | 1998-08-11 | Toshiba Corp | クロック逓倍回路及び半導体集積回路 |
KR100214559B1 (ko) * | 1997-02-20 | 1999-08-02 | 구본준 | 주파수 배가기 |
US6369624B1 (en) * | 1998-11-03 | 2002-04-09 | Altera Corporation | Programmable phase shift circuitry |
CA2270516C (en) | 1999-04-30 | 2009-11-17 | Mosaid Technologies Incorporated | Frequency-doubling delay locked loop |
US8085074B1 (en) * | 2010-10-11 | 2011-12-27 | Texas Instruments Incorporated | Fast-locking delay locked loop |
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1999
- 1999-04-30 CA CA002270516A patent/CA2270516C/en not_active Expired - Fee Related
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2000
- 2000-05-01 AU AU42803/00A patent/AU4280300A/en not_active Abandoned
- 2000-05-01 DE DE10084500.2T patent/DE10084500B3/de not_active Expired - Fee Related
- 2000-05-01 JP JP2000616126A patent/JP2002543732A/ja active Pending
- 2000-05-01 WO PCT/CA2000/000468 patent/WO2000067381A1/en active Application Filing
- 2000-05-01 CN CNB008069409A patent/CN1190012C/zh not_active Expired - Fee Related
- 2000-05-01 KR KR1020017013919A patent/KR100811766B1/ko not_active IP Right Cessation
- 2000-05-01 US US09/562,024 patent/US6441659B1/en not_active Expired - Lifetime
- 2000-05-01 GB GB0125097A patent/GB2363684B/en not_active Expired - Fee Related
- 2000-05-01 DE DE2000185617 patent/DE10085617A5/de active Pending
-
2002
- 2002-08-26 US US10/227,547 patent/US7116141B2/en not_active Expired - Lifetime
-
2006
- 2006-07-28 US US11/495,212 patent/US7456666B2/en not_active Expired - Fee Related
-
2008
- 2008-09-25 US US12/284,763 patent/US7746136B2/en not_active Expired - Fee Related
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2009
- 2009-12-18 JP JP2009287078A patent/JP4619446B2/ja not_active Expired - Fee Related
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2010
- 2010-05-20 US US12/784,157 patent/US8283959B2/en not_active Expired - Lifetime
- 2010-09-21 JP JP2010210865A patent/JP4677511B2/ja not_active Expired - Fee Related
-
2012
- 2012-09-07 US US13/607,015 patent/US8558593B2/en not_active Expired - Fee Related
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2013
- 2013-09-10 US US14/023,047 patent/US8754687B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10249886A1 (de) * | 2002-10-25 | 2004-05-13 | Sp3D Chip Design Gmbh | Verfahren und Vorrichtung zum Erzeugen eines Taktsignals mit vorbestimmten Taktsingaleigenschaften |
DE10249886B4 (de) * | 2002-10-25 | 2005-02-10 | Sp3D Chip Design Gmbh | Verfahren und Vorrichtung zum Erzeugen eines Taktsignals mit vorbestimmten Taktsingaleigenschaften |
Also Published As
Publication number | Publication date |
---|---|
KR20020018660A (ko) | 2002-03-08 |
GB2363684B (en) | 2003-07-16 |
US20060261866A1 (en) | 2006-11-23 |
US6441659B1 (en) | 2002-08-27 |
WO2000067381A1 (en) | 2000-11-09 |
US7746136B2 (en) | 2010-06-29 |
US20140009196A1 (en) | 2014-01-09 |
US7456666B2 (en) | 2008-11-25 |
US8283959B2 (en) | 2012-10-09 |
JP4619446B2 (ja) | 2011-01-26 |
JP2002543732A (ja) | 2002-12-17 |
CN1190012C (zh) | 2005-02-16 |
US8754687B2 (en) | 2014-06-17 |
US20030042947A1 (en) | 2003-03-06 |
DE10085617A5 (de) | 2014-04-03 |
JP2010074859A (ja) | 2010-04-02 |
KR100811766B1 (ko) | 2008-03-10 |
US8558593B2 (en) | 2013-10-15 |
GB0125097D0 (en) | 2001-12-12 |
US20090039931A1 (en) | 2009-02-12 |
DE10084500B3 (de) | 2014-02-13 |
US7116141B2 (en) | 2006-10-03 |
US20130015898A1 (en) | 2013-01-17 |
CA2270516C (en) | 2009-11-17 |
JP2011019281A (ja) | 2011-01-27 |
GB2363684A (en) | 2002-01-02 |
US20100225370A1 (en) | 2010-09-09 |
JP4677511B2 (ja) | 2011-04-27 |
CA2270516A1 (en) | 2000-10-30 |
CN1349683A (zh) | 2002-05-15 |
AU4280300A (en) | 2000-11-17 |
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