DD146230A5 - Verfahren und anordnung zur phaseneinstellung von signalen im fernmeldenetz - Google Patents

Verfahren und anordnung zur phaseneinstellung von signalen im fernmeldenetz Download PDF

Info

Publication number
DD146230A5
DD146230A5 DD79215609A DD21560979A DD146230A5 DD 146230 A5 DD146230 A5 DD 146230A5 DD 79215609 A DD79215609 A DD 79215609A DD 21560979 A DD21560979 A DD 21560979A DD 146230 A5 DD146230 A5 DD 146230A5
Authority
DD
German Democratic Republic
Prior art keywords
signal
reference signal
control signal
signals
comparison
Prior art date
Application number
DD79215609A
Other languages
German (de)
English (en)
Inventor
Karl A I Andersson
Sture G Roos
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of DD146230A5 publication Critical patent/DD146230A5/de

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Control Of Velocity Or Acceleration (AREA)
  • Synchronizing For Television (AREA)
  • Manipulation Of Pulses (AREA)
DD79215609A 1978-09-21 1979-09-18 Verfahren und anordnung zur phaseneinstellung von signalen im fernmeldenetz DD146230A5 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE7809934A SE413826B (sv) 1978-09-21 1978-09-21 Sett att i ett telekommunikationssystem reglera fasleget hos en styrd signal i forhallande till en referenssignal samt anordning for genomforande av settet

Publications (1)

Publication Number Publication Date
DD146230A5 true DD146230A5 (de) 1981-01-28

Family

ID=20335888

Family Applications (1)

Application Number Title Priority Date Filing Date
DD79215609A DD146230A5 (de) 1978-09-21 1979-09-18 Verfahren und anordnung zur phaseneinstellung von signalen im fernmeldenetz

Country Status (22)

Country Link
US (1) US4380083A (sv)
EP (1) EP0010077B1 (sv)
JP (1) JPS55500724A (sv)
AR (1) AR229083A1 (sv)
AU (1) AU525914B2 (sv)
CA (1) CA1142238A (sv)
CS (1) CS216684B2 (sv)
DD (1) DD146230A5 (sv)
DE (1) DE2963616D1 (sv)
DK (1) DK149292C (sv)
EG (1) EG14080A (sv)
ES (1) ES484315A1 (sv)
FI (1) FI70660C (sv)
HU (1) HU178531B (sv)
IE (1) IE48553B1 (sv)
IN (1) IN153004B (sv)
MX (1) MX149453A (sv)
NO (1) NO150260C (sv)
PL (1) PL128123B1 (sv)
SE (1) SE413826B (sv)
WO (1) WO1980000901A1 (sv)
YU (1) YU228379A (sv)

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SE503069C2 (sv) * 1994-07-06 1996-03-18 Ericsson Telefon Ab L M Förfarande och anordning för att fasvrida en signal
GB9505350D0 (en) * 1995-03-16 1995-05-03 British Tech Group Electronic identification system
US5712580A (en) * 1996-02-14 1998-01-27 International Business Machines Corporation Linear phase detector for half-speed quadrature clocking architecture
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KR100244466B1 (ko) * 1997-04-26 2000-02-01 김영환 클럭 위상 비교기
KR100215889B1 (ko) * 1997-05-06 1999-08-16 구본준 클럭 동기 회로
DE60044276D1 (de) * 1999-06-04 2010-06-10 Sumitomo Chemical Co Esterase Gene und Verwendungen davon
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US8160864B1 (en) 2000-10-26 2012-04-17 Cypress Semiconductor Corporation In-circuit emulator and pod synchronized boot
US6724220B1 (en) 2000-10-26 2004-04-20 Cyress Semiconductor Corporation Programmable microcontroller architecture (mixed analog/digital)
US8149048B1 (en) 2000-10-26 2012-04-03 Cypress Semiconductor Corporation Apparatus and method for programmable power management in a programmable analog circuit block
US7765095B1 (en) 2000-10-26 2010-07-27 Cypress Semiconductor Corporation Conditional branching in an in-circuit emulation system
US8103496B1 (en) 2000-10-26 2012-01-24 Cypress Semicondutor Corporation Breakpoint control in an in-circuit emulation system
US8176296B2 (en) 2000-10-26 2012-05-08 Cypress Semiconductor Corporation Programmable microcontroller architecture
KR20060094106A (ko) * 2001-04-20 2006-08-28 알로이즈 우벤 풍력 발전 플랜트의 운전 방법
DE10119624A1 (de) 2001-04-20 2002-11-21 Aloys Wobben Verfahren zum Betreiben einer Windenergieanlage
US7406674B1 (en) 2001-10-24 2008-07-29 Cypress Semiconductor Corporation Method and apparatus for generating microcontroller configuration information
US8078970B1 (en) 2001-11-09 2011-12-13 Cypress Semiconductor Corporation Graphical user interface with user-selectable list-box
US8042093B1 (en) 2001-11-15 2011-10-18 Cypress Semiconductor Corporation System providing automatic source code generation for personalization and parameterization of user modules
US6971004B1 (en) 2001-11-19 2005-11-29 Cypress Semiconductor Corp. System and method of dynamically reconfiguring a programmable integrated circuit
US7774190B1 (en) 2001-11-19 2010-08-10 Cypress Semiconductor Corporation Sleep and stall in an in-circuit emulation system
US7770113B1 (en) 2001-11-19 2010-08-03 Cypress Semiconductor Corporation System and method for dynamically generating a configuration datasheet
US8069405B1 (en) 2001-11-19 2011-11-29 Cypress Semiconductor Corporation User interface for efficiently browsing an electronic document using data-driven tabs
US7844437B1 (en) 2001-11-19 2010-11-30 Cypress Semiconductor Corporation System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit
US8103497B1 (en) 2002-03-28 2012-01-24 Cypress Semiconductor Corporation External interface for event architecture
US7761845B1 (en) 2002-09-09 2010-07-20 Cypress Semiconductor Corporation Method for parameterizing a user module
US7295049B1 (en) * 2004-03-25 2007-11-13 Cypress Semiconductor Corporation Method and circuit for rapid alignment of signals
US8069436B2 (en) 2004-08-13 2011-11-29 Cypress Semiconductor Corporation Providing hardware independence to automate code generation of processing device firmware
US7332976B1 (en) 2005-02-04 2008-02-19 Cypress Semiconductor Corporation Poly-phase frequency synthesis oscillator
US7400183B1 (en) 2005-05-05 2008-07-15 Cypress Semiconductor Corporation Voltage controlled oscillator delay cell and method
US8085067B1 (en) 2005-12-21 2011-12-27 Cypress Semiconductor Corporation Differential-to-single ended signal converter circuit and method
US8067948B2 (en) 2006-03-27 2011-11-29 Cypress Semiconductor Corporation Input/output multiplexer bus
WO2008012915A1 (fr) * 2006-07-28 2008-01-31 Fujitsu Limited Appareil de détermination de phase et appareil de synchronisation de phase
US9564902B2 (en) 2007-04-17 2017-02-07 Cypress Semiconductor Corporation Dynamically configurable and re-configurable data path
US8026739B2 (en) 2007-04-17 2011-09-27 Cypress Semiconductor Corporation System level interconnect with programmable switching
US8516025B2 (en) * 2007-04-17 2013-08-20 Cypress Semiconductor Corporation Clock driven dynamic datapath chaining
US8092083B2 (en) 2007-04-17 2012-01-10 Cypress Semiconductor Corporation Temperature sensor with digital bandgap
US8040266B2 (en) 2007-04-17 2011-10-18 Cypress Semiconductor Corporation Programmable sigma-delta analog-to-digital converter
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US8266575B1 (en) 2007-04-25 2012-09-11 Cypress Semiconductor Corporation Systems and methods for dynamically reconfiguring a programmable system on a chip
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Also Published As

Publication number Publication date
PL218426A1 (sv) 1980-08-11
YU228379A (en) 1982-10-31
DE2963616D1 (en) 1982-10-28
WO1980000901A1 (en) 1980-05-01
NO793023L (no) 1980-03-24
IE48553B1 (en) 1985-03-06
CA1142238A (en) 1983-03-01
JPS55500724A (sv) 1980-10-02
AU525914B2 (en) 1982-12-09
IN153004B (sv) 1984-05-19
FI70660C (fi) 1986-09-24
DK149292C (da) 1987-01-19
MX149453A (es) 1983-11-08
AR229083A1 (es) 1983-06-15
SE413826B (sv) 1980-06-23
NO150260C (no) 1984-09-12
DK149292B (da) 1986-04-21
PL128123B1 (en) 1983-12-31
US4380083A (en) 1983-04-12
FI70660B (fi) 1986-06-06
EP0010077A1 (en) 1980-04-16
EG14080A (en) 1983-03-31
DK220080A (da) 1980-05-20
AU5099379A (en) 1980-03-27
SE7809934L (sv) 1980-03-22
FI792703A (fi) 1980-03-22
EP0010077B1 (en) 1982-09-01
IE791778L (en) 1980-03-21
ES484315A1 (es) 1980-05-16
HU178531B (en) 1982-05-28
NO150260B (no) 1984-06-04
CS216684B2 (en) 1982-11-26

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