CN2685979Y - Paralled to serial conversion circuit for universal serial interface of bus interface circuit computer - Google Patents
Paralled to serial conversion circuit for universal serial interface of bus interface circuit computer Download PDFInfo
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- CN2685979Y CN2685979Y CNU2004200211663U CN200420021166U CN2685979Y CN 2685979 Y CN2685979 Y CN 2685979Y CN U2004200211663 U CNU2004200211663 U CN U2004200211663U CN 200420021166 U CN200420021166 U CN 200420021166U CN 2685979 Y CN2685979 Y CN 2685979Y
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The utility model discloses a parallel to serial conversion circuit for universal serial interface of bus interface circuit computer, comprising a high speed parallel to serial conversion body circuit satisfying the processing speed of 480mbps and a recovery enable circuit which can reduce power consumption. The circuit is simple with high efficiency, which can be realized with the standard CMOS integrated circuit technology of the TSMC 0. 25um without expensive integrated circuit technology of the 0. 18um CMOS. The utility model can reduce the cost effectively, applicable to high speed data processing, satisfying the processing requirement of USB2. 0 interface circuit data transmission. The utility model can universally used for the present USB interface circuit.
Description
Technical field
The utility model relates to the parallel-to-serial converter in computer general-purpose serial interface bus (USB2.0) interface circuit.
Background technology
1994,7 tame computing machines such as Intel, Compaq, Digital, IBM, Microsoft, NEC, Nortel and communication producer are in order to solve the problem of speed, extended capability and the ease for use of PC in the serial line interface communication, unite and set up USB (Universal Serial Bus) forum, and formally worked out the USB0.9 universal serial bus specification November nineteen ninety-five, be used to form unified PC Peripheral Interface standard.The USB2.0 standard of issue in 2000 provides low speed (1.5Mbps), three kinds of rate modes of (12Mbps) and high speed (480Mbps) adapt to various dissimilar peripheral hardwares at full speed.Particularly, use USB interface, you can use the mode of " daisy chain " to be connected on the PC various equipment, and maximum can be supported nearly 127 equipment, add plug and play and hot plug, compare, made things convenient for many in the use with ancient serial ports and parallel port.
At present, what the parallel-to-serial converter in computer general-purpose serial interface bus (USB2.0) interface circuit on the market used is common shift register, they need spend a large amount of d type flip flops, and need the 0.18umCMOS integrated circuit fabrication process just can reach the processing speed of (480Mbps) at a high speed, cost is higher.
Summary of the invention
The purpose of this utility model provides a kind of simple and reliable, low in energy consumption, the parallel-to-serial converter in the computer general-purpose serial interface bus interface circuit that can effectively reduce cost.
For reaching above-mentioned purpose, technical solution of the present utility model is: the parallel-to-serial converter in USB (universal serial bus) bus (USB2.0) interface circuit comprise reset enable circuit and and go here and there conversion bodies circuit two parts, said reset enable circuit comprises d type flip flop, XOR gate, or door, two and door and phase inverter, input end of XOR gate and or an input end of door connect the data input pin of d type flip flop jointly, another input end of XOR gate and or another input end of door connect the data output end of d type flip flop jointly, the output terminal of XOR gate links to each other with an input end of door with first, or the output terminal of door links to each other with an input end of door with second, first with another input end of door and second with another input end connect the clock end of d type flip flop jointly, second links to each other with the input end of phase inverter with the output terminal of door, said and string conversion bodies circuit comprises eight circular shift register unit, eight transmission gates and a d type flip flop, each circular shift register unit is managed by five nmos, four pmos pipes and a phase inverter are formed, two branch roads are arranged in each circular shift register unit, article one, props up route the one pmos pipe, the 2nd pmos pipe, the one nmos pipe and the 2nd nmos pipe are followed in series to form, second props up route the 3rd pmos pipe, the 4th pmos pipe, the 3rd nmos pipe and the 4th nmos pipe are followed in series to form, the source electrode of the one pmos pipe and the 3rd pmos pipe connects power supply, the source ground of the 2nd nmos pipe and the 4th nmos pipe, the grid of the one pmos pipe links to each other with the grid of the 2nd nmos pipe, and with the input end of cell inverters separately, the common contact of second output terminal of first output terminal of unit and previous element links to each other separately, the grid of the 2nd pmos pipe connects the output terminal of the phase inverter in the reset enable circuit, the grid of the one nmos pipe connects the output terminal of second in reset enable circuit and door, the grid of the 3rd pmos pipe links to each other with the grid of the 4th nmos pipe, and is connected on the tie point of the 2nd a pmos pipe and a nmos pipe.The grid of the 4th pmos pipe connects the output terminal of second in reset enable circuit and door, the grid of the 3rd nmos pipe connects the output terminal of the phase inverter in the reset enable circuit, the 4th pmos pipe is connected to second output terminal of unit separately with the tie point of the 3rd nmos pipe, the source electrode of the 5th nmos pipe of first module connects power supply, drain electrode connects first output terminal of first module, grid connects the output terminal of first in reset enable circuit and door, the source ground of the 5th nmos pipe of Unit the second～eight, drain electrode connects first output terminal of unit separately, grid connects the output terminal of first in reset enable circuit and door, eight transmission gates are formed in parallel by a pmos pipe and a nmos pipe respectively, the grid of nmos pipe is connected with first output terminal of Unit the first～eight respectively in each transmission gate, the grid of each pmos pipe is connected with the output terminal of the phase inverter of Unit the first～eight respectively, the input end of each transmission gate is connected with the parallel data input end respectively, the output terminal of each transmission gate all is connected to and goes here and there on the data input pin of the d type flip flop in the conversion bodies circuit, the data output end of this d type flip flop connects the serial data output terminal, the output terminal of second in clock termination reset enable circuit and door.
When the parallel-to-serial converter in the USB2.0 interface circuit of the present utility model uses, the string enable signal txoe_hs that also changes of outside is input on the data input pin of d type flip flop in the reset enable circuit, the clock period signal clk480 of outside 480MHz is input on the clock end of this d type flip flop, and after changeing the string enable signal and becoming high level, first will be output as the reset signal reset of high level with the output terminal of door, the pulse width of this signal is half 480MHz cycle, this signal as and go here and there the reset signal of conversion bodies circuit, second with the output terminal of door be the displacement upset clock CLK1 of 480MHz with output frequency, the output terminal of phase inverter is the displacement upset inversion clock CLK2 of 480MHz with output frequency, the data output end output serial data useful signal txoe of d type flip flop.Eight outside bit parallel data D1～D8 are input to and go here and there on the eight bit data input end of conversion bodies circuit, and after the reset signal of string conversion bodies circuit becomes high level, and eight circular shift register unit in the string conversion bodies circuit just automatically reset, first output terminal of first module is changed to high level, first output terminal of Unit the second～eight all is changed to low level, be in conducting state with regard to the transmission gate that has only first module like this, the not conducting of transmission gate of remaining element.Eight circular shift register unit can be opened the transmission gate of eight unit successively under displacement upset clock and the control of displacement upset inversion clock then, and can guarantee to have only a transmission gate to be in conducting state at every turn, and the corresponding data of conducting sent into and go here and there in the data input pin of d type flip flop of conversion bodies circuit.Like this in the clock period of each 480MHz and go here and there the conversion bodies circuit and can read in one digit number certificate in the eight bit parallel data that input rate is 60MHz successively, and the data output end of the d type flip flop in the string conversion bodies circuit will export serial data di, thereby realize at a high speed and change the function of going here and there.When reset enable circuit was in not transmit status in USB interface, the displacement upset clock of output and displacement upset inversion clock were in not rollover states, and promptly parallel-to-serial converter is in off position, thereby has reduced power consumption.
The beneficial effects of the utility model are, can realize with the standard CMOS integrated circuit technology of TSMC0.25um, the integrated circuit fabrication process that does not need expensive 0.18um CMOS, can effectively reduce cost, circuit is simple, high-speed low-power-consumption is suitable for high-speed data and handles, and can satisfy the requirement of USB2.0 interface circuit data transmission and processing.
Description of drawings
Fig. 1 is a formation block diagram of the present utility model.
Fig. 2 is reset enable circuit figure.
Fig. 3 is and string conversion bodies circuit diagram.
Embodiment
With reference to Fig. 1, the parallel-to-serial converter in the computer general-purpose serial interface bus interface circuit of the present utility model comprises reset enable circuit I and and goes here and there conversion bodies circuit I I two parts.
Reset enable circuit I sees shown in Figure 2, it comprises d type flip flop 1, XOR gate 2 or 4, two at door and door 3,5 and phase inverter 6, input end A of XOR gate 2 and or an input end B of door 4 meet the data input pin D of d type flip flop 1 jointly, this end be and changes and go here and there enable signal txoe_hs input end.Another input end B of XOR gate 2 and or door another input end A of 4 meet the data output end Q of d type flip flop 1 jointly, this end is the output terminal of serial data useful signal txoe.The output terminal of XOR gate 2 links to each other with an input end B of door 3 with first, or the output terminal of door 4 links to each other with an input end A of door 5 with second, first meets the clock end CLK of d type flip flop 1 with door another input end A of 3 and second jointly with another input end B of 5, and this end is a 480MHz clock signal clk480 input end.Second links to each other with the input end of phase inverter 6 with the output terminal of door 5.First with door 3 output terminal be the output terminal of reset signal reset, second is displacement upset output terminal of clock CLK1 with the output terminal of door 5, the output terminal of phase inverter 6 is displacement upset inversion clock output terminal CLK2.
And string conversion bodies circuit I I sees shown in Figure 3, it comprises eight circular shift register unit, eight transmission gate TR1～TR8 and a d type flip flop DF, each circular shift register unit is by five nmos pipe N1～N5, four pmos pipe P1～P4 and a phase inverter V1 form, two branch roads are arranged in each unit, article one, props up route the one pmos pipe P1, the 2nd pmos manages P2, the one nmos pipe N1 and the 2nd nmos pipe N2 are followed in series to form, second props up route the 3rd pmos pipe P3, the 4th pmos manages P4, the 3rd nmos pipe N3 and the 4th nmos pipe N4 are followed in series to form, the source electrode of the one pmos pipe P1 and the 3rd pmos pipe P3 meets power vd D, the source ground GND of the 2nd nmos pipe N2 and the 4th nmos pipe N4, the grid of the one pmos pipe P1 links to each other with the grid of the 2nd nmos pipe N2, and with the input end I1 of cell inverters V1 separately, the common contact of the second output terminal R of first output terminal T of unit and previous element links to each other separately, the grid of the 2nd pmos pipe P2 connects the output terminal of the phase inverter 6 among the reset enable circuit I, the grid of the one nmos pipe N1 connects the output terminal of second among reset enable circuit I and door 5, the grid of the 3rd pmos pipe P3 links to each other with the grid of the 4th nmos pipe N4, and be connected on the tie point M1 of the 2nd pmos pipe P2 and nmos pipe N1, the grid of the 4th pmos pipe P4 connects the output terminal of second among reset enable circuit I and door 5, the grid of the 3rd nmos pipe N3 connects the output terminal of the phase inverter 6 among the reset enable circuit I, the tie point M2 of the 4th pmos pipe P4 and the 3rd nmos pipe N3 is connected to the second output terminal R of unit separately, the source electrode of the 5th nmos pipe N5 of first module meets power vd D, drain electrode meets the first output terminal T of first module, grid connects the output terminal of first among reset enable circuit I and door 3, the source ground GND of the 5th nmos pipe N5 of Unit the second～eight, drain electrode meets the first output terminal T of unit separately, grid connects the output terminal of first among reset enable circuit I and door 3, eight transmission gates are formed in parallel by a pmos pipe and a nmos pipe respectively, the grid of nmos pipe is connected with the first output terminal T of Unit the first～eight respectively in each transmission gate, the grid of each pmos pipe is connected with the output terminal of the phase inverter V1 of Unit the first～eight respectively, the input end of each transmission gate is connected with parallel data input end D1～D8 respectively, the output terminal of each transmission gate all is connected to and goes here and there on the data input pin D of the d type flip flop DF among the conversion bodies circuit I I, the data output end Q of this d type flip flop DF meets serial data output terminal di, and clock end CLK connects the output terminal of second among reset enable circuit I and door 5.
Above-mentioned reset enable circuit I and and go here and there conversion bodies circuit I I and can be integrated on the chip piece.
Claims (2)
1. the parallel-to-serial converter in the computer general-purpose serial interface bus interface circuit, it is characterized in that comprising reset enable circuit (I) and and go here and there conversion bodies circuit (II) two parts, said reset enable circuit (I) comprises d type flip flop (1), XOR gate (2), or door (4), two and door (3), (5) and phase inverter (6), an input end (A) of XOR gate (2) and or the input end (B) of door (4) connect the data input pin (D) of d type flip flop (1) jointly, another input end (B) of XOR gate (2) and or another input end (A) of door (4) connect the data output end (Q) of d type flip flop (1) jointly, the output terminal of XOR gate (2) links to each other with an input end (B) of door (3) with first, or the output terminal of door (4) links to each other with an input end (A) of door (5) with second, first with another input end (A) of door (3) and second and another input end (B) of (5) connect the clock end (CLK) of d type flip flop (1) jointly, second with the door (5) output terminal link to each other with the input end of phase inverter (6), said and string conversion bodies circuit (II) comprises eight circular shift register unit, eight transmission gates (TR1～TR8) and a d type flip flop (DF), (N1～N5) is managed by five nmos in each circular shift register unit, four pmos pipe (form by a P1～P4) and a phase inverter (V1), two branch roads are arranged in each circular shift register unit, article one, props up route the one pmos pipe (P1), the 2nd pmos manages (P2), the one nmos pipe (N1) and the 2nd nmos pipe (N2) are followed in series to form, second props up route the 3rd pmos pipe (P3), the 4th pmos manages (P4), the 3rd nmos pipe (N3) and the 4th nmos pipe (N4) are followed in series to form, the source electrode of the one pmos pipe (P1) and the 3rd pmos pipe (P3) connects power supply (VDD), the source ground (GND) of the 2nd nmos pipe (N2) and the 4th nmos pipe (N4), the grid of the one pmos pipe (P1) links to each other with the grid that the 2nd nmos manages (N2), and with the input end (I1) of cell inverters (V1) separately, the common contact of second output terminal (R) of first output terminal (T) of unit and previous element links to each other separately, the grid of the 2nd pmos pipe (P2) connects the output terminal of the phase inverter (6) in the reset enable circuit (I), the grid of the one nmos pipe (N1) connects the output terminal of second in reset enable circuit (I) and door (5), the grid of the 3rd pmos pipe (P3) links to each other with the grid that the 4th nmos manages (N4), and be connected on the tie point (M1) of the 2nd pmos pipe (P2) and nmos pipe (N1), the grid of the 4th pmos pipe (P4) connects the output terminal of second in reset enable circuit (I) and door (5), the grid of the 3rd nmos pipe (N3) connects the output terminal of the phase inverter (6) in the reset enable circuit (I), the 4th pmos pipe (P4) is connected to second output terminal (R) of unit separately with the tie point (M2) of the 3rd nmos pipe (N3), the source electrode of the 5th nmos pipe (N5) of first module connects power supply (VDD), drain electrode connects first output terminal (T) of first module, grid connects the output terminal of first in reset enable circuit (I) and door (3), the source ground (GND) of the 5th nmos pipe (N5) of Unit the second～eight, drain electrode connects first output terminal (T) of unit separately, grid connects the output terminal of first in reset enable circuit (I) and door (3), eight transmission gate (TR1～TR8) be formed in parallel by a pmos pipe and a nmos pipe respectively, the grid of nmos pipe is connected with first output terminal (T) of Unit the first～eight respectively in each transmission gate, the grid of each pmos pipe is connected with the output terminal of the phase inverter (V1) of Unit the first～eight respectively, the input end of each transmission gate respectively with parallel data input end (D1～D8) be connected, the output terminal of each transmission gate all is connected to and goes here and there on the data input pin (D) of the d type flip flop (DF) in the conversion bodies circuit (II), the data output end (Q) of this d type flip flop (DF) connects serial data output terminal (di), and clock end (CLK) connects the output terminal of second in reset enable circuit (I) and door (5).
2. the parallel-to-serial converter in the computer general-purpose serial interface bus interface circuit according to claim 1 is characterized in that said reset enable circuit (I) and and goes here and there conversion bodies circuit (II) and be integrated on the chip piece.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2004200211663U CN2685979Y (en) | 2004-03-19 | 2004-03-19 | Paralled to serial conversion circuit for universal serial interface of bus interface circuit computer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2004200211663U CN2685979Y (en) | 2004-03-19 | 2004-03-19 | Paralled to serial conversion circuit for universal serial interface of bus interface circuit computer |
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| CN2685979Y true CN2685979Y (en) | 2005-03-16 |
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| CNU2004200211663U Expired - Fee Related CN2685979Y (en) | 2004-03-19 | 2004-03-19 | Paralled to serial conversion circuit for universal serial interface of bus interface circuit computer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1300716C (en) * | 2004-03-19 | 2007-02-14 | 浙江大学 | Parallel-serial switching circuit in bus interface circuit of computer general serial interface |
| WO2007140725A1 (en) * | 2006-05-31 | 2007-12-13 | Olinkstar Corporation, Ltd. | A navigation satellite signal processing system |
| CN113282531A (en) * | 2021-05-28 | 2021-08-20 | 福州大学 | Two-port serial data receiving and transmitting circuit and method based on pulse triggering |
-
2004
- 2004-03-19 CN CNU2004200211663U patent/CN2685979Y/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1300716C (en) * | 2004-03-19 | 2007-02-14 | 浙江大学 | Parallel-serial switching circuit in bus interface circuit of computer general serial interface |
| WO2007140725A1 (en) * | 2006-05-31 | 2007-12-13 | Olinkstar Corporation, Ltd. | A navigation satellite signal processing system |
| CN113282531A (en) * | 2021-05-28 | 2021-08-20 | 福州大学 | Two-port serial data receiving and transmitting circuit and method based on pulse triggering |
| CN113282531B (en) * | 2021-05-28 | 2023-08-11 | 福州大学 | Pulse trigger-based two-port serial data receiving and transmitting circuit and method |
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| CF01 | Termination of patent right due to non-payment of annual fee |