CN201219256Y

CN201219256Y - Input/output bidirectional port

Info

Publication number: CN201219256Y
Application number: CNU2008201183921U
Authority: CN
Inventors: 江猛; 贾力
Original assignee: SUZHOU HUAXIN MICRO-ELECTRONICS Co Ltd
Current assignee: Suzhou Huaxin Microelectronics Co., Ltd.
Priority date: 2008-06-05
Filing date: 2008-06-05
Publication date: 2009-04-08
Anticipated expiration: 2018-06-05

Abstract

An input/output two-way port, selects a direction of an I/O port setting 0 or 1 on the port, comprising a latch, a first reverser, a first control transistor, a second control transistor, a second reverser, a tristate reverser and a two-input NAND gate. When a data bus writes in 1, and port-reading signals are effective, through the second reverser and the tristate reverser arranged between the I/OPAD port and the data bus, the signal substantially having the same input signal with I/OPAD port is input to the data bus, realizing data input; when the data-writing signal is effectively, through the latch, the first reverser, the first control transistor and the second control transistor arranged between the data bus and the I/OPAD port, the signal substantially having the same signal with the data bus is output to the I/OPAD port, realizing data output. The input/output two-way port circuit has simple structure, convenient control, small circuit area, low cost, overcoming deficiency in the prior art.

Description

The I/O bidirectional port

Technical field

The utility model is specifically related to a kind of I/O bidirectional port in the integrated circuit fields.

Background technology

In various integrated circuits, especially in MCU (Micro Control Unit, i.e. microcontroller) circuit, I/O (Input/Output, i.e. I/O) mouthful is the indispensable important channel that circuit externally carries out information interchange.It is different from one way ports, as the input port, and perhaps delivery outlet, the function of these one way ports is single, it can only receive data or dateout; And the I/O mouth is the bidirectional port that possesses two functions of input and output, and it can carry out the reception and the transmission of data.

Among the MCU of traditional RISC (Reduced Instruction Set Computing, i.e. reduced instruction set computer) type, the I/O mouth is very complicated circuit, and it occupies 1/4 of entire circuit domain sometimes, sometimes even more.Because these I/O mouths all will be provided with the port direction register, by the value that changes the port direction register direction of I/O mouth is set, have in addition the direction that special instruction comes managing I/O mouth is set.These have all caused the complexity of I/O mouth circuit and huge.

Among the MCU of number of C ISC (Complex Instruction Set Computer, i.e. sophisticated vocabulary) type, though the port direction register is not set, there is the circuit complicated problems too in they.

Therefore, in some civilian consumer circuit, all seem unrealistic with these traditional I/O mouths, they not only control complexity, and area is big, the cost height.

The utility model content

The purpose of this utility model is to propose the I/O bidirectional port that a kind of circuit structure is simple, control is convenient, circuit area is little, cost is low, it need not to be provided with the port direction register, only, overcome deficiency of the prior art by port being put 0 or put 1 direction of selecting the I/O mouth.

For achieving the above object, the utility model has adopted following technical scheme:

A kind of I/O bidirectional port can be realized the reception and the transmission of data, comprising:

Latch, its data input pin links to each other with data/address bus, and clock signal terminal links to each other with write data signal;

First reverser, its input links to each other with the output of latch;

First oxide-semiconductor control transistors is arranged between the output and first constant potential of first reverser;

Second oxide-semiconductor control transistors is arranged between the output and second constant potential of first reverser;

The output of first oxide-semiconductor control transistors is connected with the output of second oxide-semiconductor control transistors, and its node place links to each other with I/O PAD mouth;

Second reverser, the output of its input and first oxide-semiconductor control transistors links to each other with node between the output of second oxide-semiconductor control transistors;

Tri-state inverter, its input links to each other with the output of second reverser, and Enable Pin links to each other with the read port signal, and output links to each other with the input of latch;

Two input nand gates, node between the output of one input end and latch and the input of first reverser links to each other, node between the output of another input and second reverser and the input of tri-state inverter links to each other, and its output is an input port level variable signal.

When data/address bus writes 1, and when the read port signal is effective, by being arranged on second reverser and the tri-state inverter between I/O PAD mouth and the data/address bus, identical with I/O PAD mouth input signal in fact signal is input to data/address bus, realize the input of data; When write data signal is effective, by being arranged on latch, first reverser, first oxide-semiconductor control transistors and second oxide-semiconductor control transistors between data/address bus and the I/O PAD mouth, identical with data bus signal in fact signal is outputed to I/O PAD mouth, realize the output of data.

Above-mentioned I/O bidirectional port, wherein first oxide-semiconductor control transistors is big breadth length ratio NMOS pipe, and second oxide-semiconductor control transistors is less breadth length ratio PMOS pipe, and each transistorized control end, output and input are respectively grid, drain electrode and source electrode.Above-mentioned first constant potential and second constant potential are respectively earth potential and power supply potential.Described input port level variable signal can be regarded input as and change interruption or waken system usefulness.

The beneficial effects of the utility model are that circuit structure is simple, control is convenient, circuit area is little, cost is low, need not to be provided with the port direction register, only by port being put 0 or put 1 direction of selecting the I/O mouth.

Description of drawings

Fig. 1 is the circuit diagram of the utility model I/O bidirectional port;

Fig. 2 is a preferred embodiment of the present utility model.

Embodiment

Below in conjunction with accompanying drawing the utility model is further described.

As shown in Figure 1, be the circuit diagram of the utility model I/O bidirectional port, comprise: data/address bus data, read port signal rd_port, write data signal wr_port, input port level variable signal INT, earth potential, power supply potential, I/O PAD mouth, latch 1, first reverser 2, first oxide-semiconductor control transistors 3, second oxide-semiconductor control transistors 4, second reverser 5, tri-state inverter 6 and two input nand gates 7.Wherein the data input pin D of latch 1 links to each other with data/address bus data, and clock signal terminal clk links to each other with write data signal wr_port, and output Q links to each other with the input of first reverser 2; The control end of first oxide-semiconductor control transistors 3 links to each other with the control end of second oxide-semiconductor control transistors 4, and link to each other with the output of first reverser 2, the output of first oxide-semiconductor control transistors 3 links to each other with the output of second oxide-semiconductor control transistors 4, and link to each other with I/O PAD mouth, the input of first oxide-semiconductor control transistors 3 and first constant potential, be that earth potential links to each other, the input of second oxide-semiconductor control transistors 4 and second constant potential, promptly power supply potential links to each other; The output of the input of second reverser 5 and the I/O PAD mouth and first oxide-semiconductor control transistors 3 links to each other with node between the output of second oxide-semiconductor control transistors 4, the output of second reverser 5 links to each other with the input of tri-state inverter 6, the Enable Pin of tri-state inverter 6 links to each other with read port signal rd_port, and the node between the data input pin D of output and data/address bus data and latch 1 links to each other; Two input nand gates 7, node between the output Q of one input end and latch 1 and the input of first reverser 2 links to each other, node between the output of another input and second reverser 5 and the input of tri-state inverter 6 links to each other, and its output is input port level variable signal INT.

Data writes 1 when data/address bus, and when read port signal rd_port is effective, by being arranged on second reverser 5 and tri-state inverter 6 between I/O PAD mouth and the data/address bus data, identical with I/O PAD mouth input signal in fact signal is input to data/address bus data, realizes the input of data.

When write data signal wr_port is effective, by being arranged on latch 1, first reverser 2, first oxide-semiconductor control transistors 3 and second oxide-semiconductor control transistors 4 between data/address bus data and the I/O PAD mouth, identical with data/address bus data signal in fact signal is outputed to I/O PAD mouth, realize the output of data.

When writing 0, (write during wr_port=1 by data/address bus data, also can write by wr_port=0, this will see the structure of latch 1), then first reverser 2 is output as 1,3 conductings of first oxide-semiconductor control transistors, second oxide-semiconductor control transistors 4 is closed, I/O PAD mouth is output as 0, because first oxide-semiconductor control transistors the last 3, external signal 1 (high level) is difficult to overturn it, when read port signal rd_port is effective, the data of reading on the data bus still are 0, and can regard it as delivery outlet this moment, because the data of reading are always 0, do not change, can not reflect the external signal that is added on the I/O PAD mouth.Owing to the output Q=0 of latch 1 this moment, by two input nand gates 7, input port level variable signal INT is always 1, and it is invalid that INT thinks.

When writing 1 by data/address bus data, first reverser 2 is output as 0, the first oxide-semiconductor control transistors 3 and cuts out, 4 conductings of second oxide-semiconductor control transistors, and I/O PAD mouth is output as 1.Because second oxide-semiconductor control transistors 4 relatively a little less than, if the signal that join I/O PAD mouth on from the outside this moment is strong by 0, then present 0 level on the I/O PAD mouth this moment, when read port signal rd_port was effective, the data of reading on the data bus still were 0, and can regard it as input port this moment, because during read data, the data of reading can reflect that the signal on exterior I/O PAD mouth changes, and being 0, what read in is exactly 0, are that 1 what read is exactly 1.At this moment, if the signal that is added on the I/OPAD mouth is 1, INT=1 then, if the signal that is added on the I/O PAD mouth is 0, INT=0 then.Therefore this signal can be regarded input variation interruption or waken system usefulness as.

Find out that thus the utility model need not to be provided with the port direction register, only, overcome deficiency of the prior art by port being put 0 or put 1 direction of selecting the I/O mouth.

Realize that optimal way of the present utility model is to be applied in the MCU circuit.With among four of risc architecture and eight the low and middle-grade MCU, be that the product of HS0227, HS0228 etc. is all used this I/O mouth as product type.As shown in Figure 2, be preferred embodiment of the present utility model.Wherein P10-P17 is the I/O mouth, after MCU carries out one section initialize routine, enters the power saving sleep state.If P10 ~ P13 is set in initialize routine is 1 entirely, and P14 ~ P17 is 0 entirely, and then in sleep state, as long as press in 16 buttons any one, system will be waken up.Because 0 level of P14 ~ P17 can be passed on P10 ~ P13, make P10 ~ P13 port present 0 level, thereby INT can change among Fig. 1, causes system to be waken up.Can carry out corresponding operation behind the system wake-up,, transmit etc. as keyboard scan.

Because each port can be provided with arbitrarily, so keyboard also can constitute arbitrarily.Pin can constitute keyboard in twos arbitrarily, has eliminated the limitation that specific pin constitutes keyboard like this.

Above-mentioned example only is a particular instance of the present utility model, must not be considered as restriction of the present utility model.

Claims

1. an I/O bidirectional port is characterized in that, comprising:

First reverser, its input links to each other with the output of latch;

Second reverser, its input links to each other with the output of first oxide-semiconductor control transistors, the output of second oxide-semiconductor control transistors and the node between the I/O PAD mouth;

2. I/O bidirectional port according to claim 1, it is characterized in that, when data/address bus writes 1, and when the read port signal is effective, by being arranged on second reverser and the tri-state inverter between I/O PAD mouth and the data/address bus, identical with I/O PAD mouth input signal in fact signal is input to data/address bus, realizes the input of data.

3. I/O bidirectional port according to claim 1, it is characterized in that, when write data signal is effective, by being arranged on latch, first reverser, first oxide-semiconductor control transistors and second oxide-semiconductor control transistors between data/address bus and the I/O PAD mouth, identical with data bus signal in fact signal is outputed to I/O PAD mouth, realize the output of data.

4. according to claim 1 or 3 described I/O bidirectional ports, it is characterized in that, described first oxide-semiconductor control transistors is big breadth length ratio NMOS pipe, second oxide-semiconductor control transistors is less breadth length ratio PMOS pipe, and each transistorized control end, output and input are respectively grid, drain electrode and source electrode.

5. I/O bidirectional port according to claim 1 is characterized in that, described first constant potential and second constant potential are respectively earth potential and power supply potential.

6. I/O bidirectional port according to claim 1 is characterized in that, described input port level variable signal can be regarded input as and change interruption or waken system usefulness.