CN201584404U

CN201584404U - Non-polar 485 chip

Info

Publication number: CN201584404U
Application number: CN2009202603205U
Authority: CN
Inventors: 刘爱民
Original assignee: Individual
Current assignee: Individual
Priority date: 2009-11-12
Filing date: 2009-11-12
Publication date: 2010-09-15
Anticipated expiration: 2019-11-12
Also published as: WO2011057538A1

Abstract

The utility model relates to a non-polar 485 chip, belonging to the field of manufacturing of electronic devices. The data I/O pin or the communication pin of the 485 chip is connected with a polarity reversing switch in series. When voltage Vab or Vba between a 485 communication line A and a 485 communication line B is more than zero and the duration exceeds certain time, the polarity reversing switch is controlled to act to enable the polarity of the lines is consistent with the internal polarity of the 485 chip. The utility model has the advantages that the problem of wiring error in the application of the 485 chip is eliminated, great convenience is provided for the use of the 485 chip and the non-polar 485 chip is suitable for all 485 communication places.

Description

Nonpolarity 485 chips

Affiliated technical field

The utility model belongs to field of electronic devices, relates to the making of serial communication interface 485 chips.

Background technology

485 chip application are very extensive, its communication pin divides A, B two kinds of polarity, its wiring rules: two communicate by letter pin A and B of 485 chips, couple together by two communication line A lines and B line, the connection that the A line of the A pin of all 485 chips, B pin and communication line, B line must be consistent: the A pin connects the A line, the B pin connects the B line, and to keep voltage Vab＞200mv between A line and B line, otherwise, whole or part line traffic paralysis.

The content of utility model

The purpose of this utility model: a kind of 485 chips that do not have polarity are provided.

Technical scheme provided by the utility model is: data I/O pin or polarity reversing switch of communication pin serial connection of giving 485 chips.Voltage Vab＞0 when between 485 communication line A lines, B line, and duration when surpassing certain hour are when data I/when the O pin has polarity reversing switch, make data be directly connected to 485 chips; When the communication pin has polarity reversing switch, make the A of 485 chips, A, the B line that the B pin directly connects communication line.Voltage Vba＞0 when between 485 communication line A lines, B line, and duration when surpassing certain hour are when data I/when the O pin has polarity reversing switch, make data back polarity be connected to 485 chips; When the communication pin has polarity reversing switch, make the A of 485 chips, B, the A line that the B pin connects communication line.

The beneficial effects of the utility model: current 485 chip wiring need be distinguished A line and B line, and assembling is produced and brought inconvenience to practical large-scale, have also increased many artificial site operation accidents.The present invention will eliminate 485 chip wiring error problems, and it is simpler, reliable that 485 communication equipments are installed, and use of large-scale production is more convenient.

Below in conjunction with accompanying drawing the utility model is described in further detail.

Description of drawings

Fig. 1 is the principle schematic of nonpolarity 485 first embodiment of chip of providing of the utility model.

Fig. 2 is the principle schematic of second embodiment of nonpolarity 485 chips of providing of the utility model.

Among Fig. 1: A1, differential output voltage comparator; A2, difference dateout driver; K1, K2, data polarity selector switch, 0.8S, 0.8 second delay circuit.

Among Fig. 2: A1, voltage comparator; A2, difference dateout driver; K1, polarity reversing switch, 0.8S, 0.8 second delay circuit.

Embodiment

Fig. 1 is the principle schematic of the embodiment of nonpolarity 485 chips that provides of the utility model.As shown in the figure, present embodiment includes differential output voltage comparator A1, difference dateout driver A2,0.8 second delay circuit 0.8S and data polarity selector switch K1, K2.Wherein, described differential output voltage comparator A1 is the input voltage of L1, L2 pin relatively, and its difference output connects data polar selecting switch K1, and K1 outputs to pin RO, and the polarity of K1 is selected controlled by the output of 0.8 second delay circuit 0.8S; Differential output voltage comparator A1 is controlled by pin RE simultaneously, during RE=0, and the A1 operate as normal, during RE=1, the output of A1 is frozen.Its input data of described difference dateout driver A2 are connected to pin DI by data polarity selector switch K2, and the polarity of K2 is selected controlled by the output of 0.8 second delay circuit 0.8S; The difference output of A2 links to each other with the input homophase of A1 and outputs to L1, L2, and difference dateout driver A2 is controlled by pin DE simultaneously, during DE=1, and the A2 operate as normal, during DE=0, A2 exports high-impedance state.0.8 a second delay circuit 0.8S is subjected to A1 output control, when A1 output changed, 0.8S picked up counting, and less than 0.8 second, variation took place in A1 output, the 0.8S reclocking, and A1 output in 0.8 second does not change, and 0.8S will export control signal; If A1=1 continued more than 0.8 second, 0.8S output 1 makes K1, K2 be connected to the positive ends of A1, A2; If A1=0 continued more than 0.8 second, 0.8S output 0 makes K1, K2 be connected to the negative polarity end of A1, A2.

Among another embodiment shown in Figure 2, include voltage comparator A1, difference dateout driver A2,0.8 second delay circuit 0.8S and polarity reversing switch K1.Wherein, the difference output homophase of input of the difference of described voltage comparator A1 and difference dateout driver A2 links to each other, and is connected to pin L1, L2 by polarity reversing switch K1; A1 outputs to pin RO by the input voltage of polarity reversing switch comparison L1, L2 pin; A2 amplifies the signal of input pin DI, output to L1, L2 pin by the polarity reversing switch difference, voltage comparator A1 is controlled by pin RE simultaneously, during RE=0, the A1 operate as normal, during RE=1, A1 exports high-impedance state, and A2 is controlled by pin DE, during DE=1, the A2 operate as normal, during DE=0, A2 exports high-impedance state.Polarity reversing switch K1 is controlled by the output of 0.8 second delay circuit 0.8S, and delay circuit 0.8S was subjected to A1 output control in 0.8 second; When A1 exported 0,0.8S picked up counting, and when A1 exported 1,0.8S resetted and freezes output; Continue more than 0.8 second when A1 exports 0,0.8S will export control signal, makes the polarity reversing switch action.

Claims

1. nonpolarity 485 chips is characterized in that: polarity reversing switch of serial connection on the data I of described 485 chips/O pin or the communication pin.