CN102999467A - High-speed interface and low-speed interface switching circuit and method based on FPGA (Field Programmable Gate Array) - Google Patents
High-speed interface and low-speed interface switching circuit and method based on FPGA (Field Programmable Gate Array) Download PDFInfo
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Abstract
The invention provides a high-speed interface and low-speed interface switching circuit and method based on an FPGA (Field Programmable Gate Array). The high-speed interface and low-speed interface switching circuit based on the FPGA comprises a high-speed parallel interface module, a high-speed writing control module, a high-speed reading control module, a first data caching FIFO (First In First Out) reading-writing module, a second data caching FIFO reading-writing module, a low-speed reading control module, a low-speed writing control module, a parallel-series switching module, a series-parallel switching module and a low-speed serial interface module. According to the high-speed interface and low-speed interface switching circuit and method based on the FPGA disclosed by the invention, the problem that data rates and interface protocols of a high-speed parallel interface and a low-speed serial interface are not matched in an embedded system can be solved, and meanwhile, full-duplex communication can be realized; and when an Xilinx Virtex-5 series FPGA is adopted, occupied logic resources are few and system integration is easy to realize.
Description
Technical field
The present invention relates to the change-over circuit between distinct interface bus, the different clock-domains and method in the digital circuitry, particularly a kind of high speed parallel interface and low-speed serial interface conversion circuit and method that realizes based on field programmable gate array (FPGA).
Background technology
The reliability transmission of mass data between distinct interface bus, the different clock-domains in the digital circuitry is the key issue in the Design of Digital Circuit always; In order to realize the reliable exchange of data between distinct interface bus, the different clock-domains, to avoid because the metastable state problem brought of asynchronous clock, interface conversion circuit is absolutely necessary.Existing various types of special purpose interface conversion chips in the market, but special purpose interface conversion chip restructural not, structure is single, and dirigibility is relatively poor.Along with the fast development of programmable logic device (PLD), adopt the abundant logical resource of FPGA to realize more simple and fast of interface conversion circuit, and the user can reconfigure according to demand to it.
Summary of the invention
The object of the invention is to, a kind of high-speed interface and low-speed interface change-over circuit and method that realizes based on FPGA is provided, it can solve data transfer rate and interface protocol mismatch problem between high speed parallel interface and the low-speed serial interface.
In order to address this problem, the present invention proposes a kind of high-speed interface and low-speed interface change-over circuit of realizing based on FPGA, comprising:
One high speed parallel interface module, it realizes the transmission of variable length data bag and data flow con-trol according to the control signal of one group of protocol-independent of characterizing definition of bus;
One high speed write control module, its first input end is connected with the first output terminal of high speed parallel interface module;
One high speed reads control module, its first output terminal is connected with the second input end of high speed parallel interface module;
One first data buffer storage FIFO module for reading and writing, its first input end and high speed write control module the first output terminal be connected, the first output terminal of this first data buffer storage FIFO module for reading and writing is connected with the second input end of high speed write control module, and the second input end of this first data buffer storage FIFO module for reading and writing is connected with the second output terminal of high speed parallel interface module;
One second data buffer storage FIFO module for reading and writing, its first output terminal is connected with the first input end of high speed parallel interface module, the first input end of this second data buffer storage FIFO module for reading and writing is connected with the second output terminal of high speed reads control module, and the second output terminal of this second data buffer storage FIFO module for reading and writing is connected with the first input end of high speed reads control module;
One low fast reading control module, its first output terminal is connected with the 3rd input end of the first data buffer storage FIFO module for reading and writing, and the first input end of this low fast reading control module is connected with the second output terminal of the first data buffer storage FIFO module for reading and writing;
One low literary sketch control module, its first output terminal is connected with the 3rd input end of the second data buffer storage FIFO module for reading and writing, and the first input end of this low literary sketch control module is connected with the 3rd output terminal of the second data buffer storage FIFO module for reading and writing;
Go here and there in the lump modular converter, its first input end is connected with the second output terminal of low fast reading control module, and the second input end of this parallel serial conversion module is connected with the 3rd output terminal of the first data buffer storage FIFO module for reading and writing;
A string and modular converter, its first output terminal is connected with the second input end of the second data buffer storage FIFO module for reading and writing, and the second output terminal of this string and modular converter is connected with the second input end of low literary sketch control module;
One low-speed serial interface module, its input end is connected with the first output terminal of parallel serial conversion module, and its output terminal is connected with the first input end of string and modular converter.
The present invention also provides a kind of high-speed interface based on the FPGA realization and the conversion method of low-speed interface change-over circuit, and it is to adopt change-over circuit claimed in claim 1, and this conversion method comprises the steps:
Step 1: when the first input end signal of high speed write control module effectively and the first data buffer storage FIFO module for reading and writing when non-full, the first data buffer storage FIFO module for reading and writing is write and is enabled, and writes in the first data buffer storage FIFO module for reading and writing in synchronous lower the second fan-out factor certificate with the high speed parallel interface module of the rising edge of high-frequency clock;
Step 2: when the first data buffer storage FIFO module for reading and writing non-NULL, the first data buffer storage FIFO module for reading and writing is read to enable, sense data is in parallel serial conversion module from the first data buffer storage FIFO module for reading and writing under the rising edge of low-speed clock is synchronous, and the second output end signal that sets low simultaneously the fast reading control module is effective;
Step 3: when the first input end signal of parallel serial conversion module is effective, the parallel data that parallel serial conversion module will be read from the first data buffer storage FIFO module for reading and writing is descended transformed into serial data synchronously at the low-speed clock rising edge, deliver to by turn on the first output terminal the mode of operation of configuring external serial device;
Step 4: string and modular converter convert the serial data of receiving on the 3rd input end to parallel data at the low-speed clock rising edge synchronously, deliver on the first output terminal, and it is effective to put simultaneously the second output end signal;
Step 5: when the second input end signal of low literary sketch control module effectively and the second data buffer storage FIFO module for reading and writing when non-full, the second data buffer storage FIFO module for reading and writing is write and is enabled, and will going here and there also synchronously at the rising edge of low-speed clock, the first fan-out factor certificate of modular converter writes in the second data buffer storage FIFO module for reading and writing;
Step 6: when the second data buffer storage FIFO module for reading and writing non-NULL, the reading of the second data buffer storage FIFO module for reading and writing enables, rising edge at high-frequency clock descends sense data to deliver to the first input end of high speed parallel interface module synchronously, and the first output end signal that sets high simultaneously the fast reading control module is effective.
Description of drawings
For further specifying technology contents of the present invention, be described in detail as follows below in conjunction with embodiment and accompanying drawing, wherein:
Fig. 1 is converting circuit structure synoptic diagram of the present invention;
Fig. 2 is the read-write operation synoptic diagram of the second data buffer storage FIFO module for reading and writing 5;
Fig. 3 is the embodiment that adopts the circuit structure realization of Fig. 1.
Embodiment
See also shown in Figure 1, Fig. 1 is converting circuit structure synoptic diagram provided by the invention, and this change-over circuit 100 comprises high speed parallel interface module 1, high speed write control module 2, high speed reads control module 3, the first data buffer storage FIFO module for reading and writing 4, the second data buffer storage FIFO module for reading and writing 5, low fast reading control module 6, low literary sketch control module 7, parallel serial conversion module 8, string and modular converter 9 and low-speed serial interface module 10.Wherein, high speed parallel interface module 1 realizes the transmission of variable length data bag and data flow con-trol according to the control signal of one group of protocol-independent of characterizing definition of parallel bus A; High speed write control module 2 is used for the data writing process of control the first data buffer storage FIFO module for reading and writing 4; High speed reads control module 3 is used for the data reading process of control the second data buffer storage FIFO module for reading and writing 5; The first data buffer storage FIFO module for reading and writing 4 is used for the data that temporary high speed parallel interface module 1 writes parallel serial conversion module 8; The second data buffer storage FIFO module for reading and writing 5 writes the data of high speed parallel interface module 1 for temporary string and modular converter 9; Low fast reading control module 6 is used for the data reading process of control the first data buffer storage FIFO module for reading and writing 4; Low literary sketch control module 7 is used for the data writing process of control the second data buffer storage FIFO module for reading and writing 5; Parallel serial conversion module 8 is used for the parallel data transformed into serial data; String and modular converter 9 are used for converting serial data to parallel data; 10 translations of low-speed serial interface module produce clock signal and the control signal of bus B, and the outside that driving is connected with bus B is from machine equipment.
Annexation between each module of concrete this change-over circuit 100 of formation is: high speed write control module 2, and its first input end 21 (the pin label in the module) is connected in the first output terminal 11 of high speed parallel interface module 1; High speed reads control module 3, its first output terminal 31 are connected in the second input end 14 of high speed parallel interface module 1; The first data buffer storage FIFO module for reading and writing 4, its first input end 41 is connected in the first output terminal 22 of high speed write control module 2, the first output terminal 42 of this first data buffer storage FIFO module for reading and writing 4 is connected in the second input end 23 of high speed write control module 2, and the second input end 43 of this first data buffer storage FIFO module for reading and writing 4 is connected in the second output terminal 12 of high speed parallel interface module 1; The second data buffer storage FIFO module for reading and writing 5, its first output terminal 51 is connected in the first input end 13 of high speed parallel interface module 1, the first input end 52 of this second data buffer storage FIFO module for reading and writing 5 is connected in the second output terminal 32 of high speed reads control module 3, and the second output terminal 53 of this second data buffer storage FIFO module for reading and writing 5 is connected in the first input end 33 of high speed reads control module 3; Low fast reading control module 6, its first output terminal 61 is connected in the 3rd input end 44 of the first data buffer storage FIFO module for reading and writing 4, and the first input end 62 of this low fast reading control module 6 is connected in the second output terminal 45 of the first data buffer storage FIFO module for reading and writing 4; Low literary sketch control module 7, its first output terminal 71 is connected in the 3rd input end 55 of the second data buffer storage FIFO module for reading and writing 5, and the first input end 72 of this low literary sketch control module 7 is connected in the 3rd output terminal 56 of the second data buffer storage FIFO module for reading and writing 5; Parallel serial conversion module 8, its first input end 81 are connected in the second output terminal 63 of low fast reading control module 6, and the second input end 82 of this parallel serial conversion module 8 is connected in the 3rd output terminal 46 of the first data buffer storage FIFO module for reading and writing 4; String and modular converter 9, its first output terminal 91 is connected in the second input end 54 of the second data buffer storage FIFO module for reading and writing 5, and the second output terminal 92 of this string and modular converter 9 is connected in the second input end 73 of low literary sketch control module 7; Low-speed serial interface module 10, its input end 101 are connected in the first output terminal 83 of parallel serial conversion module 8, and the output terminal 102 of this low-speed serial interface module 10 is connected in the first input end 93 of string and modular converter 9.
The first data buffer storage FIFO module for reading and writing 4 and the second data buffer storage FIFO module for reading and writing 5 all adopt the block RAM of FPGA inside to realize, are used for the isolation clock zone, the coupling read or write speed.Wherein, to write clock frequency fast for the clock frequency ratio of reading of the second data buffer storage FIFO module for reading and writing 5, so the degree of depth of the second data buffer storage FIFO module for reading and writing 5 only is required to be 2, concrete read-write operation step (consulting Fig. 2) is:
A) initial time, the low speed end carries out write operation to address 1;
B) in the moment 1, speed end is carried out read operation to address 1, and the low speed end carries out write operation to address 2 simultaneously;
C) in the moment 2, speed end is carried out read operation to address 2, and the low speed end carries out write operation to address 1 simultaneously;
D) repeating step b, c.
The clock of the clock of the clock of high speed parallel interface module 1, high speed write control module 2, high speed reads control module 3, the first data buffer storage FIFO module for reading and writing 4 write clock, the second data buffer storage FIFO module for reading and writing 5 to read the clock unification given by high-frequency clock A; The clock unification of the clock of the clock of reading the clock of writing clock, low fast reading control module 6 of clock, the second data buffer storage FIFO module for reading and writing 5, low literary sketch control module 7, string and the modular converter 8 of the first data buffer storage FIFO module for reading and writing 4, the clock of parallel serial conversion module 9 and low-speed serial interface module 10 is given by low-speed clock B.
The reset signal of modules is unified asynchronous reset or is resetted separately.
Concrete conversion method based on change-over circuit shown in Figure 1 is:
1) from the first bus A to the second bus B the transmission of data:
When first input end (1) signal of high speed write control module 2 effectively and the first data buffer storage FIFO module for reading and writing 4 when non-full, the first data buffer storage FIFO module for reading and writing 4 is write and is enabled, and writes in the first data buffer storage FIFO module for reading and writing 4 in synchronous lower the second output terminal 12 data with high speed parallel interface module 1 of the rising edge of high-frequency clock;
When the first data buffer storage FIFO module for reading and writing 4 non-NULL, the first data buffer storage FIFO module for reading and writing 4 is read to enable, sense data is in parallel serial conversion module 8 from the first data buffer storage FIFO module for reading and writing 4 under the rising edge of low-speed clock is synchronous, and the second output terminal 63 signals that set low simultaneously fast reading control module 6 are effective;
When first input end 81 signals of parallel serial conversion module 8 are effective, the parallel data that parallel serial conversion module 8 will be read from the first data buffer storage FIFO module for reading and writing 4 is descended transformed into serial data synchronously at the low-speed clock rising edge, deliver to by turn on the first output terminal 83 mode of operation of configuring external serial device;
2) from the second bus B to the first bus A the transmission of data:
String and modular converter 9 convert the serial data of receiving on the 3rd input end 93 to parallel data at the low-speed clock rising edge synchronously, deliver on the first output terminal 91, and it is effective to put simultaneously the second output terminal 92 signals;
When the second input end 73 signals of low literary sketch control module 7 effectively and the second data buffer storage FIFO module for reading and writing 5 when non-full, the second data buffer storage FIFO module for reading and writing 5 is write and is enabled, and will going here and there also synchronously at the rising edge of low-speed clock, the first output terminal 91 data of modular converter 9 write in the second data buffer storage FIFO module for reading and writing 5;
When the second data buffer storage FIFO module for reading and writing 5 non-NULL, the reading of the second data buffer storage FIFO module for reading and writing 5 enables, rising edge at high-frequency clock descends sense data to deliver to the first input end 13 of high speed parallel interface module 1 synchronously, and the first output terminal 31 signals that set high simultaneously fast reading control module 3 are effective.
Fig. 3 shows the embodiment of realizing according to the present invention.Employing the present invention has realized the full-duplex communication between high-speed parallel LocalLink interface 1 and the low-speed serial SPI interface 10.In a kind of specific embodiment, adopt the Virtex-5FPGA of Xilinx company to realize that bus A is the LocalLink bus, data width is 32; Bus B is spi bus; High-frequency clock A is 100Mhz, and low-speed clock B clock is 20Mhz; The degree of depth of the first data buffer storage FIFO module for reading and writing 4 is 1024, and width is 32, and the degree of depth of the second data buffer storage FIFO module for reading and writing 5 is 2, and width is 32; LocalLink interface 1 produces the LocalLink bus control signal, is connected with dma module 11; SPI interface 10 produces the spi bus control signal, is connected with ADC module 12; Concrete data transmission procedure is identical with conversion method.
More than explanation is just illustrative for the purpose of the present invention; and nonrestrictive, those of ordinary skills understand, in the situation that does not break away from the spirit and scope that following claims limit; can make many modifications, variation or equivalence, but all will fall within the scope of protection of the present invention.
Claims (8)
1. high-speed interface and low-speed interface change-over circuit of realizing based on FPGA comprises:
One high speed parallel interface module, it realizes the transmission of variable length data bag and data flow con-trol according to the control signal of one group of protocol-independent of characterizing definition of bus;
One high speed write control module, its first input end is connected with the first output terminal of high speed parallel interface module;
One high speed reads control module, its first output terminal is connected with the second input end of high speed parallel interface module;
One first data buffer storage FIFO module for reading and writing, its first input end and high speed write control module the first output terminal be connected, the first output terminal of this first data buffer storage FIFO module for reading and writing is connected with the second input end of high speed write control module, and the second input end of this first data buffer storage FIFO module for reading and writing is connected with the second output terminal of high speed parallel interface module;
One second data buffer storage FIFO module for reading and writing, its first output terminal is connected with the first input end of high speed parallel interface module, the first input end of this second data buffer storage FIFO module for reading and writing is connected with the second output terminal of high speed reads control module, and the second output terminal of this second data buffer storage FIFO module for reading and writing is connected with the first input end of high speed reads control module;
One low fast reading control module, its first output terminal is connected with the 3rd input end of the first data buffer storage FIFO module for reading and writing, and the first input end of this low fast reading control module is connected with the second output terminal of the first data buffer storage FIFO module for reading and writing;
One low literary sketch control module, its first output terminal is connected with the 3rd input end of the second data buffer storage FIFO module for reading and writing, and the first input end of this low literary sketch control module is connected with the 3rd output terminal of the second data buffer storage FIFO module for reading and writing;
Go here and there in the lump modular converter, its first input end is connected with the second output terminal of low fast reading control module, and the second input end of this parallel serial conversion module is connected with the 3rd output terminal of the first data buffer storage FIFO module for reading and writing;
A string and modular converter, its first output terminal is connected with the second input end of the second data buffer storage FIFO module for reading and writing, and the second output terminal of this string and modular converter is connected with the second input end of low literary sketch control module;
One low-speed serial interface module, its input end is connected with the first output terminal of parallel serial conversion module, and its output terminal is connected with the first input end of string and modular converter.
2. high-speed interface and the low-speed interface change-over circuit of realizing based on FPGA according to claim 1, the clock of the clock of wherein said high speed parallel interface module, high speed write control module, the clock of high speed reads control module, the first data buffer storage FIFO module for reading and writing write clock, the second data buffer storage FIFO module for reading and writing to read the clock unification given by high-frequency clock; The clock of the clock of reading the clock of writing clock, low fast reading control module of clock, the second data buffer storage FIFO module for reading and writing, low literary sketch control module of the first data buffer storage FIFO module for reading and writing, clock, string and the modular converter of parallel serial conversion module and the clock unification of low-speed serial interface module are given by low-speed clock.
3. high-speed interface and the low-speed interface change-over circuit of realizing based on FPGA according to claim 1, the reset signal of wherein said modules is unified asynchronous reset or is resetted separately.
4. high-speed interface and the low-speed interface change-over circuit of realizing based on FPGA according to claim 1, wherein said the first data buffer storage FIFO module for reading and writing and the second data buffer storage FIFO module for reading and writing all adopt the block RAM realization of FPGA inside; Be used for the isolation clock zone, the coupling read or write speed.
5. high-speed interface and the conversion method of low-speed interface change-over circuit of realizing based on FPGA, it is employing change-over circuit claimed in claim 1, this conversion method comprises the steps:
Step 1: when the first input end signal of high speed write control module effectively and the first data buffer storage FIFO module for reading and writing when non-full, the first data buffer storage FIFO module for reading and writing is write and is enabled, and writes in the first data buffer storage FIFO module for reading and writing in synchronous lower the second fan-out factor certificate with the high speed parallel interface module of the rising edge of high-frequency clock;
Step 2: when the first data buffer storage FIFO module for reading and writing non-NULL, the first data buffer storage FIFO module for reading and writing is read to enable, sense data is in parallel serial conversion module from the first data buffer storage FIFO module for reading and writing under the rising edge of low-speed clock is synchronous, and the second output end signal that sets low simultaneously the fast reading control module is effective;
Step 3: when the first input end signal of parallel serial conversion module is effective, the parallel data that parallel serial conversion module will be read from the first data buffer storage FIFO module for reading and writing is descended transformed into serial data synchronously at the low-speed clock rising edge, deliver to by turn on the first output terminal the mode of operation of configuring external serial device;
Step 4: string and modular converter convert the serial data of receiving on the 3rd input end to parallel data at the low-speed clock rising edge synchronously, deliver on the first output terminal, and it is effective to put simultaneously the second output end signal;
Step 5: when the second input end signal of low literary sketch control module effectively and the second data buffer storage FIFO module for reading and writing when non-full, the second data buffer storage FIFO module for reading and writing is write and is enabled, and will going here and there also synchronously at the rising edge of low-speed clock, the first fan-out factor certificate of modular converter writes in the second data buffer storage FIFO module for reading and writing;
Step 6: when the second data buffer storage FIFO module for reading and writing non-NULL, the reading of the second data buffer storage FIFO module for reading and writing enables, rising edge at high-frequency clock descends sense data to deliver to the first input end of high speed parallel interface module synchronously, and the first output end signal that sets high simultaneously the fast reading control module is effective.
6. the high-speed interface of realizing based on FPGA according to claim 5 and the conversion method of low-speed interface change-over circuit, the clock of the clock of wherein said high speed parallel interface module, high speed write control module, the clock of high speed reads control module, the first data buffer storage FIFO module for reading and writing write clock, the second data buffer storage FIFO module for reading and writing to read the clock unification given by high-frequency clock; The clock of the clock of reading the clock of writing clock, low fast reading control module of clock, the second data buffer storage FIFO module for reading and writing, low literary sketch control module of the first data buffer storage FIFO module for reading and writing, clock, string and the modular converter of parallel serial conversion module and the clock unification of low-speed serial interface module are given by low-speed clock.
7. according to claim 5 based on the high-speed interface of FPGA realization and the conversion method of low-speed interface change-over circuit, the reset signal of wherein said modules is unified asynchronous reset or is resetted separately.
8. according to claim 5 based on the high-speed interface of FPGA realization and the conversion method of low-speed interface change-over circuit, wherein said the first data buffer storage FIFO module for reading and writing and the second data buffer storage FIFO module for reading and writing all adopt the block RAM of FPGA inside to realize; Be used for the isolation clock zone, the coupling read or write speed.
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