CN2585416Y - 半导体芯片与布线基板、半导体晶片、半导体装置、线路基板以及电子机器 - Google Patents
半导体芯片与布线基板、半导体晶片、半导体装置、线路基板以及电子机器 Download PDFInfo
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- CN2585416Y CN2585416Y CN02252398U CN02252398U CN2585416Y CN 2585416 Y CN2585416 Y CN 2585416Y CN 02252398 U CN02252398 U CN 02252398U CN 02252398 U CN02252398 U CN 02252398U CN 2585416 Y CN2585416 Y CN 2585416Y
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- passivation film
- etching
- semiconductor
- semiconductor chip
- resist layer
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Abstract
本实用新型涉及半导体芯片与布线基板、半导体晶片、半导体装置、线路基板以及电子机器。所述半导体芯片在集成电路上电连接多个底垫(12);钝化膜(14)覆盖底垫(12)的一部分而露出其他部分;在底垫(12)上形成有接块(30);接块(30)是置于底垫(12)从钝化膜(14)露出的部分和钝化膜(14)上的单一层。所形成的接块可以防止水分进入衬底层。
Description
技术领域
本实用新型涉及半导体芯片与布线基板、半导体晶片、半导体装置、线路基板以及电子机器。
背景技术
随着半导体集成电路的高集成化与半导体芯片缩小化的发展,需要能够与微细间距端子连接相配套的组装技术。作为容易与该需要对应的组装技术,譬如可以举出TCP(Tape Carrier Package,载带封装)等采用的TAB(Tape Automated Boding,带式自动键合)封装、CSP(Chip SizePackage,芯片水平封装)等采用的倒装片封装。
按上述封装技术,通常要在半导体芯片的底垫上设接块(bump)。具有代表性的接块譬如有Au接块,其一般是采用电解电镀形成。下面说明一下电解电镀法构成的Au接块的形成方法。
图14是已有半导体芯片的Au接块的截面图。作为连接于内部集成电路的布线之一部分的接块底垫12,除了电连接区表面而外都被钝化膜14所覆盖。
首先,利用溅射法形成底部接块金属层(阻碍金属层与密接性金属层之叠层)1。其后,利用光刻技术让底垫12的电连接区及其周围露出的形成接块用的抗蚀层2。接着,利用电解电镀法按抗蚀层2的图案镀Au。随后剥离抗蚀层2,以镀成的Au为掩模并相应于底部接块金属层1的种类来湿法蚀刻底部接块金属层1。然后,经过退火等形成接块3。另外还在各处实施清洗工序。可见,采用电解电镀法形成接块的工序较长,需要进一步缩短、合理化。
对此,最近提出了采用无电解电镀法形成接块的方法。采用无电解电镀法形成接块时,至少可以不要底部接块金属层的溅射形成工序及蚀刻工序。因此,可以大幅度地缩短制造工序、廉价地形成接块。但是,由于采用无电解电镀法形成接块时不形成底部接块金属层,所以必须要防止底垫进水。
实用新型内容
本实用新型目的就在于提供一种可以形成防止衬低层进水的接块的半导体芯片与布线基板、半导体晶片、半导体装置、线路基板以及电子机器。
本实用新型目的实现如下。
(1)一种半导体晶片,其中,具有多个集成电路、与各所述集成电路电连接的多个底垫、覆盖各所述底垫的一部分而露出其他部分的钝化膜、以及形成于各所述底垫上的接块;所述接块是置于所述底垫从所述钝化膜露出的部分和所述钝化膜上的单一层。
根据本实用新型,由于所述接块是连着钝化膜而覆盖于底垫上的,故可以防止水分进入底垫。而且,由于覆盖着底垫的是单一层,所以防止进水效果强。
(2)在该半导体晶片中,可在所述接块外侧形成有第二层。
(3)一种半导体芯片,其中,具有集成电路、与所述集成电路电连接的多个底垫、覆盖各所述底垫的一部分而露出其他部分的钝化膜、以及形成于各所述底垫上的接块;所述接块是置于所述底垫从所述钝化膜露出的部分和所述钝化膜上的单一层。
根据本实用新型,由于所述接块是连着钝化膜而覆盖于底垫上的,故可以防止水分进入底垫。而且,由于覆盖着底垫的是单一层,所以防止进水效果强。
(4)在(3)所述的半导体芯片中,可在所述接块外侧形成有第二层。
(5)一种半导体装置,其中,具有所述半导体芯片、组装有所述半导体芯片的基板、及外部端子。
(6)一种电路基板,其中,组装有所述半导体芯片。
(7)一种电路基板,其中,组装有所述半导体装置。
(8)一种电子机器,其中,具有所述半导体装置。
(9)一种布线基板,其特征在于,包括具有凸台的布线图案、覆盖所述凸台之一部分而使其他部分露出的绝缘膜、以及形成于所述凸台的接块;所述接块是置于所述凸块从所述绝缘膜露出部分及所述绝缘膜上的单一层。
根据本实用新型,由于接块是连着绝缘膜而覆盖于凸台上的,故可以防止水分进入凸台。而且,由于覆盖着凸台的接块是单一层,所以防止进水效果强。
附图说明
图1A-1D是本实用新型实施例1的半导体芯片制造方法的说明图。
图2是本实用新型实施例1的半导体芯片制造方法的说明图。
图3是本实用新型实施例1的半导体装置的说明图。
图4是组装了本实用新型实施例1的半导体芯片的电路基板的示意图。
图5是组装了本实用新型实施例1的半导体芯片的电路基板的示意图。
图6是组装了图3所示半导体装置的电路基板的示意图。
图7是具有本实用新型实施例的半导体装置的电子机器的示意图。
图8是具有本实用新型实施例的半导体装置的电子机器的示意图。
图9A、9B是本实用新型实施例2的半导体芯片制造方法的说明图。
图10A、10B是本实用新型实施例3的半导体芯片制造方法的说明图。
图11A-11C是本实用新型实施例4的半导体芯片制造方法的说明图。
图12A、12B是本实用新型实施例5的半导体芯片制造方法的说明图。
图13是本实用新型实施例6的布线基板制造方法的说明图。
图14是本实用新型的已有技术的说明图。
具体实施方式
下面参照附图来说明一下本实用新型的实施例。
实施例1
图1A-1D是本实用新型实施例1的半导体芯片制造方法的说明图。图2是本实用新型实施例1的半导体芯片制造方法的说明图。在本实施例中,半导体晶片10在主体(半导体基板及其上绝缘膜)上方具有底垫12。首先,如图1A所示,在覆盖底垫12的钝化膜14(保护用绝缘膜)上形成抗蚀层20。底垫12譬如可以用铝构成。底垫12同主体(半导体基板及其上绝缘膜)内或半导体基板上设的集成电路16(参见图2)电连接。多个集成电路16形成于半导体晶片10。半导体晶片10可切割(dicing或scribing)成多个半导体芯片,各半导体芯片具有集成电路16。半导体晶片10主体具有集成电路16,譬如具有晶体管和保护晶体管的层间绝缘膜。底垫12设于层间绝缘膜上方。钝化膜14形成于半导体晶片10的主体和底垫12之上。钝化膜14也可是半导体晶片10的最上层。钝化膜14可以CVD(化学气相生长法)形成。
钝化膜14可以避开切割线(譬如dicing线或scribing线)而形成。钝化膜14可以采用SiO2、SiN、聚酰亚胺等树脂等构成。钝化膜14既可以是单层也可以是多层。
抗蚀层20可以能量(光、电子射线、X射线等)感应材料(譬如感光性树脂)形成。抗蚀层20可以是感光性聚酰亚胺树脂。抗蚀层20在底垫12局部(譬如中央部)上方具有开口22。开口22可以利用刻膜(如光刻)形成。
如图1B所示,以抗蚀层20为掩模进行蚀刻,在钝化膜14上形成开口22。蚀刻既可用湿法蚀刻也可用干法蚀刻。
对钝化膜14进行蚀刻,使底垫12部分(譬如端部)被覆盖部分(譬如中央部)被露出。即,在底垫12上的钝化膜14上形成比底垫12上表面(其上设有钝化膜14的表面)面积小的开口部。钝化膜14可以干法蚀刻或湿法蚀刻进行蚀刻。通过以高各向异性干法蚀刻譬如使用含Ar或CF4蚀刻气体的干式蚀刻(譬如反应性离子蚀刻)来蚀刻部分钝化膜14,可以进行高各向异性蚀刻。
钝化膜14的开口也可以采用以Ar或CF4与O2的混合气体为蚀刻气体的干法蚀刻(譬如反应性离子蚀刻)来进行。譬如采用含有O2与CF4的蚀刻气体,这时蚀刻条件可以是:O2与CF4的比例为O2∶CF4=2∶1-1∶5;最好是O2∶CF4=2∶1-1∶2。
若为叶片式蚀刻,则压力可为80-250Pa、Rf功率可为100-200W。若钝化膜14是SiO2膜,则可以采用湿法蚀刻及干法蚀刻。钝化膜14含有SiN膜时以干法蚀刻为主,但若需要带锥度的话,则也可以采用湿法蚀刻。当钝化膜14(绝缘膜)由多层构成时也可以适当采用湿法蚀刻及干法蚀刻。
另外,在设有抗蚀层20的开口22的区域设置比开口22的开口面积大的开口24。开口面积是指抗蚀层20在同钝化膜14接触一侧的开口面积。也可以将抗蚀层20蚀刻得其开口22比底垫12局部(譬如中央部)大。即,可让开口24的开口面积比底垫12上表面(其上设有钝化膜14的表面)面积大。也可以蚀刻抗蚀层20的开口22的内壁面。也可以利用比起各向异性来各向同性高的蚀刻来蚀刻抗蚀层20。譬如,在使用含有O2的蚀刻气体的等离子体蚀刻(譬如反应性粒子蚀刻、使用氧等离子体的等离子体蚀刻)中通过反应气体同抗蚀层20的反应可以蚀刻抗蚀层20。若采用使用氧等离子体的等离子体蚀刻,反应气体会被氧基积激活,抗蚀层20蚀刻速度变快。这时,可以通过改变蚀刻条件来对抗蚀层20进行各向同性蚀刻,控制在给定范围量进行蚀刻。即,可以通过进一步对抗蚀层20进行各向同性蚀刻形成开口24,使抗蚀层20上设的开口22自横向扩展。另外,也可以各向异性高的干蚀刻除去开口22周围的抗蚀层。这样容易控制开口形状。
在本实施例中,钝化膜14的蚀刻和为扩大抗蚀层20的开口22的蚀刻既可以同一工序进行也可分别以不同工序进行。
蚀刻结束后,在扩大了的开口24的内侧会有钝化膜14突出出来。开口24的开口面积也可大于钝化膜14的底垫12上的开口的开口面积。即,在扩大了的开口24的内侧,底垫12的一部分(譬如中央)从钝化膜14露出,在底垫12的其他部分(譬如端部)置有钝化膜14。也可以让钝化膜14带有某种程度的锥度,即让钝化膜14覆盖底垫12的部分自底垫12的露出部(譬如中央部)朝斜上方倾斜。即,可以让钝化膜14的开口面积自底垫12一侧朝抗蚀层20一侧趋向增大。底垫12的侧面被钝化膜14所覆盖。抗蚀层20构成规定无电解电镀生长方向的部件。可在接下来的无电解电镀工序之前利用UV照射等固化抗蚀层20。
如图1C所示,通过无电解电镀形成接块30。譬如,在抗蚀层20的开口24内对Al形成的底垫12的从钝化膜14露出的面镀锌酸盐处理。譬如将半导体晶片10浸入含有Zn离子的处理液中,通过 反应来将Al置换为Zn。据此可将底垫12的露出面置换为Zn。其后,可以将半导体晶片10浸入无电解镀Ni液(以Ni离子、还原剂(一般为次磷酸钠)、稳定剂、缓冲剂为主要成分的液体),通过Zn和Ni的置换反应来堆积Ni。或者,也可以将Al浸入只选择性地吸附于Al上的钯溶液中,然后再浸入无电解镀Ni液中,让Ni以钯为核析出。
靠无电解电镀析出的金属(譬如为Ni)自底垫12的露出面也向横向扩展,也延伸于钝化膜14上,在抗蚀层20的内壁面停止向横向扩展。只要开口24的内壁面垂直于底垫12而直立,就能形成垂直而立的接块30。当在抗蚀层20上端部开口24的内壁面经上述蚀刻后倾斜的场合,也可以在内壁面垂直而立的区域(连续性强的图案区)结束无电解镀Ni。
这样,就可以在抗蚀层20的扩大了的开口24内的底垫12之一部分(譬如中央部)及钝化膜14上形成单一层的接块30。由于接块30是连着钝化膜14而覆盖于底垫12上的,故可以防止水分进入底垫12。而且,由于接块30为单一层,所以防止进水效果强。由于接块30置于钝化膜14之上,所以上面也可以为凹面。这时接块30上端部易破损也可。
接着,如图1D所示,除去抗蚀层20。也可以在接块30上形成第二层32。第二层32可利用无电解电镀形成。第二层32可以用Au形成。譬如,可以将半导体晶片10浸入电镀液(以Au离子、还原剂、稳定剂、缓冲剂为主要成分的液体),进行无电解镀Au。可以对电镀时间进行控制,以使Au自析出量在0.4μm以上。即,由于镀Au析出速度同镀Ni析出速度量相比极慢,所以只要第二层32的厚度在0.4μm以上即可结束电镀。其后,进行清洗即可形成第二层32。靠镀Au形成的第二层32可以得到良好的电连接。也可将第二层32置于钝化膜14上。也可以使形成的第二层32密封接块30。
在本实施例中,利用使用不同电镀液、使2层以上的不同金属析出生长的无电解电镀液来形成接块。电镀材料可以参考电镀生长速度、电阻及连接性等来选择高效的材料。由于镀Au析出速度同镀Ni析出速度量相比极慢,所以接块30及第二层32的整个高度的99%都可以Ni形成。
在无电解电镀工序中,当处理液接触到半导体晶片10的背面时,有时会形成对接地电位(或不稳定电位)的导电通路,各底垫12的电位变得不稳定(接地效应)。对此,可让电镀的处理液只与半导体晶片10的主表面(形成接块30的面)接触。即采取这样的措施:不让镀锌酸盐处理、无电解镀Ni、无电解镀Au等的处理液接触半导体晶片10主表面以外部分。譬如,在使用浸泡式处理槽的场合,可以使用密封半导体晶片10背面一侧的支持体,或在不损伤半导体晶片10主表面一侧的情况下在背面涂抹抗蚀剂。或者,也可以采用盖罩方式,即在半导体晶片10主表面周围部加处理盖罩,等等。还可以采取其他措施。据此,在镀锌酸盐处理、各种无电解电镀处理中可以不受底垫电位所左右,能防止接地效应之影响。
根据本实施例,可以通过比电解电镀能大幅度地缩短制造步骤的无电解电镀来形成接块30。另外,一旦形成了接块30,其不仅可以当作蚀刻钝化膜14(绝缘膜)用的掩模使用,还可以起到规定无电解电镀生长方向的部件的作用。据此,可大幅度地缩短和合理化制造步骤、提高生产效率和可靠性。另外,由于无需再次涂抹抗蚀剂及刻模工序,所以不需要应对位置偏差的区域,故容易实现可以应对窄间距的接块。
另外,作为变形例,也可以用Cu形成接块30。这时,可以将半导体晶片10浸入以Au离子、还原剂、稳定剂、缓冲剂为主要成分的电镀液中,让Au自析出。另外,也可以Sn取代Cu来形成第二层32。
如图2所示,利用工具40(切丁机等切割机或划线器)切断半导体晶片10,可以得到一个个半导体芯片。另外,也可对半导体芯片实施上述工序来形成接块30。
经上述工序的半导体晶片10具有多个集成电路16,各集成电路16电连接有多个底垫12。钝化膜14覆盖各底垫12的一部分(譬如中央部),而让其他部分露出。在各底垫12上形成有接块30。接块30的一部分是置于底垫12从钝化膜14露出的部分和钝化膜14上的单一层。也可在接块30外侧形成第二层32。
图3是本实用新型实施例1的半导体装置的示意图。半导体装置具有半导体芯片50,半导体芯片50具有集成电路16,集成电路16电连接有多个底垫12。钝化膜14覆盖各底垫12的一部分(譬如中央部),而让其他部分露出。在各底垫12上形成有接块30。接块30的一部分是置于底垫12从钝化膜14露出的部分和钝化膜14上的单一层。也可在接块30外侧形成第二层32。
半导体芯片50安装在基板52(譬如陶瓷基板或柔性基板等)上。在基板52上形成有布线图案54,布线图案54与接块30电连接。若使用各向异性导电材料(各向异性导电膜或各向异性导电膏等)进行电连接、接块30或第二层32上面呈凹面时,容易在所述凹面捕捉导电粒子。那么,可以在捕捉到导电粒子的情况下,接块30或第二层32溃落、进行良好的接合。使用导电性材料(导电膏等)也一样。布线图案54与接块30的电连接以金属接合为宜,也可以使用绝缘性粘接剂。也可以在基板52上设置外部端子56(譬如焊锡球)。
图4是组装了本实用新型实施例1的半导体芯片的电路基板之示意图。电路基板60(主印刷电路板)上组装(譬如倒装片接合)有上述半导体芯片50。另外,在电路基板60上还形成有未图示的布线图案。
图5是组装了本实用新型实施例1的半导体芯片的半导体装置之示意图。半导体装置是通过在基板70上组装半导体芯片50,实施TCP(TapeCarrier Package,载带封装)而构成的。该半导体装置被接合于电子面板72(譬如液晶面板、电致发光面板)。另外,半导体芯片50的组装形态也可是COG(Chip On Glass)、COF(Chip On Film/Flexible)。
图6给出了组装了图3所示的半导体装置的电路基板80。作为具有应用本实用新型的半导体装置的电子机器,在图7中给出了笔记本型个人电脑90,在图8给出了携带电话100。
实施例2
图9A、9B是本实用新型实施例2的半导体芯片制造方法的说明图。在本实施例中也是以图1A所示的具有开口22的抗蚀层20为掩模,让底垫12的一部分(譬如中央)从钝化膜14露出,同时让抗蚀层20的开口22扩大。而本实施例同实施例1不同之处在于:如图9A所示,扩大了的开口102的内壁面倾斜。这种倾斜是因物理性蚀刻作用的蚀刻而产生的。
为此,本实施例中应用比使抗蚀层20的开口22扩大的蚀刻的物理蚀刻效应小的(譬如化学性蚀刻效应大)的第二蚀刻,让抗蚀层20的开口102进一步扩大。作为第二蚀刻,既可以采用干式蚀刻也可以采用湿式蚀刻(利用喷淋器对底垫12垂直地喷淋蚀刻液的湿式蚀刻)。第二蚀刻也可以在用UV照射等固化抗蚀层20之前进行。这样,如图9B所示,可以形成具有相对于底垫12垂直而立的内壁面的开口104。于是能形成垂直而立的接块。本实施例也可以达到实施例1所说明的效果。另外,在本实施例中,也可以适用于实施例1所说明的内容。进一步,也可以将本实施例所说明的内容应用于其他实施例。
实施例3
图10A、10B是本实用新型实施例3的半导体芯片制造方法的说明图。如图10A所示,在本实施例中,以图1A所示的具有开口22的抗蚀层20为掩模,对钝化膜14进行蚀刻,使底垫12的一部分(譬如端部)仍被覆盖而让底垫12的其它部分(譬如中央部)露出。该蚀刻可以在最适于钝化膜14蚀刻的条件(譬如物理性腐蚀效应变大的条件)下进行。抗蚀层20不蚀刻也行,蚀刻也可。
接着,如图10B所示,对抗蚀层20进行蚀刻,使开口22扩大。该蚀刻可以最适于抗蚀层20蚀刻的条件(譬如化学性蚀刻作用变大的条件)下进行。钝化膜14不蚀刻也行,蚀刻也可。
在本实施例中,由于钝化膜14和抗蚀层20的蚀刻分别是在最佳条件下进行的,所以可以进行良好的蚀刻。譬如,可以扩大抗蚀层20的开口22,形成具有相对于底垫12垂直而立的内壁面的、扩大了的开口半导体晶片106。于是能形成垂直而立的接块。本实施例也可以达到实施例1所说明的效果。另外,在本实施例中,也可以适用于实施例1所说明的内容。进一步,也可以将本实施例所说明的内容应用于其他实施例。
实施例4
图11A-11C是本实用新型实施例4的半导体芯片制造方法的说明图。如图11A所示,在本实施例中,以图1A所示的具有开口22的抗蚀层20为掩模,对钝化膜14进行蚀刻(第一蚀刻),使底垫12的一部分(譬如端部)仍被覆盖而让底垫12的其它部分(譬如中央部)露出。该蚀刻可以在最适于钝化膜14蚀刻的条件(譬如物理性蚀刻作用变大的条件)下进行。抗蚀层20不蚀刻也行,蚀刻也可。
接着,如图11B所示,对抗蚀层20的除了下端部110以外的部分进行蚀刻(第二蚀刻),使开口22扩大。譬如,蚀刻开口22的内壁面。可以不蚀刻抗蚀层20的下端部110,即便蚀刻,其蚀刻量也比其它部分(如上端部及中央部)的少。这样即形成了抗蚀层20的被扩大了的开口108。开口108中,由抗蚀层20的下端部110形成的孔比下端部110以外部分(譬如上端部及中央部)所形成的孔小,因此抗蚀层20的下端部110覆盖着钝化膜14(譬如其上面)。
接着,如图11C所示,对抗蚀层20的下端部110进行蚀刻(第三蚀刻),以让开口108进一步扩大。对比第二蚀刻,可以让第三蚀刻的对抗蚀层20的钝化膜14的蚀刻选择比高。这样即形成了抗蚀层20的进一步被扩大了的开口112。在开口112内侧有钝化膜14突出出来。在第三蚀刻中,由于要让钝化膜14露出于开口112内,所以适用对钝化膜14的影响要小于第二蚀刻的条件。
在本实施例中,通过两阶段蚀刻(第二及第三蚀刻)来扩大开口22。第二蚀刻的对抗蚀层20的蚀刻速度可以比第三蚀刻的小。另外,第二蚀刻的对抗蚀层20的钝化膜14的蚀刻选择比可以比第三蚀刻的低。然而,即便将开口22扩大成开口108,抗蚀层20的下端部110也仍然留在钝化膜14上。据此,可减少蚀刻对钝化膜14的影响。另外,第二蚀刻不蚀刻钝化膜14,或者,即便蚀刻也可在蚀刻量少的条件下进行。
根据本实施例,可以在减少对钝化膜14影响的情况下形成接块。本实施例也可以达到实施例1所说明的效果。另外,在本实施例中,也可以适用于实施例1所说明的内容。进一步,也可以将本实施例所说明的内容应用于其他实施例。
实施例5
图12A、12B是本实用新型实施例5的半导体芯片制造方法的说明图。如图12A所示,在本实施例中,在覆盖底垫12的钝化膜14上形成了于底垫12之一部分(譬如中央部)具有第一开口122的第一抗蚀层120。第一抗蚀层120及开口122相当于实施例1所说明的抗蚀层20及开口22。
然后,以第一抗蚀层120为掩模,对钝化膜14进行蚀刻,使底垫12的一部分(譬如端部)仍被覆盖而让底垫12的其它部分(譬如中央部)露出。该蚀刻可以在最适于钝化膜14蚀刻的条件(譬如物理性蚀刻作用变大的条件)下进行。抗蚀层120不蚀刻也行,蚀刻也可。然后除去第一抗蚀层120。
接着,如图12B所示,形成具有比底垫12从钝化膜14露出部分(譬如中央部)还大的第二开口132的第二抗蚀层130。在第二开口132内配置底垫12从钝化膜14露出部分(譬如中央部)和钝化膜14的一部分。在本实施例中,在钝化膜14蚀刻时使用第一抗蚀层120,在形成接块时使用不同于此的第二抗蚀层130。因此,可以使用分别具有最适于对应工序的形状(开口122、132)的第一抗蚀层120和第二抗蚀层130。
于是,如实施例1中所说明的那样,利用无电解电镀来形成接块。本实施例也可以达到实施例1所说明的效果。另外,在本实施例中,也可以适用于实施例1所说明的内容。进一步,也可以将本实施例所说明的内容应用于其他实施例。
实施例6
图13是根据本实用新型实施例6的布线基板的制造方法的说明图。在本实施例中,在基板140上形成有部分布线图案即凸台142。凸台142被绝缘膜144(譬如Solder Resist——钎料抗蚀层)所覆盖。于是,相对凸台142形成接块。其细节是:将实施例1的底垫12置换成凸台142,将钝化膜14置换成绝缘膜144。这样即可以制造出形成有接块的布线基板。本实施例也可以达到实施例1所说明的效果。另外,在本实施例中,也可以适用于实施例1所说明的内容。进一步,也可以将本实施例所说明的内容应用于其他实施例。
本实用新型并非仅限于上述实施例,可以有种种变形。譬如,本实用新型包括同实施例所说明的结构实质上一样的结构(譬如功能、方法及效果一样的结构,或目的、效果一样的结构)。另外,本实用新型还包括同实施例所说明的结构具有同样作用效果的结构或可以达到同一目的的结构。另外,本实用新型还包括在实施例所说明的结构上附加了公知技术的结构。
Claims (9)
1.一种半导体晶片,其中,具有多个集成电路、与各所述集成电路电连接的多个底垫、覆盖各所述底垫的一部分而露出其他部分的钝化膜、以及形成于各所述底垫上的接块;所述接块是置于所述底垫从所述钝化膜露出的部分和所述钝化膜上的单一层。
2.按权利要求1所述的半导体晶片,其特征在于:在所述接块外侧形成有第二层。
3.一种半导体芯片,其中,具有集成电路、与所述集成电路电连接的多个底垫、覆盖各所述底垫的一部分而露出其他部分的钝化膜、以及形成于各所述底垫上的接块;所述接块是置于所述底垫从所述钝化膜露出的部分和所述钝化膜上的单一层。
4.按权利要求3所述的半导体芯片,其特征在于:在所述接块外侧形成有第二层。
5、一种半导体装置,其中,具有权利要求3或4所述的半导体芯片、组装有所述半导体芯片的基板、及外部端子。
6、一种电路基板,其中,组装有权利要求3或4所述的半导体芯片。
7、一种电路基板,其中,组装有权利要求5所述的半导体装置。
8、一种电子机器,其中,具有权利要求5所述的半导体装置。
9、一种布线基板,其特征在于,包括具有凸台的布线图案、覆盖所述凸台之一部分而使其他部分露出的绝缘膜、以及形成于所述凸台的接块;所述接块是置于所述凸块从所述绝缘膜露出部分及所述绝缘膜上的单一层。
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- 2002-08-29 JP JP2002250773A patent/JP2003203940A/ja active Pending
- 2002-10-22 US US10/277,114 patent/US6924553B2/en not_active Expired - Fee Related
- 2002-10-24 CN CN02252398U patent/CN2585416Y/zh not_active Expired - Lifetime
- 2002-10-24 CN CNB021480702A patent/CN1208830C/zh not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100472739C (zh) * | 2004-11-08 | 2009-03-25 | Tel艾派恩有限公司 | 铜互连布线和形成铜互连布线的方法 |
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Publication number | Publication date |
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US20030080420A1 (en) | 2003-05-01 |
US6924553B2 (en) | 2005-08-02 |
JP2003203940A (ja) | 2003-07-18 |
CN1208830C (zh) | 2005-06-29 |
CN1414630A (zh) | 2003-04-30 |
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