CN205177842U - 绝缘体上硅类型的衬底和集成电路 - Google Patents

绝缘体上硅类型的衬底和集成电路 Download PDF

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CN205177842U
CN205177842U CN201520964778.4U CN201520964778U CN205177842U CN 205177842 U CN205177842 U CN 205177842U CN 201520964778 U CN201520964778 U CN 201520964778U CN 205177842 U CN205177842 U CN 205177842U
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thickness
semiconductor film
dielectric
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D·佩蒂特
F·蒙塞尤尔
X·费德斯佩尔
G·比达尔
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STMicroelectronics SA
STMicroelectronics Crolles 2 SAS
STMicroelectronics SRL
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Abstract

提供了一种绝缘体上硅类型的衬底和集成电路。该绝缘体上硅类型的衬底，包括半导体膜，该半导体膜在不同衬底区域中具有不同厚度并且存在于本身位于相同载体衬底顶部的相同掩埋绝缘层上。

Description

绝缘体上硅类型的衬底和集成电路
技术领域
本实用新型涉及集成电路，并且更具体地涉及从本领域技术人员通常以缩写“SOI”表示的绝缘体上硅类型的相同衬底开始形成不同厚度的薄膜，并且更具体地涉及本领域技术人员以缩写“FDSOI”公知的全耗尽绝缘体上硅类型的衬底。
背景技术
绝缘体上硅类型的衬底通常包括具有统一厚度的例如硅的或硅合金的半导体膜，该半导体膜存在于埋入绝缘层上，该埋入绝缘层通常由缩写“BOX”来表示(“掩埋氧化物”)，其本身位于承载衬底顶部，例如半导体阱。
具体地，在FDSOI技术中，半导体膜是完全耗尽的，这确保良好的静电控制。
通常来说，半导体膜非常薄，例如约几纳米。此外，掩埋绝缘层通常非常薄，约20纳米。
然而，在一些应用中，可能有必要在同一SOI或FDSOI衬底上形成具有不同厚度的栅极氧化物的晶体管，例如具有薄栅极氧化物的晶体管和具有厚栅极氧化物的晶体管以便于承受高电压，例如约几伏。
此外，晶体管的热载流子可靠性(HCI：热载流子注入)高度取决于在整个衬底上相同的薄膜的厚度。劣化将随着薄膜的厚度减小而更差，并且由于高电压而更差。
因此，对于这样的晶体管，总是存在要在HCI可靠性和静电控制之间实现折衷。
实用新型内容
根据一个实施例及其实现方式，目的是例如在相同的SOI衬底、具体地FDSOI衬底上、与具有薄栅极氧化物的晶体管联合形成具有厚栅极氧化物的晶体管的情况下，对于所有晶体管改善这种折衷。
根据一个实施例，提供在相同SOI类型的衬底上形成不同厚度的薄膜。
根据一个方面，提供了一种绝缘体上硅类型的衬底，包括在不同区域中具有不同厚度的半导体膜并且存在于本身位于相同载体衬底的顶部的相同掩埋绝缘层上。
根据一个实施例，衬底可以例如具有完全耗尽的绝缘体上硅类型。
根据另一实施例，该衬底进一步在不同衬底区域之间包括绝缘结构。
根据又一方面，提供了一种集成电路，包括：绝缘体上硅类型的衬底，包括在不同衬底区域中具有不同厚度并且存在于本身位于相同载体衬底的顶部的相同掩埋绝缘层上的半导体膜；具有第一栅极电介质的第一晶体管，所述第一栅极电介质在第一衬底区域中具有第一厚度，在第一衬底区域中所述半导体膜具有第一厚度；以及具有第二栅极电介质的第二晶体管，所述第二栅极电介质在第二衬底区域中具有第二厚度，在第二衬底区域中所述半导体膜具有第二厚度，其中第二栅极电介质的第二厚度比第一栅极电介质的第一厚度厚，并且其中半导体膜的第二厚度比半导体膜的第一厚度厚。
根据一个实施例，该衬底具有完全耗尽的绝缘体上硅类型。
根据又一实施例，该集成电路进一步在第一衬底区域和第二衬底区域之间包括绝缘结构。
附图说明
在考察了非限制性实施例及其实现方式的具体描述和附图之后，本实用新型的其他优点和特征将变得显而易见，在附图中：
图1至图11示意性图示了本实用新型的实施例及其实现方式。
具体实施方式
图1图示了完全耗尽的绝缘体上硅(FDSOI)类型的初始衬底S，该初始衬底S包括在掩埋绝缘层2(BOX)顶部的半导体膜3，该掩埋绝缘层2本身存在于可以例如是半导体阱的载体衬底1上。
应当注意，半导体膜3的初始厚度EI在第一区域Z1和第二区域Z2中是相同的。
在该初始衬底S上，例如由原硅酸四乙酯(TEOS)制成的硬掩模层4首先被完全沉积在第一区域Z1和第二区域Z2中(图2)。
使用利用蚀刻掩模和随后适用于硬掩膜4的湿蚀刻、例如HF蚀刻(基于氢氟酸(HF))的常规光刻法，第二区域Z2中的TEOS硬掩膜4的层可以被向下蚀刻到半导体膜3(图3)。
一般来说，在CMOS制造工艺中，避免对裸硅执行处理操作，并且裸硅由本领域技术人员通常使用术语PADOX来表示的氧化物层保护。
因此，在本实施例中，半导体膜3可以在第二区域Z2中由例如PADOX类型的保护层5来覆盖。在图4中图示的该PADOX层5的该形成可以在烤炉中执行。
该PADOX层5在其形成期间消耗半导体膜3的一部分，这将减少第二区域Z2中的半导体膜3的厚度E2。
然后，如图5中所示，硬掩模层4连同保护层5可以例如通过单个HF蚀刻步骤来消除。
因此，可以在各区域Z1和Z2中形成包括不同厚度(E1>E2)的半导体膜3的SOI类型的衬底S1(图5)。厚度差(E1-E2)可以是约5纳米或更小或更大。
为了改善所有晶体管的热载流子可靠性(HCI)和静电控制之间的折衷，具体地具有厚栅极氧化物的晶体管、包括厚栅极氧化物的至少一个晶体管T1可以有利地在第一区域Z1中形成，其中，位于半导体膜3中的其导电沟道C1更厚。然后，在具有较薄导电沟道C2的第二区域Z2中形成包括较薄栅极电介质OX2的晶体管T2(图6)。
通过示例的方式，具有厚栅极氧化物的晶体管例如是具有约40埃的氧化物厚度的晶体管，而具有薄栅极氧化物的传统晶体管具有大约10至15埃的氧化物厚度。
形成这些晶体管的工艺是常规的，并且是本领域技术人员公知的。
应当注意，在非常示意性的图6中，包括例如浅沟槽(STI：浅沟槽隔离)的绝缘区域隔离第一区域Z1和第二区域Z2，并且故意没有被示出。
图7至图11示意性图示了本实用新型的一种可能变体。
图7图示了FDSOI类型的初始衬底S，其中第一区域Z3和第二区域Z4通过例如STI类型的绝缘区域RIS被隔离。可以再次看到，半导体膜3位于本身存在于载体衬底1顶部的掩埋绝缘层2(BOX)上，该载体衬底可以例如是半导体阱。
这里的半导体膜3通常由例如PADOX类型的保护层6覆盖，并且部分地被该PADOX层6消耗。因此，半导体膜3的厚度因此在整个半导体膜3上被一致地减少。
如图8所示，随后通过常规的光刻法(蚀刻掩模和适当的湿蚀刻)，第二区域Z4中的半导体膜3的顶部的保护层6被消除。
可以在图9中图示的步骤中提供在第二区域Z4中的半导体膜3上的本身常规和已知的硅或硅锗或硅合金类型的外延步骤，以便于在第二区域Z4中形成具有大于第一区域Z3中的厚度E3的厚度E4的半导体膜3。
随后在半导体膜3上执行蚀刻步骤，以移除第一区域Z3中位于具有薄的厚度E3的半导体膜3顶部的层6的其余部分(图10)。
由此获得了SOI类型的衬底S2，其半导体膜3在各区域Z3和Z4中具有不同的厚度E3和E4。
然后，以与已经参考图6描述的类似的方式，例如在第一区域Z3中的薄膜C3上形成包括薄栅极电介质OX3的晶体管T3和在第二区域Z4中的导电沟道C4上形成包括厚栅极电介质OX4的晶体管T4(图11)。
因此，通过两个变体，可以形成集成电路，该集成电路包括绝缘体上硅类型的所述衬底S1或S2、至少第一晶体管T2或T3和至少第二晶体管T1或T4，第一晶体管T2或T3具有在其中半导体膜具有第一厚度的膜的区域Z2或Z3中具有第一厚度的电介质的栅极电介质，第二晶体管T1或T4具有在其中半导体膜具有大于第一厚度的膜的第二厚度的膜的另一区域Z1或Z4中具有比第一厚度的电介质更厚的第二厚度的电介质的栅极电介质。
本实用新型不限于刚被描述的实施例及其实现方式，但其包含在本实用新型范围内的所有变体。
因此，可能能够在同一衬底上形成多于两个厚度的半导体膜3。

Claims (6)

1.一种绝缘体上硅类型的衬底，其特征在于，包括：
半导体膜，在不同衬底区域中具有不同厚度并且存在于本身位于相同载体衬底顶部的相同掩埋绝缘层上。
2.根据权利要求1所述的衬底，其特征在于，所述衬底具有完全耗尽的绝缘体上硅类型。
3.根据权利要求2所述的衬底，其特征在于，进一步在所述不同衬底区域之间包括绝缘结构。
4.一种集成电路，其特征在于，包括：
绝缘体上硅类型的衬底，包括在不同衬底区域中具有不同厚度并且存在于本身位于相同载体衬底的顶部的相同掩埋绝缘层上的半导体膜；
具有第一栅极电介质的第一晶体管，所述第一栅极电介质在第一衬底区域中具有第一厚度，在所述第一衬底区域中所述半导体膜具有第一厚度；以及
具有第二栅极电介质的第二晶体管，所述第二栅极电介质在第二衬底区域中具有第二厚度，在所述第二衬底区域中所述半导体膜具有第二厚度，
其中所述第二栅极电介质的所述第二厚度比所述第一栅极电介质的所述第一厚度厚，并且
其中所述半导体膜的所述第二厚度比所述半导体膜的所述第一厚度厚。
5.根据权利要求4所述的集成电路，其特征在于，所述衬底具有完全耗尽的绝缘体上硅类型。
6.根据权利要求4所述的集成电路，其特征在于，进一步在所述第一衬底区域和所述第二衬底区域之间包括绝缘结构。
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