CN205122563U - Cermet dual in line package diode array board - Google Patents
Cermet dual in line package diode array board Download PDFInfo
- Publication number
- CN205122563U CN205122563U CN201520957290.9U CN201520957290U CN205122563U CN 205122563 U CN205122563 U CN 205122563U CN 201520957290 U CN201520957290 U CN 201520957290U CN 205122563 U CN205122563 U CN 205122563U
- Authority
- CN
- China
- Prior art keywords
- layer
- contact
- conductive layer
- data wire
- lower film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model relates to a cermet dual in line package diode array board, array panel includes the base plate and forms the first conducting layer on the base plate, first grid insulating layer on the first conducting layer, semiconductor layer on the first grid insulating layer, at least the part forms on this semiconductor layer and including the data line and the second conducting layer of drain electrode that separate each other, and this second conducting layer is including blockking the lower part membrane that the metal constitutes and the upper portion membrane of al or al alloy constitution, cover this semiconductor layer's passivation layer, and form on this second conducting layer and with the third conducting layer of second conducting layer contact, wherein, to lie in the lower part epimembranal at an edge of this upper portion membrane at least for the lower part membrane includes the first portion of dew outside the membrane of upper portion, and this first portion of third conducting layer contact lower part membrane, the edge of upper portion membrane crosss the lower part membrane.
Description
Technical field
The utility model belongs to technical field of semiconductors, particularly a kind of cermet dip diode array plate.
Background technology
Usually, integrated circuit comprises the combination being formed in NMOS (η type Metal-oxide-semicondutor) transistor on substrate and PMOS (P type Metal-oxide-semicondutor) transistor.The performance of the performance of integrated circuit and its transistor comprised has direct relation.Therefore, wish that the drive current improving transistor is to strengthen its performance.
U.S. Patent application No.20100038685 Α discloses a kind of transistor, dislocation is formed between the channel region and source/drain region of this transistor, this dislocation produces tension stress, and this tension stress improves the electron mobility in raceway groove, and the drive current of transistor is increased thus.Silicon injection is carried out to the semiconductor substrate defining gate-dielectric and grid, thus forms non-crystalline areas.Anneal to this semiconductor substrate, make non-crystalline areas recrystallization, in recrystallization process, meeting in two on horizontal direction and vertical direction different crystal growth front ends, thus defines dislocation.
DIP encapsulates, and is the abbreviation of dualinline-pinpackage, is also dual in-line package technology, two lambda line encapsulation; Refer to the integrated circuit (IC) chip adopting the encapsulation of dual-in-line form, most middle small scale integrated circuit all adopts this packing forms.DIP encapsulation CPM chip have two row's pins, need be inserted into there is DIP structure chip carrier socket on.Certainly, also can directly be inserted in identical welding hole number and geometry arrangement circuit board on weld.DIP encapsulating structure form has: multi-layer ceramics dual inline type DIP, single-layer ceramic dual inline type DIP, lead frame posture DIP (containing glass ceramics sealing-in formula, plastic encapsulation structural formula, ceramic low-melting-point glass packaged type) etc.Along with the development of DIP encapsulation technology, dual-in-line ceramic package technology is also constantly brought forth new ideas.Such as, patent CN2834017Y discloses a kind of dual-in-line shell being applied to SAW (Surface Acoustic Wave) device.Patent CN203503638M discloses a kind of dual inline type optical coupler black ceramic package casing.Above-mentioned ceramic package is still confined to the structure of single cavity, is difficult to promote its electrical density and effective area thereof further.
Utility model content
The purpose of this utility model is to solve the problem, and proposes a kind of cermet dip diode array plate.
A kind of cermet dip diode array plate, described array board comprises substrate and is formed in the first conductive layer on substrate; First grid insulating barrier on first conductive layer; Semiconductor layer on first grid insulating barrier; Being formed at least partly on this semiconductor layer and comprising the second conductive layer of data wire spaced apart from each other and drain electrode, this second conductive layer comprises lower film that barrier metal forms and the upper membrane that Al or Al alloy is formed; Cover the passivation layer of this semiconductor layer; And to be formed on this second conductive layer and with the 3rd conductive layer of the second conductive layers make contact, wherein, at least an edge of this upper membrane is positioned in lower film, lower film is comprised be exposed at the Part I outside upper membrane, and this Part I of the 3rd conductive layers make contact lower film; The edge of upper membrane traverses lower film; Passivation layer has the contact hole of this Part I exposing lower film at least partly; 3rd conductive layer be positioned on passivation layer at least partially; And this at least one edge of upper membrane not with the overlapping margins of contact hole; Lower film near passivation layer contact contact hole.
Described array board also comprises the data wire be arranged on substrate; Described data wire and first grid epipolar lines intersect, described first grid polar curve comprises gate electrode; Described first grid insulating barrier, to be arranged on gate line and to have the contact hole exposing described data wire; Described passivation layer is arranged on the semiconductor layer; Comprise the insulator layer be arranged between described semiconductor layer and described passivation layer further; Also comprise interlayer insulating film, this interlayer insulating film is arranged between data wire and gate line; 3rd conductive layer comprises the pixel electrode of contact drain electrode; Passivation layer have for the contact between drain electrode and pixel electrode the first contact hole, expose the second contact hole of a part for the first conductive layer and expose the 3rd contact hole of a part of data wire, and the 3rd conductive layer comprises the first contact slave part by the second contact holes contact first conductive layer and the second contact slave part by the 3rd contact holes contact data wire; The Part I of the second conductive layer is uneven.
Described array board also comprises dual-in-line ceramic package, comprise housing and the two row pins being arranged at hull outside, enclosure interior offers four cavitys, bottom in each cavity is provided with metal layer, metallization layer is provided with base, be provided with cover plate above base, described base is connected with cover plate by base sealing ring; Described pin is biserial arrangement, often arranges and all has eight pins; Described pin is zigzag, obliquely bottom pin is provided with insulating strength muscle; NiPdAu alloy layer is coated with outside pin; Described metal layer comprises nickel coating and Gold plated Layer; The thickness of described nickel coating is 9.5 μm, and the thickness of Gold plated Layer is 1 μm; Described housing is made up of alumina ceramic of black color.
Described substrate is composited by carbon, carborundum, silicon nitride, aluminium oxide and silicon, and described substrate is of five storeys from outside to inside altogether, and be silicon layer, silicon nitride layer, silicon carbide layer, carbon-coating and alumina substrate layer respectively, the thickness of every layer is 0.5-3mm.
Accompanying drawing explanation
Fig. 1 is the cross sectional representation of a kind of cermet dip diode array plate according to an embodiment of the present utility model;
Fig. 2 is the structural representation of substrate.
Wherein, 1 is substrate; 2 is first conductive layers; 3 is second conductive layers; 4 is semiconductor layers; 5 is ohmic contact layers; 6 is the 3rd conductive layers; 7 is gate insulators; 11 are silicon layers, 12 are silicon nitride layers, 13 are silicon carbide layers, 14 are carbon-coatings, 15 is alumina substrate layers.
Embodiment
A kind of cermet dip diode array plate, described array board comprises substrate and is formed in the first conductive layer on substrate; First grid insulating barrier on first conductive layer; Semiconductor layer on first grid insulating barrier; Being formed at least partly on this semiconductor layer and comprising the second conductive layer of data wire spaced apart from each other and drain electrode, this second conductive layer comprises lower film that barrier metal forms and the upper membrane that Al or Al alloy is formed; Cover the passivation layer of this semiconductor layer; And to be formed on this second conductive layer and with the 3rd conductive layer of the second conductive layers make contact, wherein, at least an edge of this upper membrane is positioned in lower film, lower film is comprised be exposed at the Part I outside upper membrane, and this Part I of the 3rd conductive layers make contact lower film; The edge of upper membrane traverses lower film; Passivation layer has the contact hole of this Part I exposing lower film at least partly; 3rd conductive layer be positioned on passivation layer at least partially; And this at least one edge of upper membrane not with the overlapping margins of contact hole; Lower film near passivation layer contact contact hole.
Described array board also comprises the data wire be arranged on substrate; Described data wire and first grid epipolar lines intersect, described first grid polar curve comprises gate electrode; Described first grid insulating barrier, to be arranged on gate line and to have the contact hole exposing described data wire; Described passivation layer is arranged on the semiconductor layer; Comprise the insulator layer be arranged between described semiconductor layer and described passivation layer further; Also comprise interlayer insulating film, this interlayer insulating film is arranged between data wire and gate line; 3rd conductive layer comprises the pixel electrode of contact drain electrode; Passivation layer have for the contact between drain electrode and pixel electrode the first contact hole, expose the second contact hole of a part for the first conductive layer and expose the 3rd contact hole of a part of data wire, and the 3rd conductive layer comprises the first contact slave part by the second contact holes contact first conductive layer and the second contact slave part by the 3rd contact holes contact data wire; The Part I of the second conductive layer is uneven.
Described array board also comprises dual-in-line ceramic package, comprise housing and the two row pins being arranged at hull outside, enclosure interior offers four cavitys, bottom in each cavity is provided with metal layer, metallization layer is provided with base, be provided with cover plate above base, described base is connected with cover plate by base sealing ring; Described pin is biserial arrangement, often arranges and all has eight pins; Described pin is zigzag, obliquely bottom pin is provided with insulating strength muscle; NiPdAu alloy layer is coated with outside pin; Described metal layer comprises nickel coating and Gold plated Layer; The thickness of described nickel coating is 9.5 μm, and the thickness of Gold plated Layer is 1 μm; Described housing is made up of alumina ceramic of black color.
Described substrate is composited by carbon, carborundum, silicon nitride, aluminium oxide and silicon, and described substrate is of five storeys from outside to inside altogether, and be silicon layer, silicon nitride layer, silicon carbide layer, carbon-coating and alumina substrate layer respectively, the thickness of every layer is 0.5-3mm.
Last it is noted that obviously, above-described embodiment is only for the utility model example is clearly described, and the restriction not to execution mode.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here exhaustive without the need to also giving all execution modes.And thus the apparent change of extending out or variation be still among protection range of the present utility model.
Claims (4)
1. a cermet dip diode array plate, is characterized in that: described array board comprises substrate and is formed in the first conductive layer on substrate; First grid insulating barrier on first conductive layer; Semiconductor layer on first grid insulating barrier; Being formed at least partly on this semiconductor layer and comprising the second conductive layer of data wire spaced apart from each other and drain electrode, this second conductive layer comprises lower film that barrier metal forms and the upper membrane that Al or Al alloy is formed; Cover the passivation layer of this semiconductor layer; And to be formed on this second conductive layer and with the 3rd conductive layer of the second conductive layers make contact, wherein, at least an edge of this upper membrane is positioned in lower film, lower film is comprised be exposed at the Part I outside upper membrane, and this Part I of the 3rd conductive layers make contact lower film; The edge of upper membrane traverses lower film; Passivation layer has the contact hole of this Part I exposing lower film at least partly; 3rd conductive layer be positioned on passivation layer at least partially; And this at least one edge of upper membrane not with the overlapping margins of contact hole; Lower film near passivation layer contact contact hole.
2. diode array plate according to claim 1, is characterized in that: described array board also comprises the data wire be arranged on substrate; Described data wire and first grid epipolar lines intersect, described first grid polar curve comprises gate electrode; Described first grid insulating barrier, to be arranged on gate line and to have the contact hole exposing described data wire; Described passivation layer is arranged on the semiconductor layer; Comprise the insulator layer be arranged between described semiconductor layer and described passivation layer further; Also comprise interlayer insulating film, this interlayer insulating film is arranged between data wire and gate line; 3rd conductive layer comprises the pixel electrode of contact drain electrode; Passivation layer have for the contact between drain electrode and pixel electrode the first contact hole, expose the second contact hole of a part for the first conductive layer and expose the 3rd contact hole of a part of data wire, and the 3rd conductive layer comprises the first contact slave part by the second contact holes contact first conductive layer and the second contact slave part by the 3rd contact holes contact data wire; The Part I of the second conductive layer is uneven.
3. array board according to claim 1, it is characterized in that: described array board also comprises dual-in-line ceramic package, comprise housing and the two row pins being arranged at hull outside, enclosure interior offers four cavitys, bottom in each cavity is provided with metal layer, metallization layer is provided with base, is provided with cover plate above base, and described base is connected with cover plate by base sealing ring; Described pin is biserial arrangement, often arranges and all has eight pins; Described pin is zigzag, obliquely bottom pin is provided with insulating strength muscle; NiPdAu alloy layer is coated with outside pin; Described metal layer comprises nickel coating and Gold plated Layer; The thickness of described nickel coating is 9.5 μm, and the thickness of Gold plated Layer is 1 μm; Described housing is made up of alumina ceramic of black color.
4. array board according to claim 1, it is characterized in that: described substrate is composited by carbon, carborundum, silicon nitride, aluminium oxide and silicon, described substrate is of five storeys from outside to inside altogether, be silicon layer, silicon nitride layer, silicon carbide layer, carbon-coating and alumina substrate layer respectively, the thickness of every layer is 0.5-3mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520957290.9U CN205122563U (en) | 2015-11-26 | 2015-11-26 | Cermet dual in line package diode array board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520957290.9U CN205122563U (en) | 2015-11-26 | 2015-11-26 | Cermet dual in line package diode array board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205122563U true CN205122563U (en) | 2016-03-30 |
Family
ID=55578144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520957290.9U Active CN205122563U (en) | 2015-11-26 | 2015-11-26 | Cermet dual in line package diode array board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205122563U (en) |
-
2015
- 2015-11-26 CN CN201520957290.9U patent/CN205122563U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102339817B (en) | Semiconductor package and mobile device using the same | |
| KR101546572B1 (en) | Semiconductor device package and method for manufacturing the same | |
| CN105529317B (en) | Embedded packaging system | |
| TW201533860A (en) | Wiring board and semiconductor device using the same | |
| TW200509331A (en) | Semiconductor chip package and method for making the same | |
| JP2006319204A (en) | Semiconductor device and manufacturing method therefor | |
| JP2008130701A (en) | Wiring substrate, semiconductor device using the substrate, and method of manufacturing the semiconductor device | |
| TW201340261A (en) | Semiconductor device and manufacturing method thereof | |
| TW201523829A (en) | Semiconductor device and method of manufacturing semiconductor device | |
| JPH11233683A (en) | Resin-encapsulated type semiconductor device, circuit member used for the device, and manufacture thereof | |
| JP2003204014A (en) | Semiconductor wafer, method of manufacturing the same having bumps, semiconductor chip having bumps, method of manufacturing the same, semiconductor device, circuit board and electronic equipment | |
| TW200735313A (en) | Semiconductor device and manufacturing method thereof | |
| JP2008181702A (en) | Battery pack, battery protection module, and manufacturing method of base board for battery protection module | |
| CN205122563U (en) | Cermet dual in line package diode array board | |
| CN210110300U (en) | Pixel driving circuit, array substrate and display device | |
| US9570439B2 (en) | Semiconductor device and semiconductor package | |
| US20200083215A1 (en) | Semiconductor device | |
| CN102456655A (en) | Semiconductor module | |
| US20210111109A1 (en) | Flat no-lead package with surface mounted structure | |
| CN205122585U (en) | Cermet table pastes encapsulation transistor array board | |
| CN109817697B (en) | Semiconductor device and method for manufacturing the same | |
| US3828229A (en) | Leadless semiconductor device for high power use | |
| JP2004087882A (en) | Semiconductor device | |
| JP2001094044A (en) | Semiconductor device, its manufacturing method circuit substrate, and electronic equipment | |
| TWI827014B (en) | Package structure and circuit board assembly with embedded power chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |