TWI827014B - Package structure and circuit board assembly with embedded power chip - Google Patents
Package structure and circuit board assembly with embedded power chip Download PDFInfo
- Publication number
- TWI827014B TWI827014B TW111115243A TW111115243A TWI827014B TW I827014 B TWI827014 B TW I827014B TW 111115243 A TW111115243 A TW 111115243A TW 111115243 A TW111115243 A TW 111115243A TW I827014 B TWI827014 B TW I827014B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- circuit layer
- lead frame
- power chip
- base material
- Prior art date
Links
- 238000003466 welding Methods 0.000 claims abstract description 22
- 238000005476 soldering Methods 0.000 claims abstract description 21
- 238000004806 packaging method and process Methods 0.000 claims description 73
- 239000000463 material Substances 0.000 claims description 55
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 51
- 229910052802 copper Inorganic materials 0.000 claims description 51
- 239000010949 copper Substances 0.000 claims description 51
- 230000017525 heat dissipation Effects 0.000 claims description 12
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 5
- 238000000465 moulding Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 229920000106 Liquid crystal polymer Polymers 0.000 description 3
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 3
- 239000004743 Polypropylene Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000001746 injection moulding Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- -1 Polypropylene Polymers 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920001155 polypropylene Polymers 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 239000004677 Nylon Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229920001778 nylon Polymers 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
本申請涉及一種封裝結構及內埋功率晶片的電路板組件。 The present application relates to a packaging structure and a circuit board assembly with a built-in power chip.
功率晶片組裝於電路板的方式通常包括：將功率晶片置於導線架(Lead Frame，又稱引線框架)上，以打線方式(例如，打金線或者打鋁線)連接所述功率晶片和導線架，再經成型及注模(Molding)完成封裝，得到功率封裝組件。然後，將封裝好的功率封裝元件焊接於另一電路板表面以完成組裝。但這種以打線方式所製得的功率封裝元件通常會產生較高的寄生電感，在高速開關過程中產生較大的功率損耗。 The method of assembling the power chip on the circuit board usually includes: placing the power chip on a lead frame (also called a lead frame), and connecting the power chip and the wires by wire bonding (for example, gold wire or aluminum wire) The frame is then packaged through molding and injection molding (Molding) to obtain a power package component. Then, the packaged power package components are soldered to the surface of another circuit board to complete the assembly. However, such power packaging components produced by wire bonding usually produce high parasitic inductance, resulting in large power loss during high-speed switching.
有鑑於此，本申請提供一種能夠能解決上述問題的封裝結構。 In view of this, the present application provides a packaging structure that can solve the above problems.
另外，還有必要提供一種包括上述封裝結構的內埋功率晶片的電路板組件。 In addition, it is also necessary to provide a circuit board assembly including a built-in power chip of the above-mentioned packaging structure.
另外，還有必要提供另一種包括上述封裝結構的內埋功率晶片的電路板組件。 In addition, there is a need to provide another circuit board assembly including an embedded power chip in the above package structure.
本申請提供一種封裝結構，包括功率晶片、柵極引出端、第一導線架、第二導線架、導線、第一焊接層、第二焊接層和封裝體，所述功率晶片具有柵極、源極和漏極；所述柵極引出端通過導線連接於所述功率晶片的柵極，所述第一導線架通過第一焊接層連接於所述功率晶片的源極，所述第二導線架通過第二焊接層連接於所述功率晶片的漏極，所述封裝體包覆所述功率晶片、柵極引出端、第一導線架、第二導線架、所述導線、所述第一焊接層和所述第二焊接層。 The present application provides a packaging structure, including a power chip, a gate terminal, a first lead frame, a second lead frame, wires, a first welding layer, a second welding layer and a package body. The power chip has a gate, a source electrode and drain; the gate lead-out terminal is connected to the gate of the power chip through a wire, the first lead frame is connected to the source of the power chip through a first welding layer, and the second lead frame Connected to the drain of the power chip through a second welding layer, the package covers the power chip, the gate terminal, the first lead frame, the second lead frame, the wire, and the first welding layer and the second welding layer.
在一些實施方式中，所述封裝結構還包括源極引出端及第三焊接層，所述源極引出端通過第三焊接層連接於所述第一導線架；所述封裝結構包括第一表面和與所述第一表面相對設置的第二表面，所述柵極引出端、源極引出端和第二導線架暴露於所述第二表面。 In some embodiments, the packaging structure further includes a source terminal and a third soldering layer, and the source terminal is connected to the first lead frame through the third soldering layer; the packaging structure includes a first surface and a second surface disposed opposite to the first surface, and the gate lead-out terminal, the source lead-out terminal and the second lead frame are exposed to the second surface.
在一些實施方式中，所述第一導線架暴露於所述第一表面。 In some embodiments, the first leadframe is exposed to the first surface.
本申請還提供一種內埋功率晶片的電路板組件，包括電路板和所述封裝結構，所述電路板包括第一基材層、第一內側線路層和第一外側線路層，所述第一內側線路層和第一外側線路層設置於所述第一基材層的相對兩側；所述第一基材層貫穿設有開孔，所述封裝結構設於所述開孔。 This application also provides a circuit board assembly with a built-in power chip, including a circuit board and the packaging structure. The circuit board includes a first base material layer, a first inner circuit layer and a first outer circuit layer. The first The inner circuit layer and the first outer circuit layer are provided on opposite sides of the first base material layer; the first base material layer is provided with openings, and the packaging structure is provided in the openings.
在一些實施方式中，部分所述第一內側線路層連接於所述第一導線架；部分所述第一外側線路層連接於所述柵極引出端、所述源極引出端和所述第二導線架。 In some embodiments, part of the first inner circuit layer is connected to the first lead frame; part of the first outer circuit layer is connected to the gate terminal, the source terminal and the third Two lead frames.
在一些實施方式中，所述電路板還包括多個第二基材層、多個第二內側線路層和第二外側線路層，所述第二外側線路層和所述第一內側線路層間隔設置，多個所述第二基材層和多個所述第二內側線路層交替疊設於所述第二外側線路層和所述第一內側線路層之間。 In some embodiments, the circuit board further includes a plurality of second base material layers, a plurality of second inner circuit layers and a second outer circuit layer, and the second outer circuit layer and the first inner circuit layer are spaced apart It is provided that a plurality of second base material layers and a plurality of second inner circuit layers are alternately stacked between the second outer circuit layer and the first inner circuit layer.
在一些實施方式中，所述電路板組件還包括第一導電柱和第二導電柱，所述第一導電柱電性連接所述第一內側線路層、所述第二內側線路層、所述第一外側線路層及所述第二外側線路層；所述第二導電柱電性連接所述第二內側線路層、所述柵極引出端、所述第一外側線路層及所述第二外側線路層。 In some embodiments, the circuit board assembly further includes a first conductive pillar and a second conductive pillar, the first conductive pillar is electrically connected to the first inner circuit layer, the second inner circuit layer, the The first outer circuit layer and the second outer circuit layer; the second conductive pillar is electrically connected to the second inner circuit layer, the gate terminal, the first outer circuit layer and the second Outside line layer.
本申請還提供另一種內埋功率晶片的電路板組件，包括電路板和所述的封裝結構，所述電路板包括第一基材層、第二基材層、第一內側線路層、第一外側線路層及第二外側線路層，所述第一內側線路層設置於所述第一基材層和所述第二基材層之間，所述第一外側線路層設置於第一基材層背離所述第一內側線路層的一側，所述第二外側線路層設置於所述第二基材層背離所述第一內側線路層的一側，所述第一基材層貫穿設有開孔，所述封裝結構設於所述開孔；部分所述第一內側線路層和第一外側線路層連接於所述封裝結構的相對兩側；相鄰二所述封裝結構中的兩個所述第二導線架朝向相背，且其中一封裝結構的第一導線架通過第一外側線路層電性連接於另一所述封裝結構的第二導線架。在一些實施方式中，所述電路板組件還包括第一導電柱和第二導電柱，所述第一導電柱貫穿所述第二基材層，電性連接於所述第一內側線路層和第二外側線路層；所述第一導電柱貫穿所述封裝結構，電性連接於所述第一內側線路層、所述柵極引出端和所述第一外側線路層。 This application also provides another circuit board assembly with a built-in power chip, including a circuit board and the packaging structure. The circuit board includes a first base material layer, a second base material layer, a first inner circuit layer, a first Outside circuit layer and second outside circuit layer, the first inside circuit layer is provided between the first base material layer and the second base material layer, the first outside circuit layer is provided on the first base material The side of the layer facing away from the first inner circuit layer, the second outer circuit layer is provided on the side of the second base material layer facing away from the first inner circuit layer, and the first base material layer passes through There is an opening, and the packaging structure is provided in the opening; part of the first inner circuit layer and the first outer circuit layer are connected to opposite sides of the packaging structure; two of the two adjacent packaging structures The two second lead frames face opposite sides, and the first lead frame of one of the package structures is electrically connected to the second lead frame of the other package structure through the first outer circuit layer. In some embodiments, the circuit board assembly further includes a first conductive pillar and a second conductive pillar. The first conductive pillar penetrates the second base material layer and is electrically connected to the first inner circuit layer and the second conductive pillar. The second outer circuit layer; the first conductive pillar penetrates the packaging structure and is electrically connected to the first inner circuit layer, the gate terminal and the first outer circuit layer.
在一些實施方式中，所述第一外側線路層背離所述封裝結構的一側設置有散熱塊；所述散熱塊為銅層、銅塊或鰭片。 In some embodiments, a heat dissipation block is provided on a side of the first outer circuit layer away from the packaging structure; the heat dissipation block is a copper layer, a copper block or a fin.
本申請提供的封裝結構通過將功率晶片的柵極通過導線連接於柵極引出端，可有效解決柵極接點尺寸小的問題，且為所述功率晶片的源極留出 空間，以實現所述源極與第一導線架的大面積焊接。該封裝結構可有效降低寄生電感，並降低功率損耗。 The packaging structure provided by this application can effectively solve the problem of small gate contact size by connecting the gate of the power chip to the gate terminal through a wire, and leaves space for the source of the power chip. space to achieve large-area welding of the source electrode and the first lead frame. This packaging structure can effectively reduce parasitic inductance and reduce power loss.
另外，本申請還提供一種包括上述封裝結構的內埋功率晶片的電路板組件，可通過控制封裝結構中柵極引出端的尺寸，使得所述第一導電柱的位置準確度增加，降低多層線路板壓合於所述基板時封裝位置漂移所造成的不良率，從而提高整個內埋功率晶片的電路板的可靠度。並且，採用第一導電柱貫通連接所述多層線路板和所述封裝結構的柵極引出端，可進一步降低因打線而造成的寄生電感升高問題，降低功率損耗，還可以增加功率密度，提升開關頻率，同時還能起到散熱作用。 In addition, the present application also provides a circuit board assembly including a power chip embedded in the above-mentioned packaging structure. By controlling the size of the gate terminal in the packaging structure, the position accuracy of the first conductive pillar can be increased and the multi-layer circuit board can be reduced in size. The defective rate is caused by the drift of the package position when being pressed onto the substrate, thereby improving the reliability of the entire circuit board with embedded power chip. In addition, the first conductive pillar is used to connect the multi-layer circuit board and the gate terminal of the packaging structure, which can further reduce the problem of increased parasitic inductance caused by wiring, reduce power loss, and can also increase power density and improve switching frequency, and also plays a role in heat dissipation.
另外，本申請還提供另一種內埋功率晶片的電路板組件，同時內埋兩個封裝結構，通過將所述兩個封裝結構相背設置並連接，即其中一封裝結構的源極連接於另一封裝結構的漏極，可一步提高整個內埋功率晶片的電路板組件的功率密度。 In addition, the present application also provides another circuit board assembly with a built-in power chip and two package structures embedded at the same time. The two package structures are arranged and connected oppositely, that is, the source of one package structure is connected to the other. The drain of a package structure can further increase the power density of the entire circuit board assembly with embedded power chip.
100、100’:封裝結構 100, 100’: package structure
110:第一表面 110: First surface
120:第二表面 120: Second surface
10:功率晶片 10:Power chip
G:柵極 G:Gate
S:源極 S: source
D:漏極 D: Drain
11:柵極引出端 11: Gate terminal
12:導線 12:Wire
13:第一導線架 13:First lead frame
14:第一焊接層 14: First welding layer
15:第二焊接層 15: Second welding layer
16:第二導線架、漏極引出端 16: Second lead frame, drain terminal
17:第三焊接層 17: The third welding layer
18:源極引出端 18: Source terminal
19:封裝體 19:Package
200、300:內埋功率晶片的電路板組件 200, 300: Circuit board components with embedded power chips
200a、300a:電路板 200a, 300a: circuit board
20:覆銅基板 20:Copper clad substrate
201:第一基材層 201: First base material layer
202:第一銅層 202: First copper layer
203:第二銅層 203: Second copper layer
21:開孔 21:Opening
221:第三銅層 221: The third copper layer
221a:第一內側線路層 221a: First inner circuit layer
222:第四銅層 222:The fourth copper layer
222a:第一外側線路層 222a: First outer line layer
23:封裝中間體 23: Encapsulation intermediate
24:多層線路板 24:Multilayer circuit board
241:第五銅層 241: The fifth copper layer
241a:第二外側線路層 241a: Second outside line layer
242:第二內側線路層 242: Second inside line layer
243:第二基材層 243: Second base material layer
24a:第一通孔 24a: First through hole
24b:第二通孔 24b: Second through hole
25a:第一導電柱 25a: First conductive pillar
25b:第二導電柱 25b: Second conductive pillar
26:絕緣體 26:Insulator
27:散熱塊 27:Heating block
圖1是本申請一實施例提供的封裝結構的截面示意圖。 Figure 1 is a schematic cross-sectional view of a packaging structure provided by an embodiment of the present application.
圖2是本申請一實施例提供的覆銅基板的截面示意圖。 FIG. 2 is a schematic cross-sectional view of a copper-clad substrate provided by an embodiment of the present application.
圖3是圖2所示的覆銅基板設置開孔後的截面示意圖。 FIG. 3 is a schematic cross-sectional view of the copper-clad substrate shown in FIG. 2 after openings are provided.
圖4是圖3所示的開孔內設置圖1所示的封裝結構的截面示意圖。 FIG. 4 is a schematic cross-sectional view of the packaging structure shown in FIG. 1 disposed in the opening shown in FIG. 3 .
圖5是圖4所示的封裝結構上設置第三銅層及第四銅層後的截面示意圖。 FIG. 5 is a schematic cross-sectional view of the package structure shown in FIG. 4 after a third copper layer and a fourth copper layer are provided.
圖6是本申請一實施例提供的封裝中間體的截面示意圖。 Figure 6 is a schematic cross-sectional view of a packaging intermediate provided by an embodiment of the present application.
圖7是圖6所示的封裝中間體上設置多層線路板後的截面示意圖。 FIG. 7 is a schematic cross-sectional view of the packaging intermediate shown in FIG. 6 after a multi-layer circuit board is installed.
圖8是圖7所示的封裝中間體和多層線路板中設置導電柱的截面示意圖。 FIG. 8 is a schematic cross-sectional view of the conductive pillars provided in the packaging intermediate body and the multilayer circuit board shown in FIG. 7 .
圖9是本申請一實施例提供的內埋功率晶片的電路板組件的截面示意圖。 FIG. 9 is a schematic cross-sectional view of a circuit board assembly with a built-in power chip provided by an embodiment of the present application.
圖10是本申請另一實施例提供的內埋功率晶片的電路板組件的截面示意圖。 FIG. 10 is a schematic cross-sectional view of a circuit board assembly with a built-in power chip provided by another embodiment of the present application.
下面將結合本申請實施例中的附圖，對本申請實施例中的技術方案進行清楚、完整地描述，顯然，所描述的實施例僅是本申請一部分實施例，而不是全部的實施例。基於本申請中的實施例，本領域普通技術人員在沒有做出創造性勞動前提下所獲得的所有其他實施例，都屬於本申請保護的範圍。 The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.
除非另有定義，本文所使用的所有的技術和科學術語與屬於本申請的技術領域的技術人員通常理解的含義相同。本文中在本申請的說明書中所使用的術語只是為了描述具體的實施例的目的，不是旨在於限制本申請。 Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing specific embodiments only and is not intended to limit the application.
下面結合附圖，對本申請的一些實施方式作詳細說明。在不衝突的情況下，下述的實施例及實施例中的特徵可以相互組合。 Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The following embodiments and features in the embodiments may be combined with each other without conflict.
請參閱圖1，本申請一實施例提供一種封裝結構100，所述封裝結構100可以是一種功率半導體器件，用於進行功率處理，包括變頻、變壓、變流等。所述封裝結構100包括功率晶片10、柵極引出端11、導線12、第一導線架13、第一焊接層14、第二焊接層15、第二導線架16、第三焊接層17、源極引出端18和封裝體19。所述功率晶片10具有柵極G、源極S及漏極D，所述柵極引出端11通過所述導線12連接於所述功率晶片10的柵極G。所述第一導線架13通過所述第一焊接層14連接於所述功率晶片10的源極S。所述源極引出端18通過所述第三焊接層17連接於所述第一導線架13。所述第二導線架16通過所述第二焊接層15連接於所述功率晶片10的漏極D。所述封裝體19包覆所述功率晶片10、柵極引出端11、第一導線架13、源極引出端18和第二導線架16。所述柵極引出端11、源極
引出端18和第二導線架16(即，漏極引出端)暴露於所述封裝結構100的同一表面。
Referring to Figure 1, an embodiment of the present application provides a
本實施例中，所述封裝結構100包括第一表面110和與所述第一表面110相對設置的第二表面120。所述第一導線架13的一端暴露於所述第一表面110，另一端連接於所述源極引出端18。所述柵極引出端11、源極引出端18和第二導線架16暴露於所述第二表面120。
In this embodiment, the
所述功率晶片10可以為絕緣柵雙極型電晶體(Insulated Gate Bipolar Transistor,IGBT)、碳化矽(SiC)、氮化鎵(GaN)等功率晶片。所述導線12可以為金線或鋁線。
The
本申請中提供的封裝結構100，將功率晶片10的源極S通過焊接連接於所述第一導線架13，以及將功率晶片10的漏極D通過焊接連接於所述第二導線架16，有利於實現源極S與第一導線架13之間、所述漏極D與所述第二導線架16之間的大面積焊接，從而可以有效減少封裝結構100的寄生電感，降低所述功率晶片10在高速開關過程產生的功率損耗。同時，利用導線12連接柵極G與柵極引出端11，從而方便連接到面積較小的柵極G，並且為源極S與第一導線架13之間的連接留出較大的連接空間。
In the
請參閱圖2~圖8，本申請一實施例提供一種內埋功率晶片的電路板組件200的製備方法，其包括如下步驟：
Referring to Figures 2 to 8, one embodiment of the present application provides a method for preparing a
步驟S1：請參閱圖2，提供一覆銅基板20，所述覆銅基板20包括第一基材層201、第一銅層202和第二銅層203。所述第一銅層202和第二銅層203設置於所述第一基材層201的相對兩側面。
Step S1: Please refer to FIG. 2 to provide a copper-clad
步驟S2：請參閱圖3和圖4，於所述覆銅基板20上開設一貫穿所述第一基材層201、第一銅層202和第二銅層203的開孔21，將所述封裝結構100設置於所述開孔21。所述封裝結構100包括所述第一導線架13所在的第一表面110，以及所述柵極引出端11、源極引出端18和所述第二導線架16所在的第二表面120。所述第一表面110與所述覆銅基板20的第一銅層202背離所述
第一基材層201的一側面平齊，所述第二表面120與所述第二銅層203背離所述第一基材層201的一側面平齊。
Step S2: Referring to Figures 3 and 4, an
在設置所述封裝結構100前，還包括對其進行電性量測，確保埋入的功率晶片10以及整體封裝結構100的品質。
Before setting up the
步驟S3：請參閱圖5，於所述第一銅層202和所述封裝結構100的第一表面110上設置第三銅層221。於所述第二銅層203和所述封裝結構100的第二表面120上設置第四銅層222。
Step S3: Referring to FIG. 5 , a third copper layer 221 is provided on the
在設置第三銅層221和第四銅層222之前還包括機械刷磨所述封裝結構100的第一表面110和第二表面120，使得所述第一導線架13、所述柵極引出端11、源極引出端18和所述第二導線架16的表面完全露出，從而便於後續引出線路。本實施例中，設置所述第三銅層221和第四銅層222的方式可以為化銅或電鍍銅中的任意一種。
Before disposing the third copper layer 221 and the
步驟S4：請參閱圖6，圖形化所述第一銅層202和第三銅層221以形成第一內側線路層221a，獲得封裝中間體23。其中，部分所述第一內側線路層221a連接所述第一導線架13。
Step S4: Referring to FIG. 6 , the
具體地，可通過覆膜、曝光顯影以及蝕刻的方式圖形化所述第一銅層202和第三銅層221以形成第一內側線路層221a。
Specifically, the
步驟S5：請參閱圖7，於所述第一內側線路層221a所在的一側通過壓合設置多層線路板24。所述多層線路板24包括第五銅層241、多個第二內側線路層242及多個第二基材層243。所述第五銅層241背離所述封裝結構100設置，所述第二內側線路層242間隔設置於所述第五銅層241和所述第一內側線路層221a之間。所述第二基材層243設置於每相鄰兩個所述第二內側線路層242之間，以及設置於相鄰的所述第二內側線路層242和所述第一內側線路層221a之間，以及設置於相鄰的所述第五銅層241和所述第二內側線路層242之間。
Step S5: Referring to FIG. 7, a
步驟S6：請參閱圖8，貫穿所述多層線路板24和所述封裝中間體23以形成第一通孔24a及第二通孔24b。所述第一通孔24a貫穿連接所述多層線
路板24、所述第一內側線路層221a、所述第一基材層201及所述第二銅層203。所述第二通孔24b貫穿連接所述多層線路板24、所述第一內側線路層221a、所述封裝體19及所述第二銅層203，且所述第二通孔24b避開所述功率晶片10設置。
Step S6: Referring to FIG. 8 , a first through
於所述第一通孔24a內電鍍以形成中空的第一導電柱25a，以及於所述第二通孔24b內電鍍以形成中空的第二導電柱25b。所述第一導電柱25a電性連接所述第五銅層241、所述第一內側線路層221a、多個所述第二內側線路層242及所述第二銅層203。所述第二導電柱25b電性連接所述第二銅層203、所述柵極引出端11、多個所述第二內側線路層242及所述第五銅層241。
Electroplating is performed in the first through
步驟S6還包括：分別於所述中空的所述第一導電柱25a和中空的第二導電柱25b內填入絕緣體26，所述絕緣體26用於排出中空的第一導電柱25a及中空的第二導電柱25b內的空氣，減少爆板風險。
Step S6 also includes: filling the hollow first
步驟S7：請參閱圖9，圖形化所述第二銅層203及所述第四銅層222以形成第一外側線路層222a，以及圖形化所述第五銅層241以形成第二外側線路層241a，即得所述內埋功率晶片的電路板組件200。
Step S7: Refer to FIG. 9 , pattern the
請參閱圖9，本申請一實施例還提供一種內埋功率晶片的電路板組件200，包括所述封裝結構100及電路板200a。
Referring to FIG. 9 , an embodiment of the present application further provides a
所述電路板200a包括第一基材層201、多個第二基材層243、第一內側線路層221a、多個第二內側線路層242、第一外側線路層222a及第二外側線路層241a。所述第一內側線路層221a設置於所述第一基材層201和所述第二基材層243之間，所述第一外側線路層222a設置於第一基材層201背離所述第一內側線路層221a的一側，所述第二外側線路層241a設置於所述第二基材層243背離所述第一內側線路層221a的一側。多個所述第二內側線路層242間隔設置於所述第二外側線路層241a和所述第一內側線路層221a之間。所述第二基材層243設置於每相鄰兩個所述第二內側線路層242之間，以及設置於相鄰的所述第二內側線路層242和所述第一內側線路層221a之間，以及設置於相鄰的所
述第二外側線路層241a和所述第二內側線路層242之間。
The
在其它實施方式中，所述封裝體19也可採用注塑工藝或模壓工藝形成。其中，注塑工藝可以選擇尼龍、LCP(Liquid Crystal Polymer，液晶高分子聚合物)、PP(Polypropylene，聚丙烯)等，模壓工藝可以採用環氧樹脂。
In other embodiments, the
所述第一基材層201貫穿設有開孔21，所述封裝結構100設於所述開孔21。
The first
所述封裝結構100包括功率晶片10、柵極引出端11、導線12、第一導線架13、第二導線架16、源極引出端18和封裝體19。所述柵極引出端11通過所述導線12連接於所述功率晶片10的柵極G。所述第一導線架13通過第一焊接層14連接於所述功率晶片10的源極S。所述第二導線架16通過第二焊接層15連接於所述功率晶片10的漏極D。所述源極引出端18通過第三焊接層17連接於所述第一導線架13。所述封裝體19包覆所述功率晶片10、柵極引出端11、第一導線架13、源極引出端18和第二導線架16。所述柵極引出端11、源極引出端18和第二導線架16(即，漏極引出端)暴露於所述封裝結構100的同一表面。
The
部分所述第一內側線路層221a連接所述第一導線架13，部分所述第一外側線路層222a連接所述柵極引出端11、所述源極引出端18和所述第二導線架16。
Part of the first
在本實施例中，所述內埋功率晶片的電路板組件200還包括第一導電柱25a和第二導電柱25b。所述第一導電柱25a電性連接所述第一內側線路層221a、所述第二內側線路層242、所述第一外側線路層222a及所述第二外側線路層241a。所述第二導電柱25b電性連接所述第二內側線路層242、所述柵極引出端11、所述第一外側線路層222a及所述第二外側線路層241a，從而實現所述電路板200a和所述功率晶片10的電性連接。
In this embodiment, the
本實施例中，所述第一導電柱25a的數量為4個。所述第一導電柱25a和多個所述第二導電柱25b在導通所述內埋功率晶片的電路板組件200和外
部線路的同時，還能起到散熱作用。
In this embodiment, the number of the first
本申請中可通過控制封裝結構100中柵極引出端11的尺寸，使得所述第二導電柱25b的位置準確度增加，降低後續壓合時封裝位置漂移所造成的不良率，從而提高整個內埋功率晶片的電路板組件200的可靠度。另外，採用第二導電柱25b貫通連接所述電路板200a和所述封裝結構100的柵極引出端11，可進一步降低因打線而造成的寄生電感升高問題，降低功率損耗，還可以增加功率密度，提升開關頻率，同時還能起到散熱作用。
In this application, the size of the gate lead-out 11 in the
請參閱圖10，本申請另一實施例提供一種內埋功率晶片的電路板組件300，包括電路板300a、封裝結構100和封裝結構100’，所述封裝結構100和封裝結構100’一正一反相背設置於所述電路板300a中。
Referring to Figure 10, another embodiment of the present application provides a
所述電路板300a包括第一基材層201、第二基材層243、第一內側線路層221a、多個第一導電柱25a、第一外側線路層222a及第二外側線路層241a。所述第一內側線路層221a設置於所述第一基材層201和所述第二基材層243之間，所述第一外側線路層222a設置於第一基材層201背離所述第一內側線路層221a的一側，所述第二外側線路層241a設置於所述第二基材層243背離所述第一內側線路層221a的一側。多個所述第一導電柱25a貫穿所述第二基材層243，且電性連接所述第二外側線路層241a和所述第一內側線路層221a。所述第一基材層201貫穿設有開孔21，所述封裝結構100和所述封裝結構100’相背設於所述開孔21。
The
所述封裝結構100包括功率晶片10、柵極引出端11、導線12、第一導線架13、第二導線架16和封裝體19。所述柵極引出端11通過所述導線12連接於所述功率晶片10的柵極G。所述第一導線架13通過第一焊接層14連接於所述功率晶片10的源極S。所述第二導線架16通過第二焊接層15連接於所述功率晶片10的漏極D。所述封裝體19包覆所述功率晶片10、柵極引出端11、第一導線架13和第二導線架16。所述封裝結構100’與所述封裝結構100的結構大致相同。
The
所述封裝結構100的柵極引出端11和第二導線架16連接於所述第一內側線路層221a，所述封裝結構100’的第一導線架13連接於所述第一內側線路層221a。所述封裝結構100的第一導線架13(即，源極引出端)通過第一外側線路層222a連接於所述封裝結構100’的第二導線架16(即，漏極引出端)，即使得所述封裝結構100的源極S與所述封裝結構100’的漏極D相連接。
The
所述封裝結構100和封裝結構100’中貫穿設置有第二導電柱25b，所述第二導電柱25b依次電性連接於所述第一外側線路層222a、柵極引出端11、第一內側線路層221a、第一導電柱25a和第二外側線路層241a。
A second
部分所述第一外側線路層222a背離所述封裝結構100和所述封裝結構100’部分還設置有散熱塊27，以解決散熱問題。所述散熱塊27可以為銅層、銅塊或鰭片。
The portion of the first
在本實施例中，多個所述第一導電柱25a採用鐳射微孔並電鍍的方式形成。可以理解地，在其他實施例中，也可採用貫孔鍍銅的方式。所述第二導電柱25b採用貫孔鍍銅的方式形成。
In this embodiment, the plurality of first
本實施例中，通過將所述封裝結構100和封裝結構100’相背設置，並通過第一外側線路層222a電性連接所述封裝結構100的源極S和所述封裝結構100’的漏極D，並於部分所述第一外側線路層222a外側設置散熱塊27，可一步提高整個內埋功率晶片的電路板組件300的功率密度，並能提高散熱。
In this embodiment, the
以上所述，僅是本申請的較佳實施方式而已，並非對本申請任何形式上的限制，雖然本申請已是較佳實施方式揭露如上，並非用以限定本申請，任何熟悉本專業的技術人員，在不脫離本申請技術方案範圍內，當可利用上述揭示的技術內容做出些許更動或修飾為等同變化的等效實施方式，但凡是未脫離本申請技術方案內容，依據本申請的技術實質對以上實施方式所做的任何簡單修改、等同變化與修飾，均仍屬於本申請技術方案的範圍內。 The above are only the preferred embodiments of the present application and are not intended to limit the present application in any form. Although the preferred embodiments of the present application are disclosed above, they are not intended to limit the present application. Any skilled person familiar with this field will , without departing from the scope of the technical solution of this application, when the technical content disclosed above can be used to make some changes or modifications to equivalent implementations with equivalent changes, but without departing from the content of the technical solution of this application, based on the technical essence of this application Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solution of the present application.
100:封裝結構 100:Package structure
110:第一表面 110: First surface
120:第二表面 120: Second surface
10:功率晶片 10:Power chip
G:柵極 G:Gate
S:源極 S: source
D:漏極 D:Drain
11:柵極引出端 11: Gate terminal
12:導線 12:Wire
13:第一導線架 13:First lead frame
14:第一焊接層 14: First welding layer
15:第二焊接層 15: Second welding layer
16:第二導線架、漏極引出端 16: Second lead frame, drain terminal
17:第三焊接層 17: The third welding layer
18:源極引出端 18: Source terminal
19:封裝體 19:Package
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111115243A TWI827014B (en) | 2022-04-21 | 2022-04-21 | Package structure and circuit board assembly with embedded power chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111115243A TWI827014B (en) | 2022-04-21 | 2022-04-21 | Package structure and circuit board assembly with embedded power chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW202344145A TW202344145A (en) | 2023-11-01 |
| TWI827014B true TWI827014B (en) | 2023-12-21 |
Family
ID=89720255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW111115243A TWI827014B (en) | 2022-04-21 | 2022-04-21 | Package structure and circuit board assembly with embedded power chip |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI827014B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201444031A (en) * | 2013-03-15 | 2014-11-16 | Renesas Electronics Corp | Semiconductor device and manufacturing method of the same |
| CN104900634A (en) * | 2014-03-05 | 2015-09-09 | 台达电子国际（新加坡）私人有限公司 | Package structure and stacked package module with same |
| CN111261596A (en) * | 2018-12-03 | 2020-06-09 | 杰米捷韩国株式会社 | Semiconductor package using multiple clip structures and method of manufacturing the same |
-
2022
- 2022-04-21 TW TW111115243A patent/TWI827014B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201444031A (en) * | 2013-03-15 | 2014-11-16 | Renesas Electronics Corp | Semiconductor device and manufacturing method of the same |
| CN104900634A (en) * | 2014-03-05 | 2015-09-09 | 台达电子国际（新加坡）私人有限公司 | Package structure and stacked package module with same |
| CN111261596A (en) * | 2018-12-03 | 2020-06-09 | 杰米捷韩国株式会社 | Semiconductor package using multiple clip structures and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW202344145A (en) | 2023-11-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9589869B2 (en) | Packaging solutions for devices and systems comprising lateral GaN power transistors | |
| US9824949B2 (en) | Packaging solutions for devices and systems comprising lateral GaN power transistors | |
| US9659854B2 (en) | Embedded packaging for devices and systems comprising lateral GaN power transistors | |
| TWI399836B (en) | Wafer level chip scale package and process of manufacture | |
| TWI590395B (en) | Power encapsulation module of multi-power chip and manufacturing method of power chip unit | |
| TW201631722A (en) | Encapsulation module of power-converting circuit and manufacturing method thereof | |
| US10312194B2 (en) | Stacked electronics package and method of manufacturing thereof | |
| US7163841B2 (en) | Method of manufacturing circuit device | |
| TW201423947A (en) | Stacked type power device module | |
| US10700035B2 (en) | Stacked electronics package and method of manufacturing thereof | |
| TWI686878B (en) | Packaging process and packaging structure | |
| US9093277B2 (en) | Semiconductor device and method of manufacturing the same | |
| US10770444B2 (en) | Electronics package having a multi-thickness conductor layer and method of manufacturing thereof | |
| TWI827014B (en) | Package structure and circuit board assembly with embedded power chip | |
| TW200843063A (en) | Structure of semiconductor chip and package structure having semiconductor chip embedded therein | |
| JP3203228B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3757766B2 (en) | SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE | |
| CN116978881A (en) | Packaging structure and circuit board assembly with embedded power chip | |
| EP2800130A1 (en) | Chip-to-substrate transient liquid phase bonding using a spacer | |
| JP4088394B2 (en) | Insulated circuit board and semiconductor device using the same | |
| CN111244061A (en) | Packaging structure of gallium nitride equipment | |
| WO2024109434A1 (en) | Gan device packaging structure and packaging method therefor | |
| US11728289B2 (en) | Integrated magnetic assembly with conductive field plates | |
| TWI831247B (en) | Power module and method for manufacturing the same | |
| CN118198048A (en) | Packaging structure and packaging method of high-voltage control device |