CN205122585U - Cermet table pastes encapsulation transistor array board - Google Patents
Cermet table pastes encapsulation transistor array board Download PDFInfo
- Publication number
- CN205122585U CN205122585U CN201520957291.3U CN201520957291U CN205122585U CN 205122585 U CN205122585 U CN 205122585U CN 201520957291 U CN201520957291 U CN 201520957291U CN 205122585 U CN205122585 U CN 205122585U
- Authority
- CN
- China
- Prior art keywords
- layer
- conductive layer
- contact
- transistor array
- array board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model relates to a cermet table pastes encapsulation transistor array board, the transistor array board includes the base plate and forms the first conducting layer on the base plate, first grid insulating layer on the first conducting layer, semiconductor layer on the first grid insulating layer, at least the part forms on this semiconductor layer and including the data line and the second conducting layer of drain electrode that separate each other, and this second conducting layer is including blockking the lower part membrane that the metal constitutes and the upper portion membrane of al or al alloy constitution, cover this semiconductor layer's passivation layer, and form on this second conducting layer and with the third conducting layer of second conducting layer contact, wherein, to lie in the lower part epimembranal at an edge of this upper portion membrane at least for the lower part membrane includes the first portion of dew outside the membrane of upper portion, and this first portion of third conducting layer contact lower part membrane, the edge of upper portion membrane crosss the lower part membrane, the passivation layer has the contact hole that this first portion of lower part membrane is exposed to at least part, third conducting layer at least some be located the passivation layer.
Description
Technical field
The utility model belongs to technical field of semiconductors, particularly a kind of cermet surface mount packages transistor array board.
background technology
Usually, integrated circuit comprises the combination being formed in NMOS (η type Metal-oxide-semicondutor) transistor on substrate and PMOS (P type Metal-oxide-semicondutor) transistor.The performance of the performance of integrated circuit and its transistor comprised has direct relation.Therefore, wish that the drive current improving transistor is to strengthen its performance.
U.S. Patent application No.20100038685 Α discloses a kind of transistor, dislocation is formed between the channel region and source/drain region of this transistor, this dislocation produces tension stress, and this tension stress improves the electron mobility in raceway groove, and the drive current of transistor is increased thus.Silicon injection is carried out to the semiconductor substrate defining gate-dielectric and grid, thus forms non-crystalline areas.Anneal to this semiconductor substrate, make non-crystalline areas recrystallization, in recrystallization process, meeting in two on horizontal direction and vertical direction different crystal growth front ends, thus defines dislocation.
Utility model content
The purpose of this utility model is to solve the problem, and proposes a kind of cermet surface mount packages transistor array board.
A kind of cermet surface mount packages transistor array board, described transistor array board comprises substrate and is formed in the first conductive layer on substrate; First grid insulating barrier on first conductive layer; Semiconductor layer on first grid insulating barrier; Being formed at least partly on this semiconductor layer and comprising the second conductive layer of data wire spaced apart from each other and drain electrode, this second conductive layer comprises lower film that barrier metal forms and the upper membrane that Al or Al alloy is formed; Cover the passivation layer of this semiconductor layer; And to be formed on this second conductive layer and with the 3rd conductive layer of the second conductive layers make contact, wherein, at least an edge of this upper membrane is positioned in lower film, lower film is comprised be exposed at the Part I outside upper membrane, and this Part I of the 3rd conductive layers make contact lower film; The edge of upper membrane traverses lower film; Passivation layer has the contact hole of this Part I exposing lower film at least partly; 3rd conductive layer be positioned on passivation layer at least partially; And this at least one edge of upper membrane not with the overlapping margins of contact hole; Lower film near passivation layer contact contact hole; Lower film comprises Cr, Mo or Mo alloy; Also comprise the ohmic contact layer between semiconductor layer and the second conductive layer; Ohmic contact layer has the flat shape substantially identical with the second conductive layer; The border of semiconductor layer or roughly overlap with the border of the second conductive layer, or be positioned at outside the second conductive layer; 3rd conductive layer comprises ITO or IZO.
Described array board also comprises the data wire be arranged on substrate; Described data wire and first grid epipolar lines intersect, described first grid polar curve comprises gate electrode; Described first grid insulating barrier, to be arranged on gate line and to have the contact hole exposing described data wire; Described passivation layer is arranged on the semiconductor layer; Comprise the insulator layer be arranged between described semiconductor layer and described passivation layer further; Also comprise interlayer insulating film, this interlayer insulating film is arranged between data wire and gate line; 3rd conductive layer comprises the pixel electrode of contact drain electrode; Passivation layer have for the contact between drain electrode and pixel electrode the first contact hole, expose the second contact hole of a part for the first conductive layer and expose the 3rd contact hole of a part of data wire, and the 3rd conductive layer comprises the first contact slave part by the second contact holes contact first conductive layer and the second contact slave part by the 3rd contact holes contact data wire; The Part I of the second conductive layer is uneven.
Described transistor array board also comprises ceramic metallization pipe base, metal cover board, wherein metal cover board and ceramic metallization shell encapsulate and form shell, shell arranges flat outer lead, ceramic metallization pipe base is equipped with the metallized area that eight parts are independent and arranged in parallel, eight silicon rectifying diode chips are bonded on corresponding metallized area by conducting resinl respectively, be electrically connected by the shell inside cavity part of Si-Al wire by silicon rectifying diode chip and outer lead, shell inside cavity adopts AB glue to fill.
Described substrate is composited by carbon, carborundum, silicon nitride, aluminium oxide and silicon, and described substrate is of five storeys from outside to inside altogether, and be silicon layer, silicon nitride layer, silicon carbide layer, carbon-coating and alumina substrate layer respectively, the thickness of every layer is 0.5-3mm.
Accompanying drawing explanation
Fig. 1 is the cross sectional representation of a kind of cermet surface mount packages transistor array board according to an embodiment of the present utility model;
Fig. 2 is the structural representation of substrate.
Wherein, 1 is substrate; 2 is first conductive layers; 3 is second conductive layers; 4 is semiconductor layers; 5 is ohmic contact layers; 6 is the 3rd conductive layers; 7 is gate insulators; 11 are silicon layers, 12 are silicon nitride layers, 13 are silicon carbide layers, 14 are carbon-coatings, 15 is alumina substrate layers.
Embodiment
A kind of cermet surface mount packages transistor array board, described transistor array board comprises substrate and is formed in the first conductive layer on substrate; First grid insulating barrier on first conductive layer; Semiconductor layer on first grid insulating barrier; Being formed at least partly on this semiconductor layer and comprising the second conductive layer of data wire spaced apart from each other and drain electrode, this second conductive layer comprises lower film that barrier metal forms and the upper membrane that Al or Al alloy is formed; Cover the passivation layer of this semiconductor layer; And to be formed on this second conductive layer and with the 3rd conductive layer of the second conductive layers make contact, wherein, at least an edge of this upper membrane is positioned in lower film, lower film is comprised be exposed at the Part I outside upper membrane, and this Part I of the 3rd conductive layers make contact lower film; The edge of upper membrane traverses lower film; Passivation layer has the contact hole of this Part I exposing lower film at least partly; 3rd conductive layer be positioned on passivation layer at least partially; And this at least one edge of upper membrane not with the overlapping margins of contact hole; Lower film near passivation layer contact contact hole; Lower film comprises Cr, Mo or Mo alloy; Also comprise the ohmic contact layer between semiconductor layer and the second conductive layer; Ohmic contact layer has the flat shape substantially identical with the second conductive layer; The border of semiconductor layer or roughly overlap with the border of the second conductive layer, or be positioned at outside the second conductive layer; 3rd conductive layer comprises ITO or IZO.
Described array board also comprises the data wire be arranged on substrate; Described data wire and first grid epipolar lines intersect, described first grid polar curve comprises gate electrode; Described first grid insulating barrier, to be arranged on gate line and to have the contact hole exposing described data wire; Described passivation layer is arranged on the semiconductor layer; Comprise the insulator layer be arranged between described semiconductor layer and described passivation layer further; Also comprise interlayer insulating film, this interlayer insulating film is arranged between data wire and gate line; 3rd conductive layer comprises the pixel electrode of contact drain electrode; Passivation layer have for the contact between drain electrode and pixel electrode the first contact hole, expose the second contact hole of a part for the first conductive layer and expose the 3rd contact hole of a part of data wire, and the 3rd conductive layer comprises the first contact slave part by the second contact holes contact first conductive layer and the second contact slave part by the 3rd contact holes contact data wire; The Part I of the second conductive layer is uneven.
Described transistor array board also comprises ceramic metallization pipe base, metal cover board, wherein metal cover board and ceramic metallization shell encapsulate and form shell, shell arranges flat outer lead, ceramic metallization pipe base is equipped with the metallized area that eight parts are independent and arranged in parallel, eight silicon rectifying diode chips are bonded on corresponding metallized area by conducting resinl respectively, be electrically connected by the shell inside cavity part of Si-Al wire by silicon rectifying diode chip and outer lead, shell inside cavity adopts AB glue to fill.
Described substrate is composited by carbon, carborundum, silicon nitride, aluminium oxide and silicon, and described substrate is of five storeys from outside to inside altogether, and be silicon layer, silicon nitride layer, silicon carbide layer, carbon-coating and alumina substrate layer respectively, the thickness of every layer is 0.5-3mm.
Last it is noted that obviously, above-described embodiment is only for the utility model example is clearly described, and the restriction not to execution mode.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here exhaustive without the need to also giving all execution modes.And thus the apparent change of extending out or variation be still among protection range of the present utility model.
Claims (4)
1. a cermet surface mount packages transistor array board, is characterized in that: described transistor array board comprises substrate and is formed in the first conductive layer on substrate; First grid insulating barrier on first conductive layer; Semiconductor layer on first grid insulating barrier; Being formed at least partly on this semiconductor layer and comprising the second conductive layer of data wire spaced apart from each other and drain electrode, this second conductive layer comprises lower film that barrier metal forms and the upper membrane that Al or Al alloy is formed; Cover the passivation layer of this semiconductor layer; And to be formed on this second conductive layer and with the 3rd conductive layer of the second conductive layers make contact, wherein, at least an edge of this upper membrane is positioned in lower film, lower film is comprised be exposed at the Part I outside upper membrane, and this Part I of the 3rd conductive layers make contact lower film; The edge of upper membrane traverses lower film; Passivation layer has the contact hole of this Part I exposing lower film at least partly; 3rd conductive layer be positioned on passivation layer at least partially; And this at least one edge of upper membrane not with the overlapping margins of contact hole; Lower film near passivation layer contact contact hole; Lower film comprises Cr, Mo or Mo alloy; Also comprise the ohmic contact layer between semiconductor layer and the second conductive layer; Ohmic contact layer has the flat shape substantially identical with the second conductive layer; The border of semiconductor layer or roughly overlap with the border of the second conductive layer, or be positioned at outside the second conductive layer; 3rd conductive layer comprises ITO or IZO.
2. transistor array board according to claim 1, is characterized in that: described array board also comprises the data wire be arranged on substrate; Described data wire and first grid epipolar lines intersect, described first grid polar curve comprises gate electrode; Described first grid insulating barrier, to be arranged on gate line and to have the contact hole exposing described data wire; Described passivation layer is arranged on the semiconductor layer; Comprise the insulator layer be arranged between described semiconductor layer and described passivation layer further; Also comprise interlayer insulating film, this interlayer insulating film is arranged between data wire and gate line; 3rd conductive layer comprises the pixel electrode of contact drain electrode; Passivation layer have for the contact between drain electrode and pixel electrode the first contact hole, expose the second contact hole of a part for the first conductive layer and expose the 3rd contact hole of a part of data wire, and the 3rd conductive layer comprises the first contact slave part by the second contact holes contact first conductive layer and the second contact slave part by the 3rd contact holes contact data wire; The Part I of the second conductive layer is uneven.
3. transistor array board according to claim 1, it is characterized in that: described transistor array board also comprises ceramic metallization pipe base, metal cover board, wherein metal cover board and ceramic metallization shell encapsulate and form shell, shell arranges flat outer lead, ceramic metallization pipe base is equipped with the metallized area that eight parts are independent and arranged in parallel, eight silicon rectifying diode chips are bonded on corresponding metallized area by conducting resinl respectively, be electrically connected by the shell inside cavity part of Si-Al wire by silicon rectifying diode chip and outer lead, shell inside cavity adopts AB glue to fill.
4. transistor array board according to claim 1, it is characterized in that: described substrate is composited by carbon, carborundum, silicon nitride, aluminium oxide and silicon, described substrate is of five storeys from outside to inside altogether, be silicon layer, silicon nitride layer, silicon carbide layer, carbon-coating and alumina substrate layer respectively, the thickness of every layer is 0.5-3mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520957291.3U CN205122585U (en) | 2015-11-26 | 2015-11-26 | Cermet table pastes encapsulation transistor array board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520957291.3U CN205122585U (en) | 2015-11-26 | 2015-11-26 | Cermet table pastes encapsulation transistor array board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205122585U true CN205122585U (en) | 2016-03-30 |
Family
ID=55578166
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520957291.3U Active CN205122585U (en) | 2015-11-26 | 2015-11-26 | Cermet table pastes encapsulation transistor array board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205122585U (en) |
-
2015
- 2015-11-26 CN CN201520957291.3U patent/CN205122585U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1819259B (en) | Package for gallium nitride semiconductor devices | |
| US20160322969A1 (en) | Half-bridge hemt circuit and an electronic package including the circuit | |
| JP2009302564A5 (en) | ||
| CN103972193B (en) | Power transistor arrangement and method for manufacturing the same | |
| JP2006319204A (en) | Semiconductor device and manufacturing method therefor | |
| US20060076660A1 (en) | Power transistor | |
| US10051742B2 (en) | Power module and manufacturing method thereof | |
| TW201340261A (en) | Semiconductor device and manufacturing method thereof | |
| CN103636001A (en) | Gold-free ohmic contacts | |
| CN107534040A (en) | Arrangement of optoelectronic components and the method for manufacturing a large amount of arrangement of optoelectronic components | |
| TW201234601A (en) | Vertical semiconductor device and manufacturing method therefor | |
| JP5684157B2 (en) | Semiconductor device | |
| US9853023B2 (en) | Semiconductor device and semiconductor package | |
| CN105938820B (en) | Electronic device and its Electronic Packaging | |
| US20150295044A1 (en) | Semiconductor device | |
| CN205122585U (en) | Cermet table pastes encapsulation transistor array board | |
| US4656055A (en) | Double level metal edge seal for a semiconductor device | |
| US20180308790A1 (en) | Semiconductor module | |
| US10991680B2 (en) | Common source land grid array package | |
| JP7365368B2 (en) | semiconductor equipment | |
| CN205122563U (en) | Cermet dual in line package diode array board | |
| CN205122580U (en) | High -power metal single in line package transistor array board | |
| JP2006216596A (en) | Semiconductor device and manufacturing method thereof | |
| JP2017011176A (en) | Semiconductor device and semiconductor device manufacturing method | |
| CN204189783U (en) | Reduce the encapsulating structure of MOS chip internal resistance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |