CN203561840U - Transformer station GPS time-setting IRIG-B decoder - Google Patents

Abstract

Provided is a transformer station GPS time-setting IRIG-B (inter-range instrumentation group) decoder, comprising a master control chip, and a power circuit, a crystal oscillator circuit, a reset circuit, and a serial port communication circuit connected on the periphery of the master control chip. The decoder is characterized in that the master control chip uses a STM8S103F chip packaged by TSSOP20, an IRIG-B code signal is input from pins PC3 and PC4 corresponding to input capture channels of an advanced control counter/timer of a STM8S103F chip, and after decoding by the STM8S103F, absolute time is output from the serial port communication circuit. The decoder applies an edge capture technology of a powerful 16-bit advanced control timer of the STM8S103F to measure pulse width of IRIG-B code pulse to decode B codes, and can completely meet requirement of B code accurate decoding and timing of a transformer station. The decoder is advantaged by simple structure, small volume, low power consumption, high precision, etc. The decoder is applied successfully in a transformer station GPS & IRIG-B timing system.

Description

The GPS of transformer station to time IRIG-B demoder

Technical field

The utility model relates to a kind of demoder, specifically refer to a kind of GPS of transformer station to time IRIG-B demoder.

Background technology

Along with the expanding day of electric system scale and improving constantly of grid automation level; the accurate of time seems particularly important with being unified in safe operation of power system, and it is distinct device sequence of event, fault localization, accident time series analysis, electric energy tariffing, relay protection, the automatic time reference of controlling.

In the technical manual of State Grid Corporation of China issue, explicitly call for the electric substation automation system bay device that needs time service newly putting into operation should adopt in principle GPS & IRIG-B code to time mode realize to time.GPS & IRIG-B code time system is IRIG-B(Inter-Range Instrumentation Group general between gps satellite signal and modernization target range, target range instrument group Type B form) serial timing code is packaged in one, and the timing services of high precision cheapness is provided.IRIG-B code to time mode be a kind of accurately to time scheme, comprise punctual second start point information and absolute time information, can set up independent setting network, a GPS receiving terminal only need be installed by each transformer station, utilize RS422/485 transmission time code, before end device, install that the demoder with standard RS422/485 interface can be decoded the deadline and equipment accurately to time, be suitable for short range transmission, demoder is the most complicated part of most critical, and GPS & IRIG-B code time system structural drawing as shown in Figure 1.

IRIG-B code (be called for short B code) is IRIG(Inter-Range Instrumentation Group) six kinds of form type codes a kind of, with its actual outstanding superior function, become the standard pattern of timing equipment first-selection.Without amplitude modulation(PAM) be called IRIG-B code, standard B code frame structure is as shown in Figure 2.During B code, frame rate was 1 frame/second, and all time formats are all pulsewidth codes, index count interval 10ms, and 100 code elements of every frame, code element has three kinds.The forward position of location recognition mark P 0 is at the previous index count of frame reference point (being PR) interval, every ten code elements have a location recognition sign later, be respectively P1, P2......, P9, represent that the witness marker that a time format frame starts is comprised of a location recognition sign (P0) and adjacent reference symbols sn (PR), pulsewidth is 8ms; The pulsewidth of binary one and " 0 " is respectively 5ms and 2ms.B code sequential is second-minute-time-sky-year, position at P0 between P6, wherein second 7 of 7, minutes, time 8 of 6, day 10, years, by weighted calculation, parse universal standard time format.The designing requirement of IRIG-B code demoder be can solve in real time year in coded message, sky, time, minute, second information, and by asynchronous communication mouth, be sent to other equipment in real time.

Nowadays the market demand of IRIG-B demoder is very large, domestic many coding/decoding methods and the Related product of also having occurred, but due to restriction and the implementation method of device itself, there is the weak points such as decode procedure is complicated, volume is large, power consumption is large.As the decoding design precision based on technology such as CPLD, FPGA has reached requirement, but too complicated; The demoder of the productions such as the synchronous electronics scientific technology co in Xi'an is case type, and volume is large, power consumption is large; The time message form of the demoder of the productions such as Jinan Wei Shang Electronics Co., Ltd. is not standard B code form, there is no afterwards advantage in the standardization in market; Shenzhen Yun Chen Science and Technology Ltd. has developed a series of IRIG-B professional chip of decoding, but only has at present a kind of volume production that realized, and monolithic price is 40 yuan of left and right, and price is very high comparatively speaking.Based on above problem, need existing IRIG-B demoder to be improved.

Utility model content

Technical problem to be solved in the utility model is for above-mentioned prior art present situation, provide a kind of simple in structure, precision is high, volume is little, power consumption is little and can reach completely accurately to time the GPS of transformer station that requires to time IRIG-B demoder.

The utility model solves the problems of the technologies described above adopted technical scheme: the GPS of this transformer station to time IRIG-B demoder, comprise main control chip and be connected to the power circuit of main control chip periphery, crystal oscillating circuit, reset circuit and serial communication circuit, it is characterized in that: described main control chip adopts the STM8S103F chip of TSSOP20 encapsulation, IRIG-B coded signal is from the corresponding pin PC3 of input capture passage and the PC4 input of the senior control counting/timing device TIM1 of STM8S103F chip, and by described serial communication circuit, export absolute time after described STM8S103F chip decoding.

Preferably, it is main control chip that described serial communication circuit adopts MAX232, and the pin T1in of MAX232 main control chip is connected with the pin RX of described STM8S103F chip.

Further preferably, also include a program burn writing circuit, the SWIM interface of this program burn writing circuit is connected with the SWIM data-interface of described STM8S103F chip.

As preferred version, also include a usb circuit of being powered by described power circuit.

As another preferred version, described power circuit and STM8S103F chip are all circumscribed with LED indicating circuit.

As above-mentioned arbitrary scheme preferably, include frequency division module, TIM1 edge trapping module, calculate transcoding module switching time, the functional module such as display module and interface module, system reference clock frequency after frequency division module as the frequency of TIM1 edge trapping module, described TIM edge trapping module carries out exporting to after catch at edge the input end of described calculating transcoding module switching time to IRIG-B code, the output terminal of described calculating transcoding module switching time is connected with the input end of described interface module, the output terminal of described calculating transcoding module switching time is connected on described display module simultaneously.

Compared with prior art, the pulsewidth that the utility model uses the edge capture technique of 16 senior control timer TIM1 that STM8S103F is powerful to measure the pulse of IRIG-B code innovatively realizes the decoding of B code, can meet accurately the decode requirement of time service of the B of transformer station code completely, and have simple in structure, volume is little, power consumption is little, precision advantages of higher, the utilization of succeeding in the Yi GPS & IRIG-B of transformer station time dissemination system at present.

Accompanying drawing explanation

Fig. 1 is GPS & IRIG-B code time system structural drawing;

Fig. 2 is standard IR IG-B code frame assumption diagram;

Fig. 3 is IRIG-B code decoder function structured flowchart;

Fig. 4 is IRIG-B code decoder circuit schematic diagram;

Fig. 5 is the program flow diagram of IRIG-B code demoder.

Embodiment

Below in conjunction with accompanying drawing, embodiment is described in further detail the utility model.

As shown in Figure 3, the GPS of this transformer station to time IRIG-B code demoder (being called for short B code demoder) be mainly divided into five functional modules, be respectively frequency division module, TIM1 edge trapping module, calculate transcoding module switching time, display module and interface module, wherein the part of most critical is TIM1 edge trapping module.System reference clock frequency adopt 8Mhz and after frequency division module as the frequency of TIM1 edge trapping module, described TIM edge trapping module carries out exporting to after catch at edge the input end of described calculating transcoding module switching time to IRIG-B code, the output terminal of described calculating transcoding module switching time is connected with the input end of described interface module, and the output terminal of described calculating transcoding module switching time is connected on described display module simultaneously.

1, the hardware design of B code demoder

As shown in Figure 4, main control chip adopts the STM8S103F of ST company, adopt TSSOP20 packing forms, it has 16 powerful senior control timer TIM1, containing 4, catch/compare passage, input capture passage 3 and input capture passage 4 be corresponding pin PC3 and PC4 respectively, and acquisition accuracy can reach us level, the position that can synchronously occur at pulse edge flexibly completely.Meanwhile, this main control chip has the adjustable inner 16Mhz RC of user, has the Harvard structure of 3 level production lines, 8K bytes Flash, 1K byte RAM.

Decoder circuit comprises power circuit, crystal oscillating circuit, reset circuit, serial communication circuit, program burn writing circuit and usb circuit, and wherein, power circuit provides 3.3V and two kinds of power supplys of 5V, is above-mentioned each circuit supply.

Particularly, IRIG-B coded signal is inputted from the corresponding pin PC3 of input capture passage and the PC4 of the senior control counting/timing device TIM1 of STM8S103F chip, and by serial communication circuit, exports absolute time after the decoding of STM8S103F chip.It is main control chip that serial communication circuit adopts MAX232, and the pin T1in of MAX232 main control chip is connected with the pin RX of STM8S103F chip.The SWIM interface of program burn writing circuit is connected with the SWIM data-interface of STM8S103F chip.In addition, in decoder hardware circuitry design, power circuit and STM8S103F chip are all circumscribed with LED indicating circuit.

2, the Software for Design of B code demoder

The function of IRIG-B code demoder is first from timing code frame, to judge the on-time point of second, then utilize the input capture function of STM8S103F timer TIM1 to carry out the seizure of porch counting, by count value, calculate pulse high level time width, and according to the position extracting time information of 5ms and 2ms pulse appearance, be converted into binary-coded decimal and be stored in internal memory, after being parsed with as far as possible little time delay by interface by absolute time be transferred to other devices complete to time.Development sequence is all used C language compilation.

1), frequency division

The inside 16MHz RC clock that clock selecting STM8S103F is adjustable, the 8MHz clock after two frequency divisions is as system reference clock frequency.

The pre-divider of 16 senior control counting/timing device TIM1 can be pressed the arbitrary value frequency division between 1 to 65536 by clock frequency, because B code index count is spaced apart 10ms, TIM1 count down to time cycle of 65536 from 1 and must be greater than 10ms, this TIM1 frequency is decided to be 0.5MHz, carry out again 16 frequency divisions, and with this frequency computation part high level time width.

2), catch at TIM1 edge

No matter adopt which kind of technical system to carry out the decoding of IRIG-B code, its key is all identification, the extraction of time code element, this has proposed to utilize timer edge capture technique to realize the new method of decoding, concrete methods of realizing is that timer capture channel register comes interim accurately seizure to record current count value at rising edge of a pulse, negative edge, then by adjacent twice count value and count frequency, calculate the pulsewidth of each symbol pulses, according to IRIG-B code principle, parse absolute time information.

The STM8S103F chip that this is selected, its senior control counting/timing device TIM1 is comprised of the automatic loading counter of 16, by a programmable pre-divider, is driven, and has four independently input capture/comparison passages.The I/O pin (TIM1_CCi) of timer can compare as input capture or output, and this function can be caught/compare the CCiS channel selecting position of channel pattern register (TIM1_CCMRi) and be realized by configuration.Each is caught/compares passage and builds round a catch/comparand register, catch/comparison module is comprised of a preloaded register and a shadow register, under acquisition mode, catch and occur on shadow register, and then copy in preloaded register.

In design process, the input capture passage 3 of TIM1, passage 4 are set to respectively to rising edge of a pulse is caught and lower liter along input capture pattern, timer TIM1 is set for count mode upwards, and enables input capture passage.After corresponding edge being detected on IC3/IC4 signal at every turn, the currency of counter can be latched to and catch/comparand register TIM1_CCR3/TIM1_CCR4 in.When there is capturing events, corresponding CC3IF/CC4IF sign (TIM1_SR register) is set to 1; If CC3IF/CC4IF sign has been high while there is capturing events, repeats so to catch sign CC3OF/CC4IF (TIM1_SR2 register) and be set to 1.Write CCiIF=0 or read the capture-data being stored in TIM1_CCRiL register and all can remove CCiIF, writing CCiOF=0 and can remove CCiOF.After having caught, immediately the count value in TIM1_CCR3/TIM1_CCR4 is saved in to internal memory at every turn, with this, cyclically carries out porch seizure.

3), calculate pulsewidth

According to the difference of the count value of catching for twice and TIM1 count frequency, calculate pulse.

4), judgement IRIG-B code time frame on-time point second

According to IRIG-B code form, second 8ms pulse front edge in continuous two 8ms broad pulses is the punctual starting point of second, therefore using two continuous 8ms broad pulses as information header, only have the punctual starting point of correctly judging second just can parse correct temporal information.

5), turn binary-coded decimal storage

IRIG-B code has 3 kinds of code elements, and wherein two kinds of code elements of 5ms and 2ms have represented temporal information, and when turning binary-coded decimal, scale-of-two binary-coded decimal " 1 " and " 0 " represent respectively 5ms and 2ms pulsewidth.Owing to can have error unavoidably when calculating, during transcoding, according to 3 kinds of code elements of B code, set a Uncrossed scope to the pulsewidth of calculating.Transcoding table is as shown in table 1.

Code element	Transcoding scope	Binary-coded decimal
			2ms	1-3ms	0
5ms	4-6ms	1
			8ms	7-9ms	?

Table 1

Because IRIG-B code temporal information is kept in 38 code elements between P0-P6, therefore the internal memory of opening must be greater than 38.By 96 pulse required times that detection show that TIM1 catches, transcoding, storage P0 start, be about 950ms; After having stored, be weighted immediately and resolve and absolute time information output, be about during this period of time very short.For reducing error, internal memory is opened 96 bytes, time code element binary-coded decimal of a bytes store, front 96 code element information of Coutinuous store.

6), absolute time is calculated and output

According to second-minute-the position extraction time binary-coded decimal information in time-sky-year is weighted, while calculating time second, on original basis, adding one second, after parsing by interface by absolute time be transferred to other devices complete to time, within time error just can be controlled at interior 50ms like this.

7), programming

Development sequence is all used C language compilation, and wherein most important part is initialization and the pattern setting of timer TIM1 input capture passage.In addition, for eliminating counting, overflow the impact of calculated value next time, after once having calculated, immediately correlated variables sum counter TIM1 is carried out to zero clearing.Wherein, IRIG-B code decoding process figure as shown in Figure 5.

3, emulation testing

The IRIG-B coded signal of simulation is carried out to test decode by introducing pin PC3 and the PC4 of TIM1 input capture passage 3, passage 4 correspondences.Test result shows the IRIG-B code to input, and demoder can be exported in decoding promptly and accurately, continous-stable work for a long time.The GPS & IRIG-B demoder of 16 senior control timer TIM1 designs that this time the utilization STM8S103F of novelty is powerful, can meet the requirement of automation of transformation substations time dissemination system decoding time service completely.

4, decoder function

GPS receiving terminal transmits IRIG-B timing code by RS422/232/485, and demoder is decoded to the IRIG-B code of input, and by RS232/485, exports absolute time and carry out time service.

5, decoder technique parameter

(1) supply voltage: 3.3V/5V;

(2) RS422/232/485 input IRIG-B code timing code, exports absolute time by RS232/485 after the IRIG-B code of input is decoded and carries out time service;

(3) single-chip system clock: 8MHz;

(4) base: 0.5MHz during timer TIM1;

(5) serial ports output arranges: baud rate 115200,8 bit data positions, 1 position of rest, no parity check position;

(6) synchronously to time precision≤50ms.

Claims (6)

1. The GPS of 1.Yi Zhong transformer station to time IRIG-B demoder, comprise main control chip and be connected to power circuit, crystal oscillating circuit, reset circuit and the serial communication circuit of main control chip periphery, it is characterized in that: described main control chip adopts the STM8S103F chip of TSSOP20 encapsulation, IRIG-B coded signal is inputted from the corresponding pin PC3 of input capture passage and the PC4 of the senior control counting/timing device TIM1 of STM8S103F chip, and by described serial communication circuit, exports absolute time after described STM8S103F chip decoding.
2. The GPS of transformer station according to claim 1 to time IRIG-B demoder, it is characterized in that: it is main control chip that described serial communication circuit adopts MAX232, and the pin T1in of MAX232 main control chip is connected with the pin RX of described STM8S103F chip.
3. The GPS of transformer station according to claim 1 and 2 to time IRIG-B demoder, it is characterized in that: also include a program burn writing circuit, the SWIM interface of this program burn writing circuit is connected with the SWIM data-interface of described STM8S103F chip.
4. The GPS of transformer station according to claim 1 and 2 to time IRIG-B demoder, it is characterized in that: also include a usb circuit of being powered by described power circuit.
5. The GPS of transformer station according to claim 1 and 2 to time IRIG-B demoder, it is characterized in that: described power circuit and STM8S103F chip are all circumscribed with LED indicating circuit.
6. The GPS of transformer station according to claim 1 and 2 to time IRIG-B demoder, it is characterized in that: include frequency division module, TIM1 edge trapping module, calculate transcoding module switching time, the functional module such as display module and interface module, system reference clock frequency after frequency division module as the frequency of TIM1 edge trapping module, described TIM edge trapping module carries out exporting to after catch at edge the input end of described calculating transcoding module switching time to IRIG-B code, the output terminal of described calculating transcoding module switching time is connected with the input end of described interface module, the output terminal of described calculating transcoding module switching time is connected on described display module simultaneously.

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