CN101937254A - Method for realizing IRIG-B signal decoding time correction - Google Patents
Method for realizing IRIG-B signal decoding time correction Download PDFInfo
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Abstract
The invention relates to a method for realizing the IRIG-B signal decoding time correction by using an IRIG-B signal decoding time correction card device based on a CPCI-bus, which comprises the following steps: receiving a B-code signal; carrying out pulse width detection decoding on the B-code signal so as to obtain time correction information, sending the time correction information to a remote device on the CPCI-bus to carry out time synchronous correction. The method for realizing the IRIG-B signal decoding time correction by using an IRIG-B signal decoding time correction card device based on a CPCI-bus effectively ensures the local clock synchronization of a microcomputer device, and controls the mutual error within 0.01 ms, and has the advantages of simple and practical structure, fast and efficient working process, stable and reliable working performance, and wider scope of application, therefore, the invention is suitable for an automation communication system of a transformer substation.
Description
The application for the applying date be that April 7, application number in 2009 are 200910048933.7, denomination of invention is the dividing an application of application for a patent for invention in " based on the IRIG-B signal decoding school of cpci bus time card device and method " thereof.
Technical field
The present invention relates to embedded computer platform field, particularly technical field during embedded computer distributed system school, card device and method thereof when specifically being meant a kind of IRIG-B signal decoding school based on cpci bus.
Background technology
Electric system adopts event sequence (SOE, Sequence Of Event) to determine the priority of power failure usually, and the foundation of carrying out the electric power system fault rational analysis, the correctness of SOE time directly can have influence on the result of fault analysis.
Produce these SOE just such as measure and control device; microcomputer protecting device; fault wave recording device; the PMU device; little electric current line selection apparatus; the arc suppression coil aut.eq.; the AVQC device; state monitoring apparatus; the microcomputer device of information acquisitions such as D.C. isolation monitoring device control, these microcomputer devices become supervisory system respectively according to self different principle and characteristics; the relay protection fault information analysis system; the state on_line monitoring analytic system; the scheduling of electrical production such as WAMAP system; the operation power maintenance analysis; power failure is analyzed; the elementary cell of power failure forecast analysis.
Only the system clock of guaranteed microcomputer device is correct, could guarantee time correctly available of logout, so that the clock synchronization issue of each microcomputer device just seems is very important.
In the prior art at present, conventional microcomputer device product adopts pulse mode (PPM, PPS) basically, this mode is simple and practical, but need external complement year, month, day, hour, min, the temporal information of second, if cooperate bad with main website, can bring very big error, bring very big difficulty, can't embody the superiority of GPS to power system fault analysis.
IRIG (Inter-Range Instrumentation Group) is the affiliated institutions of the U.S. Range Command council, is called " range time group ".The IRIG time standard has two big classes:
(1) one class is a parallel time sign indicating number form, and this class sign indicating number is owing to be parallel form, and transmission range is nearer, and is scale-of-two, and it is extensive therefore to can not show a candle to serial form;
(2) another kind of is the serial timing code, has six kinds of forms, i.e. A, B, D, E, G, H.
Their main difference is the frame rate difference of timing code.Frame rate was 1 frame/s when the principal feature of B sign indicating number was; Carry and contain much information, after decoding, can obtain 1,10,100, the pulse signal of 1000c/s and the temporal information and the control function information of BCD coding; High resolving power; B sign indicating number bandwidth after the modulation is applicable to long-distance transmissions; Divide direct current, exchange two kinds; Have nuclear interface standardizing, international.IRIG-B (DC) timing code form is conventional known technology, sees also shown in Figure 1ly, and its frame rate is 1 frame/s, 1 frame (1s) can be divided into 10 words, and every word is 10, and every cycle is 10ms.Every all begins with high level, and its duration is divided into 3 types: and 2ms (as binary zero sign indicating number and index mark), 5ms (as the binary one sign indicating number) and 8ms (as reference symbols sn, promptly first of first word that begins of per second; Tick lables P0～P9, promptly the tenth of each word the).What first word transmitted is second (s) information, and second word is branch (min) information, (h) information when the 3rd word is, and fourth, fifth word is day (d) (the year day of year that calculated since January 1).In addition, have respectively in the 8th word and the tenth word that the spy at station and substation marks handle unit on 3 bit representations.
This shows to decode and to discern the IRIG-B signal must carry out pulsewidth and detect, and does not also have a kind of complete implementation in present technical scheme, will give host CPU with the IRIG-B decoded data in addition, also will transmit by cpci bus.
CPCI (compression PCI, CompactPCI) be the expansion of computer PCI bus in built-in field, it is that IEC 2mm high density pin hole connects that hardware configuration changes the gold finger plate card connection, bus specification has been stipulated on the backboard between each slot, system's groove and backboard, strict interconnected relationship between I/O template and the backboard has defined the structure and the size of backboard, template and front and back panel.Define 32 PCI of P1 support and operate, P1 and P2 support 64 PCI operations, and P3, P4 and P5 leave user's use for or expand usefulness as bus.Standard also is the Clock signal distributions of 33MHz and 66MHz frequency of operation, has defined the strict design rule.Standard has also defined System Management Bus, and be on the backboard each slot definition unique physical address corresponding.Monolithic conductive and circuit design that the CPCI system is made up of metal shell and front and back panels make CPCI have ELECTROMAGNETIC RADIATION SHIELDING and static releasability, show good Electro Magnetic Compatibility.Therefore CPCI (Compact PCI) bus embedded type computing machine shows high safe reliability in the commercial production field.
Summary of the invention
The objective of the invention is to have overcome above-mentioned shortcoming of the prior art, a kind of card device and method thereof the local clock of each microcomputer device can be kept synchronously, effectively controlling clocking error, simple and practical, stable and reliable working performance, the scope of application comparatively widely based on the IRIG-B signal decoding school of cpci bus the time are provided.
In order to realize above-mentioned purpose, card device and method thereof are as follows during the IRIG-B signal decoding school based on cpci bus of the present invention:
Card device in the time of should be based on the IRIG-B signal decoding school of cpci bus, its principal feature is, described device comprises CPCI interface module, central authorities' decoding control module, B coded signal magnetic isolation load module, shows output module and power module, each module of described power module and other all is connected, described B coded signal magnetic is isolated load module and is connected with described demonstration output module by described central authorities decoding control module, and described central authorities decoding control module inserts the cpci bus of host computer system by described CPCI interface module.
Central authorities' decoding control module in the time of should be based on the IRIG-B signal decoding school of cpci bus in the card device comprises central control unit and B coded signal decoding unit, and described B coded signal decoding unit is connected with described central control unit.
B coded signal magnetic in the time of should be based on the IRIG-B signal decoding school of cpci bus in the card device is isolated load module and is comprised that TTL signal magnetic isolates input block, RS485 signal and receive that magnetic is isolated input block and analog to digital conversion magnetic is isolated input block, and described TTL signal magnetic is isolated input block, RS485 signal and received magnetic and isolate input block and analog to digital conversion magnetic and isolate input block and all be connected with the described central control module of decoding.
Demonstration output module in the time of should be based on the IRIG-B signal decoding school of cpci bus in the card device comprises that led display unit and control signal magnetic isolates output unit, described led display unit is connected with described central decoding control module, and should central authorities' decoding control module be connected with alarm relay by described control signal magnetic isolation output unit.
Method in the time of should realizing IRIG-B signal decoding school based on above-mentioned device, its principal feature is that described method may further comprise the steps:
(1) described device inserts the CPCI interface slot of host computer system, and host computer system is this device distributing system resource;
(2) described B coded signal magnetic is isolated the B coded signal that load module receives the external world;
(3) described B coded signal magnetic isolation load module is sent into the B coded signal that receives in the described central authorities decoding control module;
(4) described central authorities decodings control module is carried out pulsewidth to this B coded signal and is detected decoding processing, and information when obtaining corresponding school;
Information was to showing that output module sends the output control information when (5) described central decoding control module was according to resulting school;
The remote equipment that information was delivered on the cpci bus to be inserted by described CPCI interface module when (6) described central authorities decodings control module was with this school, described remote equipment during according to this school information carry out time synchronism calibration and handle.
Pulsewidth in method when this realizes IRIG-B signal decoding school detects decoding processing, may further comprise the steps:
(11) described central decoding control module reads the code element in the B coded signal;
(12) judge the scope of the symbol value of this code element;
(13) if this symbol value falls into 1900～2100 intervals, then putting and receiving bit is 0;
(14) if this symbol value falls into 4900～5100 intervals, then putting and receiving bit is 1;
(15), then be provided with and receive the bit position mark P if this symbol value falls into 7900～8100 intervals;
(16) otherwise with counter O reset, and, return above-mentioned steps (11) with the zero clearing of pulsewidth count value;
(17) value with counter increases by 1;
(18) judge that whether the value of counter is greater than 100;
(19) if, send the interruption that makes mistakes to host computer system, and, return above-mentioned steps (11) with the zero clearing of pulsewidth count value then with counter O reset;
(20) if not, judge then whether this reception bit position mark P is correct;
(21) if correctly, information during then according to the time information generating school in the B coded signal, and, return above-mentioned steps (11) with the zero clearing of pulsewidth count value;
(22) if incorrect,, and, return above-mentioned steps (11) with the zero clearing of pulsewidth count value then with counter O reset;
(23) finish after all code element all disposes in the B coded signal.
Information comprises year, month, day, hour, min, second information during school in the method during this realization IRIG-B signal decoding school.
Adopted this invention based on the IRIG-B signal decoding school of cpci bus the time card device and method thereof, owing to wherein detect decoding by the IRIG-B coded signal being carried out pulsewidth, and information output is sent to other remote equipment on the cpci bus by cpci bus simultaneously during with decoded school, carry out the clock synchronization correct operation for these equipment, thereby guaranteed that effectively the local clock of each microcomputer device keeps synchronously in the system, and can with each microcomputer device local clock each other error control in 0.01ms, not only simple and practical, and course of work quickness and high efficiency, stable and reliable working performance, the scope of application is comparatively extensive, is particularly useful for substation communication system field.
Description of drawings
Fig. 1 is IRIG-B of the prior art (DC) timing code form synoptic diagram.
The hardware configuration synoptic diagram of card device when Fig. 2 is the IRIG-B signal decoding school based on cpci bus of the present invention.
Fig. 3 is the process flow diagram that the pulsewidth of the IRIG-B signal decoding calibration method based on cpci bus of the present invention detects decoding processing.
Embodiment
In order more to be expressly understood technology contents of the present invention, describe in detail especially exemplified by following examples.
See also shown in Figure 1:
●
The relation between supply and demand of expression power supply
●
The expression signal data flows to
Card device in the time of should be based on the IRIG-B signal decoding school of cpci bus, isolate load module, show output module and power module comprising CPCI interface module, central authorities' decoding control module, B coded signal magnetic, each module of described power module and other all is connected, described B coded signal magnetic is isolated load module and is connected with described demonstration output module by described central authorities decoding control module, and described central authorities decoding control module inserts the cpci bus of host computer system by described CPCI interface module.
Wherein, described central authorities decoding control module comprises central control unit and B coded signal decoding unit, and described B coded signal decoding unit is connected with described central control unit; Described B coded signal magnetic is isolated load module and is comprised that TTL signal magnetic isolation input block, RS485 signal receive magnetic isolation input block and analog to digital conversion magnetic isolation input block, and described TTL signal magnetic is isolated input block, RS485 signal reception magnetic is isolated input block and all is connected with described central decoding control module with analog to digital conversion magnetic isolation input block.
Simultaneously, described demonstration output module comprises led display unit and control signal magnetic isolation output unit, described led display unit is connected with described central decoding control module, and should central authorities' decoding control module be connected with alarm relay by described control signal magnetic isolation output unit.
See also again shown in Figure 2, the method in the time of should realizing IRIG-B signal decoding school based on above-mentioned device, comprising following steps:
(1) described device inserts the CPCI interface slot of host computer system, and host computer system is this device distributing system resource;
(2) described B coded signal magnetic is isolated the B coded signal that load module receives the external world;
(3) described B coded signal magnetic isolation load module is sent into the B coded signal that receives in the described central authorities decoding control module;
(4) described central authorities decodings control module is carried out pulsewidth to this B coded signal and is detected decoding processing, and information when obtaining corresponding school; Described pulsewidth detects decoding processing, may further comprise the steps:
(a) described central decoding control module reads the code element in the B coded signal;
(b) judge the scope of the symbol value of this code element;
(c) if this symbol value falls into 1900～2100 intervals, then putting and receiving bit is 0;
(d) if this symbol value falls into 4900～5100 intervals, then putting and receiving bit is 1;
(e), then be provided with and receive the bit position mark P if this symbol value falls into 7900～8100 intervals;
(f) otherwise with counter O reset, and, return above-mentioned steps (a) with the zero clearing of pulsewidth count value;
(g) value with counter increases by 1;
(h) judge that whether the value of counter is greater than 100;
(i) if, send the interruption that makes mistakes to host computer system, and, return above-mentioned steps (a) with the zero clearing of pulsewidth count value then with counter O reset;
(j) if not, judge then whether this reception bit position mark P is correct;
(k) if correctly, information during then according to the time information generating school in the B coded signal, and, return above-mentioned steps (a) with the zero clearing of pulsewidth count value;
(l) if incorrect,, and, return above-mentioned steps (a) with the zero clearing of pulsewidth count value then with counter O reset;
(m) finish after all code element all disposes in the B coded signal;
Information comprises year, month, day, hour, min, second information during described school;
Information was to showing that output module sends the output control information when (5) described central decoding control module was according to resulting school;
The remote equipment that information was delivered on the cpci bus to be inserted by described CPCI interface module when (6) described central authorities decodings control module was with this school, described remote equipment during according to this school information carry out time synchronism calibration and handle.
In the middle of reality was used, card device had a following function during IRIG-B signal decoding school based on cpci bus of the present invention:
1. has IRIG-B sign indicating number error code correction function.
2. can discern and receive all types IRIG-B signal automatically.
3. there is clock face to show and software is adjusted function, during the computer monitor demonstration, minute, second.
4. can work in Windows 2000 and Linux platform, the Windows 2K and the Linux drive software of this demodulation card is provided with card).
5. device power fail warning output: this junction closure output after the industrial computer power down, up to sending the electricity back to discharge.
6. plant failure alarm output: this junction closure is exported after industrial computer crashes and delayed time 255 seconds, restarts also up to industrial computer to discharge behind the loading procedure.
7. watchdog reset pulse output: this junction closure discharged after the kind in one second automatically after industrial computer crashes and delayed time 255 seconds.
The corresponding techniques index is as follows:
(1) to the time precision:
IRIG-B(DC)＜50us；
IRIG-B(AC)＜400us。
(2) to the time 23: 59: 59 on the 31st Dec of 0: 00 second～2999 on the 1st January of 1970 valid period.
(3) the passive output contact of device power fail warning: 0.3A/125VAC or 0.27A/110DC or 1A/30VDC.
(4) plant failure is alarmed passive output contact: 0.3A/125VAC or 0.27A/110DC or 1A/30VDC.
(5) the passive pulse output contact of watchdog reset: 0.3A/125VAC or 0.27A/110DC or 1A/30VDC, pulsewidth 1s.
Receive modulation for the IRIG-B signal, because the IRIG-B signal has following two kinds of forms of expression:
●IRIG-B-DC
●IRIG-B-AC
Wherein the IRIG-B-DC signal is divided into Transistor-Transistor Logic level and RS422/485 level again, receives at signal and must satisfy in the modulation circuit design that can to accept whole above four types signals and can discern automatically be the model of which kind of type.
(1) the VHDL hardware description language carries out the IRIG-B signal decoding, and the IRIG-B signal decoding that receives is sent into fpga chip after light is isolated, and detects decoding by fpga chip according to the hardware description language algorithm pulsewidth of finishing writing in advance.
(2) PCI2.2 STD bus protocol processes: the IRIG-B signal is a binary data, unloading is in FPGA corresponding address internal memory, and by PCI interrupt informing the CPU main control module received gps to the time signal, the response of CPU main control module is interrupted, system by interrupt number distinguish be gps clock to the time module interruption of sending, read the time information data in this communication module corresponding address, and the automatic correction system time.
Among the present invention, software mainly is the design of CPCI card drive software:
Detecting under the situation of card:
Task one:
● start reception B sign indicating number
● start house dog
● regularly feed dog, be defaulted as 500ms once
● overtime house dog
● computing machine resets
● detect less than card and then continue to detect
Task two:
● receive interrupt notification
● enter interruption and can call program in the interruption at any time,, when query time, can use generally by down trigger
● read data
● judge whether effectively
● put the time
● invalidly then skip, wait for and interrupting
Card device and method thereof when having adopted above-mentioned IRIG-B signal decoding school based on cpci bus, owing to wherein detect decoding by the IRIG-B coded signal being carried out pulsewidth, and information output is sent to other remote equipment on the cpci bus by cpci bus simultaneously during with decoded school, carry out the clock synchronization correct operation for these equipment, thereby guaranteed that effectively the local clock of each microcomputer device keeps synchronously in the system, and can with each microcomputer device local clock each other error control in 0.01ms, not only simple and practical, and course of work quickness and high efficiency, stable and reliable working performance, the scope of application is comparatively extensive, is particularly useful for substation communication system field.
In this instructions, the present invention is described with reference to its certain embodiments.But, still can make various modifications and conversion obviously and not deviate from the spirit and scope of the present invention.Therefore, instructions and accompanying drawing are regarded in an illustrative, rather than a restrictive.
Claims (2)
1. the method when card device is realized IRIG-B signal decoding school during an IRIG-B signal decoding school based on cpci bus, described device comprises the CPCI interface module, central authorities' decoding control module, B coded signal magnetic is isolated load module, show output module and power module, each module of described power module and other all is connected, described B coded signal magnetic is isolated load module and is connected with described demonstration output module by described central authorities decoding control module, described central authorities decoding control module inserts the cpci bus of host computer system by described CPCI interface module, it is characterized in that described method may further comprise the steps:
(1) described device inserts the CPCI interface slot of host computer system, and host computer system is this device distributing system resource;
(2) described B coded signal magnetic is isolated the B coded signal that load module receives the external world;
(3) described B coded signal magnetic isolation load module is sent into the B coded signal that receives in the described central authorities decoding control module;
(4) described central authorities decodings control module is carried out pulsewidth to this B coded signal and is detected decoding processing, and information when obtaining corresponding school, and described pulsewidth detects decoding processing, may further comprise the steps:
(a) described central decoding control module reads the code element in the B coded signal;
(b) judge the scope of the symbol value of this code element;
(c) if this symbol value falls into 1900～2100 intervals, then putting and receiving bit is 0;
(d) if this symbol value falls into 4900～5100 intervals, then putting and receiving bit is 1;
(e), then be provided with and receive the bit position mark P if this symbol value falls into 7900～8100 intervals;
(f) otherwise with counter O reset, and, return above-mentioned steps (a) with the zero clearing of pulsewidth count value;
(g) value with counter increases by 1;
(h) judge that whether the value of counter is greater than 100;
(i) if, send the interruption that makes mistakes to host computer system, and, return above-mentioned steps (a) with the zero clearing of pulsewidth count value then with counter O reset;
(j) if not, judge then whether this reception bit position mark P is correct;
(k) if correctly, information during then according to the time information generating school in the B coded signal, and, return above-mentioned steps (a) with the zero clearing of pulsewidth count value;
(l) if incorrect,, and, return above-mentioned steps (a) with the zero clearing of pulsewidth count value then with counter O reset;
(m) finish after all code element all disposes in the B coded signal;
Information was to showing that output module sends the output control information when (5) described central decoding control module was according to resulting school;
The remote equipment that information was delivered on the cpci bus to be inserted by described CPCI interface module when (6) described central authorities decodings control module was with this school, described remote equipment during according to this school information carry out time synchronism calibration and handle.
2. the method during realization according to claim 1 IRIG-B signal decoding school is characterized in that, information comprises year, month, day, hour, min, second information during described school.
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| CN2009100489337A Division CN101515187B (en) | 2009-04-07 | 2009-04-07 | CPCI-bus-based IRIG-B signal decoding and time correcting card device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103199865A (en) * | 2012-01-10 | 2013-07-10 | 武汉凯默电气有限公司 | Optical serial port self-adaptive decoding circuit |
| CN103684730A (en) * | 2012-09-07 | 2014-03-26 | 北京旋极信息技术股份有限公司 | Time synchronization method |
| CN113791533A (en) * | 2021-07-02 | 2021-12-14 | 中国船舶重工集团公司第七0七研究所 | IRIG-B direct-current code decoding and time synchronization automatic switching method based on FPGA |
| CN115903438A (en) * | 2022-12-20 | 2023-04-04 | 西安超越申泰信息科技有限公司 | Method, device and equipment for time synchronization of B code and readable medium |
-
2009
- 2009-04-07 CN CN2010102624302A patent/CN101937254A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103199865A (en) * | 2012-01-10 | 2013-07-10 | 武汉凯默电气有限公司 | Optical serial port self-adaptive decoding circuit |
| CN103199865B (en) * | 2012-01-10 | 2016-06-15 | 武汉凯默电气有限公司 | A kind of light adaptive serial port decoding circuit |
| CN103684730A (en) * | 2012-09-07 | 2014-03-26 | 北京旋极信息技术股份有限公司 | Time synchronization method |
| CN113791533A (en) * | 2021-07-02 | 2021-12-14 | 中国船舶重工集团公司第七0七研究所 | IRIG-B direct-current code decoding and time synchronization automatic switching method based on FPGA |
| CN113791533B (en) * | 2021-07-02 | 2023-06-20 | 中国船舶重工集团公司第七0七研究所 | IRIG-B direct current code decoding and time synchronization automatic switching method based on FPGA |
| CN115903438A (en) * | 2022-12-20 | 2023-04-04 | 西安超越申泰信息科技有限公司 | Method, device and equipment for time synchronization of B code and readable medium |
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Application publication date: 20110105 |