CN202535341U - High-precision IRIG-B code time setting decoding plate - Google Patents

High-precision IRIG-B code time setting decoding plate Download PDF

Info

Publication number
CN202535341U
CN202535341U CN2012201438378U CN201220143837U CN202535341U CN 202535341 U CN202535341 U CN 202535341U CN 2012201438378 U CN2012201438378 U CN 2012201438378U CN 201220143837 U CN201220143837 U CN 201220143837U CN 202535341 U CN202535341 U CN 202535341U
Authority
CN
China
Prior art keywords
time
irig
fpga
signal
decoding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN2012201438378U
Other languages
Chinese (zh)
Inventor
吴旻
何鸣
王皓
王成进
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ANHUI JIYUAN POWER SYSTEM TECHNOLOGY Co Ltd
Original Assignee
ANHUI JIYUAN POWER SYSTEM TECHNOLOGY Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ANHUI JIYUAN POWER SYSTEM TECHNOLOGY Co Ltd filed Critical ANHUI JIYUAN POWER SYSTEM TECHNOLOGY Co Ltd
Priority to CN2012201438378U priority Critical patent/CN202535341U/en
Application granted granted Critical
Publication of CN202535341U publication Critical patent/CN202535341U/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Landscapes

  • Electric Clocks (AREA)

Abstract

The present utility model discloses a high-precision IRIG-B code time setting decoding plate. The decoding plate comprises an FPGA, an E<2>PROM , an RAM, a crystal oscillator, a JATG and an RESET; in an trigger pin of the FPGA, a rising edge and a falling edge are triggered and interrupted, the FPGA is used for realizing high-speed analysis and decoding of received IRIG-B code encoding signals and storing decoded real-time data to the RAM to be processed and operated; the E<2>PROM is used for storing a program for realizing time-setting analysis and decoding of the IRIG-B code encoding; the RAM is used for storing real-time data operation of FPGA decoding; the crystal oscillator is used for generating high-precision clock pulse signals needed by generation of the FPGA; the JTAG is used for downloading program in an on-line way, and the way of programming and welding a chip is not necessary during the producing process; and the RESET is used for restarting and resetting the decoding plate. By adopting the high-precision IRIG-B code time setting decoding plate, rapid analysis and calculation of the IRIG-B code signals can be realized, data safety can be enhanced, the profile dimension is small and precision is high.

Description

High accuracy IRIG-B sign indicating number to the time decoding deck
Technical field
The utility model relate to a kind of high accuracy IRIG-B sign indicating number to the time decoding deck.
Background technology
Along with increasing year by year of power consumption equipment and power consumption, people to the automation of electric power system and safe operation require increasingly high, and a key element of the automation of electric power system and safe operation be exactly the electrical network time accurately and unified.In recent years, along with popularizing of microcomputer automation equipment, the more urgent operation of power networks that requires realizes time unification.Global positioning system have high-precision to the time function, be used widely in electric power system.Just explicitly call in " about strengthening the notice of electric power secondary system Clock management " of State Grid Corporation of China issue adopt IRIG-B (Inter Range Instrumentation Group, U.S.'s target range instrument group) standard code progressively realize GPS device and related system or equipment to the time.
Traditional I RIG-B sign indicating number to the time Module Design framework be based on CPLD+MCU; The hardware designs more complicated; But the device of this paper exploitation has adopted single high performance extensive programmable gate array (FPGA) framework; Its hardware designs is simple and reliable, and the key point of this module mainly concentrate on to the time information decoding.The improvement project that in automation of transformation substations design, adopts this paper to propose can be simplified the design of IRIG-B sign indicating number time setting circuit; Raising to the time accuracy and reliability; Remedy the tradition to the time defective; Can realize multiplexing functions through update routine, effectively avoid function singleness, can't on-line debugging upgrading or the like problem.I am through consulting the related data of a large amount of IRIG-B sign indicating numbers, utilize the oscilloscope analysis waveform, accomplish to the time Module Design and making, use through on-the-spot test, obtained satisfied result of use.
Traditional setting means be to use low side CPU carry out simply to the time handle, adopt to the time pulse add the mode of serial ports, promptly send out to the time pulse in through the serial ports network send out to the time instruction.But conventional method exists a lot of not enough: the one, the too much resource that takies smart machine, the 2nd, the serial ports network to the time have time-delay, one second error possibly appear; The 3rd, function is very single; Four, performance is very unstable, is not suitable for the on-the-spot adverse circumstances of transformer station.
The utility model content
The utility model is the weak point that exists in the above-mentioned prior art for avoiding, provide a kind of high accuracy IRIG-B sign indicating number to the time decoding deck, with rapid analysis and calculating and the raising Information Security that realizes the IRIG-B coded signal.
The utility model adopts following technical scheme for the technical solution problem.
High accuracy IRIG-B sign indicating number to the time decoding deck, adopt 6 layers of printed circuit board, its design feature is to comprise FPGA, E 2PROM, RAM, crystal oscillator, JATG and RESET;
Said FPGA, it triggers pin and is set to rising and falling edges and triggers and interrupt, be used for the IRIG-B sign indicating number code signal that receives is carried out the high speed analysis decoding, and with the real-time data memory of decoding to RAM and processing operations;
Said E 2PROM, be used to store to IRIG-B sign indicating number coding carry out to the time analyze the program of decoding;
Said RAM is used to store the real time data computing that said FPGA decodes;
Said crystal oscillator is used to produce the needed high precision clock pulse signal of FPGA;
Said JTAG is used for online downloading, and need when producing, not carry out programming to chip and then welds;
Said RESET is used for restarting and resetting of decoding deck.
The high accuracy IRIG-B sign indicating number of the utility model to the time decoding deck design feature also be:
Described high accuracy IRIG-B sign indicating number to the time decoding deck also comprise signal input module and data communication module; Said signal input module comprises that B coded signal lightning protection circuit, light are at a distance from circuit, B coded signal modulate circuit, A/D modular converter and A/D control loop, GPIO input circuit; Said B coded signal lightning protection circuit, light are used for the abnormal signal of preliminary treatment B sign indicating number and convert abnormal signal into normal signal at a distance from circuit, B coded signal modulate circuit, give FPGA with normal signal then and handle; A/D modular converter and A/D control loop are used to gather 12 road 16bit analogue datas; The GPIO input circuit is used to handle the switching value input signal;
Said data communication module comprise RS232 soft to the time signaling interface and 1PPS firmly to the time signaling interface, be used for FPGA is decoded the B coded signal and sends in real time.
Said data communication module also comprises LVDS interface, SPI interface, TTL interface and GPIO interface.
Compared with present technology, the utility model beneficial effect is embodied in:
1) adopted high speed FPGA (Field-Programmable Gate Array in the utility model; Be field programmable gate array); Made full use of the ability of the superpower parallel computation of FPGA; Can realize the rapid analysis and the calculating of IRIG-B coded signal, and user's parameter storage is arranged, Information Security is high; 2) the utility model adopts based on the FPGA+ADC+GPIO framework, can under the situation of motionless hardware, realize function expansion and multiplexing, does not need to design again or revise the PCB circuit board; 3) the utility model utilizes IRIG-B sign indicating number fast decoding technology, and real-time analysis treatments B code data accurately analyzes real-time time, and computational speed is fast, precision high (less than 40 nanoseconds); 4) apparent size of the utility model little (40.9mmX65.7mm) is easy to cascade and expansion; 5) GPIO of the utility model employing is a multifunctional multiplexing IO mouth, also has RS232, SPI; LVDS or the like communication function interface; Such as at special time through other device of GPIO or communication port control, or install intelligent linkage or the like with other, use extremely flexibly, convenient; 6) the utility model can be used for a plurality of fields in the electric power system, protective relaying device for example, electric power system fault oscillograph, electric power system fault logout appearance etc., the occasion that needs synchronous high-speed data acquisition and quick real-time to handle.This B sign indicating number to the time module be applied in multiple intelligent substations such as fault message substation need to the time device in, application prospect is very extensive; 7) under the situation of motionless hardware, can easily realize multiplexing functions, effectively avoid function singleness, can't on-line debugging upgrading or the like problem.8) because volume is very little, adopt six layers of printed circuit board, first and third, four, six layer is signals layer, and the second layer is GND, and the 4th layer is the VCC layer.
The high accuracy IRIG-B sign indicating number of the utility model to the time decoding deck; Time error is less than 40 nanoseconds; Function is very powerful; Volume is very little, gathers high speed FPGA and decodes at a high speed effectively, have can realize the IRIG-B coded signal rapid analysis with calculating and raising Information Security, overall dimension is little and the precision advantages of higher.
Description of drawings
Fig. 1 be the utility model high accuracy IRIG-B sign indicating number to the time decoding deck structured flowchart.
Fig. 2 be the utility model high accuracy IRIG-B sign indicating number to the time decoding deck the nucleus module sketch map.
Fig. 3 is three kinds of basic code element sketch mapes in communicating by letter in the utility model.
Fig. 4 for the IRIG-B sign indicating number waveform imported among the embodiment of the utility model and 1PPS firmly to the time pulse per second (PPS) output waveform.
Fig. 5 is the software flow sketch map of the interrupt routine in the utility model.
Below pass through embodiment, and combine accompanying drawing that the utility model is described further.
Embodiment
Referring to Fig. 1, high accuracy IRIG-B sign indicating number to the time decoding deck, adopt 6 layers of printed circuit board, comprise FPGA, E 2PROM, RAM, crystal oscillator, JATG and RESET; Said FPGA, it triggers pin and is set to rising and falling edges and triggers and interrupt, be used for the IRIG-B sign indicating number code signal that receives is carried out the high speed analysis decoding, and with the real-time data memory of decoding to RAM and processing operations; Said E 2PROM, be used to store to IRIG-B sign indicating number coding carry out to the time analyze the program of decoding; Said RAM is used to store the real time data computing that said FPGA decodes; Said crystal oscillator is used to produce the needed high precision clock pulse signal of FPGA; Said JTAG is used for online downloading, and need when producing, not carry out programming to chip and then welds.Said RESET is used for restarting and resetting of decoding deck.
Described high accuracy IRIG-B sign indicating number to the time decoding deck also comprise signal input module and data communication module; Said signal input module comprises that B coded signal lightning protection circuit, light are at a distance from circuit, B coded signal modulate circuit, A/D modular converter and A/D control loop, GPIO input circuit; Said B coded signal lightning protection circuit, light are used for the abnormal signal of preliminary treatment B sign indicating number and convert abnormal signal into normal signal at a distance from circuit, B coded signal modulate circuit, give FPGA with normal signal then and handle; A/D modular converter and A/D control loop are used to gather 12 road 16bit analogue datas; The GPIO input circuit is used to handle the switching value input signal; Said data communication module comprise RS232 soft to the time signaling interface and 1PPS firmly to the time signaling interface, be used for FPGA is decoded the B coded signal and sends in real time.
Said data communication module also comprises LVDS interface, SPI interface, TTL interface and GPIO interface.LVDS is a Low-Voltage Differential Signaling Low Voltage Differential Signal; SPI is a Serial Peripheral Interface Serial Peripheral Interface; TTL is the communication of TTL logic level signal; GPIO is the general input/output interface of General Purpose Input Output, more than all can carry out communication or cascade as required to external world.
As shown in Figure 1, the high accuracy IRIG-B sign indicating number of the utility model to the time decoding deck form by I signal input module, digital analogue signal processing module, data communication module three parts.
Signal input module: comprise that B coded signal lightning protection circuit, light are at a distance from circuit, B coded signal modulate circuit, A/D modular converter and A/D control loop, GPIO input circuit; Wherein: B coded signal lightning protection circuit, light are given FPGA with normal signal and are handled at a distance from circuit, some abnormal signal of B coded signal modulate circuit preliminary treatment B sign indicating number; A/D modular converter and A/D control loop can be gathered 12 road 16bit analogue datas, are used for the function expansion and use, and can not weld when not required, do not influence decoding function; The GPIO input circuit can be handled some switching value input signals, also is used for the function expansion and uses.
Digital analogue signal processing module: comprise FPGA, E 2PROM, RAM, crystal oscillator, JTAG, RESET; What FPGA adopted is the BGA encapsulation, it since the powerful performance of this FPGA can easily realize the B sign indicating number to the time analyze the 1PPS precision that it produced very high (less than 40 nanoseconds); E 2PROM is used for storing user data and some parameter usefulness, but power down is preserved.Crystal oscillator is a 25M high accuracy specialty crystal oscillator, and JTAG is used for the online upgrading program and uses.
Data communication module: comprise RS232 soft to the time signal, 1PPS firmly to the time signal and LVDS, SPI, TTL, GPIO export subsequent use communication module; RS232 soft to the time signal, 1PPS firmly to the time signal be mainly used in FPGA and decode B coded signal and sending in real time, subsequent use communication module uses when doing function expansion or cascade.
High accuracy IRIG-B sign indicating number to the time decoding deck function, the course of work and principle be (referring to Fig. 2 and Fig. 5):
1. the thunderbolt instant high-voltage is filtered and shed to input original I RIG-B sign indicating number level signal through lightning protection circuit,, prevents to scurry into nucleus module;
2. the level signal of filter instant high-voltage is passed through light again at a distance from circuit, and the filtering noise signal is from the improper level signal of hardware circuit interception;
3. the normal level signal directly arrives the FPGA pin, and whether its first preliminary treatment has invalid data, as being that the mistake star can reported to the police and point out to invalid data for a long time;
4. effective IRIG-B code data of coming of processing collected, to the time modular design in, become the corresponding pin design of FPGA rising and falling edges to trigger and interrupt, start inner 16 digit counters of FPGA simultaneously, be set to 100 microseconds from adding once.Trigger the value of reading 16 digit counters when interrupting at rising edge and trailing edge respectively, both differences are pulse duration.The IRIG sign indicating number has four kinds of parallel two system timing code forms and six kinds of serial two system timing code forms, and wherein the most frequently used is IRIG-B sign indicating number form.Wherein with one second once frequency send comprise day, the time, branch, second etc. temporal information; The IRIG-B coded signal is the time string sign indicating number of per second one frame; Its basic code element is " 0 ", " 1 ", " P " (referring to Fig. 3); Each code element takies 10 milliseconds time, and a frame string sign indicating number contains 100 code elements.Code element " 0 ", " 1 " corresponding pulse duration are 2 milliseconds, 5 milliseconds.
5. analyze 0 yard through FPGA then, 1 yard with the P sign indicating number, and then translate successively second, branch, the time, day signal message, solve clock data through the FPGA computing in real time.And through Transistor-Transistor Logic level soft to the time signal send, also to solve simultaneously 1PPS firmly to the time signal.Referring to Fig. 4, above waveform be input B sign indicating number, below waveform for output firmly to the time pps pulse per second signal;
6. owing to power system automation apparatus continuous operation in the forceful electric power magnetic environment, so the interference ratio that receives is more serious.Therefore, except on hardware, taking measures such as photoelectricity isolation and lightning protection, on software, also increased following criterion:
(1) if the code element of checking out is not " 0 ", " 1 ", " P ", think that then device is interfered, all recognition data of front are invalid, wait for the extraction of secondary data down.
(2) when for the first time to the time after, internal clocking obtains change, when occurring two P code elements once more, is detected by internal clocking, error should be in acceptable time, otherwise think to the time make mistakes, wait for next time to the time.The software flow of interrupt routine is shown in figure four.
8. if lose star for a long time, soft to the time signal with output alarm signal, if decode successfully, soft to the time interface output current time, and output in real time firmly to the time 1PPS signal.
9. function expansion:
A. AD gathers analog signal if desired; Can nurse one's health analog voltage amount in the analog interface input; And be converted into actual voltage value through FPGA; If current signal can also be realized gathering indirectly not influencing main decoding function by current value through FPGA conversion in real time through adding accurate sampling resistor.
The b.GPIO input and output can easily realize opening collection and the control into the amount of leaving..LVDS, SPI, TTL communication interface are optional function.

Claims (3)

  1. High accuracy IRIG-B sign indicating number to the time decoding deck, adopt 6 layers of printed circuit board, it is characterized in that, comprise FPGA, E 2PROM, RAM, crystal oscillator, JATG and RESET;
    Said FPGA, it triggers pin and is set to rising and falling edges and triggers and interrupt, be used for the IRIG-B sign indicating number code signal that receives is carried out the high speed analysis decoding, and with the real-time data memory of decoding to RAM and processing operations;
    Said E 2PROM, be used to store to IRIG-B sign indicating number coding carry out to the time analyze the program of decoding;
    Said RAM is used to store the real time data computing that said FPGA decodes;
    Said crystal oscillator is used to produce the needed high precision clock pulse signal of FPGA;
    Said JTAG is used for online downloading, and need when producing, not carry out programming to chip and then welds;
    Said RESET is used for restarting and resetting of decoding deck.
  2. 2. high accuracy IRIG-B sign indicating number according to claim 1 to the time decoding deck, it is characterized in that, also comprise signal input module and data communication module;
    Said signal input module comprises that B coded signal lightning protection circuit, A/D modular converter and A/D control loop, light are at a distance from circuit, B coded signal modulate circuit and GPIO input circuit; Said B coded signal lightning protection circuit, light are used for the abnormal signal of preliminary treatment B sign indicating number and convert abnormal signal into normal signal at a distance from circuit, B coded signal modulate circuit, give FPGA with normal signal then and handle; A/D modular converter and A/D control loop are used to gather 12 road 16bit analogue datas; The GPIO input circuit is used to handle the switching value input signal;
    Said data communication module comprise RS232 soft to the time signaling interface and 1PPS firmly to the time signaling interface, be used for FPGA is decoded the B coded signal and sends in real time.
  3. 3. high accuracy IRIG-B sign indicating number according to claim 2 to the time decoding deck, it is characterized in that said data communication module also comprises LVDS interface, SPI interface, TTL interface and GPIO interface.
CN2012201438378U 2012-04-08 2012-04-08 High-precision IRIG-B code time setting decoding plate Expired - Lifetime CN202535341U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2012201438378U CN202535341U (en) 2012-04-08 2012-04-08 High-precision IRIG-B code time setting decoding plate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2012201438378U CN202535341U (en) 2012-04-08 2012-04-08 High-precision IRIG-B code time setting decoding plate

Publications (1)

Publication Number Publication Date
CN202535341U true CN202535341U (en) 2012-11-14

Family

ID=47136494

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2012201438378U Expired - Lifetime CN202535341U (en) 2012-04-08 2012-04-08 High-precision IRIG-B code time setting decoding plate

Country Status (1)

Country Link
CN (1) CN202535341U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102624391A (en) * 2012-04-08 2012-08-01 安徽继远电网技术有限责任公司 High-precision IRIG-B code timing and decoding board
CN103913615A (en) * 2014-03-21 2014-07-09 中国科学院长春光学精密机械与物理研究所 IRIG-B code alternating-current code distortion monitoring displaying system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102624391A (en) * 2012-04-08 2012-08-01 安徽继远电网技术有限责任公司 High-precision IRIG-B code timing and decoding board
CN103913615A (en) * 2014-03-21 2014-07-09 中国科学院长春光学精密机械与物理研究所 IRIG-B code alternating-current code distortion monitoring displaying system

Similar Documents

Publication Publication Date Title
CN204270025U (en) There is the clock system of IRIG-B time adjustment function
CN102401871B (en) Failure message integrated device based on FPGA and ARM hardware platform
CN201742158U (en) Online monitoring device for power transformer
CN102346670B (en) Intelligent sorting system for graphic logic configuration tool module in transformer substation
CN101738931A (en) IRIG-B (Inter-Range Instrumentation Group-B) code time hack device and time hack method thereof
CN105720684B (en) A kind of Microcomputer Protection method and its system based on FPGA
CN104062617B (en) Combining unit meter characteristic filed detection system and method thereof
CN201828585U (en) Portable transformer substation synchronous time ticking and SOE signal generator
CN202217149U (en) High-precision electric time synchronizer
CN105403751A (en) Power grid state monitoring device based on Beidou
CN202535341U (en) High-precision IRIG-B code time setting decoding plate
CN202837423U (en) Wireless GPRS wind power power grid electric energy quality detection device based on DSP and ARM
CN205583839U (en) Computer integrated protection measurement and control device of transformer substation
CN102624391A (en) High-precision IRIG-B code timing and decoding board
CN104991209A (en) Optical digital relay protection testing instrument detection method
CN205608152U (en) Parameter acquisition circuit that three -phase asynchronous motor used
CN105388780B (en) A kind of IRIG-B000 code simulator
CN107329096B (en) A kind of power supply signal acquisition feature extraction device based on ARM framework
CN203561840U (en) Transformer station GPS time-setting IRIG-B decoder
CN205450107U (en) Radio communication&#39;s electricity inspection terminal
CN204992532U (en) Embedded computer arc light protection device
CN206339640U (en) A kind of harmonic measure synchronization correction device based on IRIG B
CN202837448U (en) Low-voltage fault oscillograph
CN205404677U (en) Electricity inspection terminal with real -time clock
CN202903839U (en) Intelligent electric energy meter

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term

Granted publication date: 20121114

CX01 Expiry of patent term