CN1988157B - 门阵列 - Google Patents
门阵列 Download PDFInfo
- Publication number
- CN1988157B CN1988157B CN2006101468599A CN200610146859A CN1988157B CN 1988157 B CN1988157 B CN 1988157B CN 2006101468599 A CN2006101468599 A CN 2006101468599A CN 200610146859 A CN200610146859 A CN 200610146859A CN 1988157 B CN1988157 B CN 1988157B
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- CN
- China
- Prior art keywords
- mentioned
- terminal portion
- grid
- gate terminal
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 64
- 239000002184 metal Substances 0.000 claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 230000004888 barrier function Effects 0.000 claims description 10
- 230000005540 biological transmission Effects 0.000 description 7
- 230000008901 benefit Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 239000004576 sand Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
- H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Networks & Wireless Communication (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
Description
Claims (5)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005368388 | 2005-12-21 | ||
JP2005-368388 | 2005-12-21 | ||
JP2005368388A JP2007173474A (ja) | 2005-12-21 | 2005-12-21 | ゲートアレイ |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1988157A CN1988157A (zh) | 2007-06-27 |
CN1988157B true CN1988157B (zh) | 2010-05-19 |
Family
ID=38172447
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2006101468599A Expired - Fee Related CN1988157B (zh) | 2005-12-21 | 2006-11-27 | 门阵列 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7875909B2 (zh) |
JP (1) | JP2007173474A (zh) |
KR (1) | KR101318220B1 (zh) |
CN (1) | CN1988157B (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7956421B2 (en) * | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
JP2012222151A (ja) | 2011-04-08 | 2012-11-12 | Panasonic Corp | 半導体集積回路装置 |
JP3179749U (ja) * | 2012-09-05 | 2012-11-15 | ラディウス株式会社 | 携帯用電子機器の保護フレーム |
WO2020261525A1 (ja) * | 2019-06-28 | 2020-12-30 | 日本電気株式会社 | レーダ装置、イメージング方法およびイメージングプログラム |
KR20220124767A (ko) | 2021-02-05 | 2022-09-14 | 창신 메모리 테크놀로지즈 아이엔씨 | 표준 셀 레이아웃 템플릿 및 반도체 구조물 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1519937A (zh) * | 2003-02-07 | 2004-08-11 | ��ʽ���������Ƽ� | 半导体器件 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61295642A (ja) * | 1985-06-24 | 1986-12-26 | Mitsubishi Electric Corp | 半導体集積回路装置 |
JPS6433561A (en) | 1987-07-29 | 1989-02-03 | Konishiroku Photo Ind | Electrostatic latent image developer |
US5591995A (en) * | 1994-05-10 | 1997-01-07 | Texas Instruments, Incorporated | Base cell for BiCMOS and CMOS gate arrays |
JPH0997885A (ja) * | 1995-09-28 | 1997-04-08 | Denso Corp | ゲートアレイ |
US5760428A (en) * | 1996-01-25 | 1998-06-02 | Lsi Logic Corporation | Variable width low profile gate array input/output architecture |
JPH10335613A (ja) | 1997-05-27 | 1998-12-18 | Mitsubishi Electric Corp | 半導体集積回路装置 |
US20060097339A1 (en) * | 2004-11-10 | 2006-05-11 | Sullivan Thomas J | Integrated circuits including auxiliary resources |
-
2005
- 2005-12-21 JP JP2005368388A patent/JP2007173474A/ja active Pending
-
2006
- 2006-11-17 US US11/600,829 patent/US7875909B2/en not_active Expired - Fee Related
- 2006-11-22 KR KR1020060115735A patent/KR101318220B1/ko active IP Right Grant
- 2006-11-27 CN CN2006101468599A patent/CN1988157B/zh not_active Expired - Fee Related
-
2010
- 2010-12-10 US US12/964,796 patent/US8178904B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1519937A (zh) * | 2003-02-07 | 2004-08-11 | ��ʽ���������Ƽ� | 半导体器件 |
Non-Patent Citations (1)
Title |
---|
JP特开平10-335613A 1998.12.18 |
Also Published As
Publication number | Publication date |
---|---|
US7875909B2 (en) | 2011-01-25 |
US20070138510A1 (en) | 2007-06-21 |
KR20070067603A (ko) | 2007-06-28 |
JP2007173474A (ja) | 2007-07-05 |
US8178904B2 (en) | 2012-05-15 |
KR101318220B1 (ko) | 2013-10-15 |
CN1988157A (zh) | 2007-06-27 |
US20110073916A1 (en) | 2011-03-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: OKI SEMICONDUCTOR CO., LTD. Free format text: FORMER OWNER: OKI ELECTRIC INDUSTRY CO., LTD. Effective date: 20131127 |
|
C41 | Transfer of patent application or patent right or utility model | ||
C56 | Change in the name or address of the patentee | ||
CP03 | Change of name, title or address |
Address after: Kanagawa Patentee after: LAPIS SEMICONDUCTOR Co.,Ltd. Address before: Tokyo, Japan Patentee before: OKI Semiconductor Corp. |
|
TR01 | Transfer of patent right |
Effective date of registration: 20131127 Address after: Tokyo, Japan Patentee after: OKI Semiconductor Corp. Address before: Tokyo, Japan Patentee before: Oki Electric Industry Co.,Ltd. |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100519 Termination date: 20161127 |
|
CF01 | Termination of patent right due to non-payment of annual fee |