CN1953020A - 显示装置 - Google Patents
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- CN1953020A CN1953020A CNA2006101357702A CN200610135770A CN1953020A CN 1953020 A CN1953020 A CN 1953020A CN A2006101357702 A CNA2006101357702 A CN A2006101357702A CN 200610135770 A CN200610135770 A CN 200610135770A CN 1953020 A CN1953020 A CN 1953020A
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- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Abstract
本发明提供一种显示装置,将电容设定线配置于像素的上端部,将发光设定线配置于像素的下端部,并将栅极线配置于两者的正中间。于栅极线与电容设定线之间,配置选择晶体管、电位控制晶体管及电容,于栅极线与发光设定线之间,配置短路晶体管、驱动晶体管及驱动控制晶体管。通过如此的配置,可以达到配线的拉引以及接触点之有效率的配置,使开口率相对较高。
Description
技术领域
[0001]本发明涉及一种包含发光组件的显示装置,尤其是涉及显示装置的布局(layout)。
背景技术
[0002]以往,采用有机电致发光(EL)组件的有机电致发光(EL)面板为人所知,其开发亦积极进行中。在该有机EL面板中,将有机EL组件配置为矩阵状,并分别控制该有机EL组件的发光,借此而进行显示。尤其是在主动矩阵型的有机EL面板中,于每个像素中具有显示控制用的TFT(薄膜晶体管),并可以通过此TFT的动作控制而控制每个像素的发光,因此可以进行极为精细的显示。
[0003]图12显示主动矩阵型的有机EL面板的像素电路的一例。供给有表示像素亮度的数据电压的数据线DL,经过栅极连接于栅极线GL的n沟道的选择TFT10,而与驱动TFT12的栅极连接。此外,于驱动TFT12的栅极上,连接有另一端连接于电容线SC的保持电容14的一端,以保持驱动TFT12的栅极电压。
[0004]驱动TFT12的源极与EL电源线连接,漏极与有机EL组件16的阳极连接,有机EL组件16的阴极则与阴极电源连接。
[0005]这样的像素电路被配置成矩阵状,并以预定的时序使每一条水平线都设置之栅极线成为H,使该行的选择TFT10成为导通(ON)状态。在此状态下,由于数据电压依序供给至数据线,因此该数据电压供给至保持电容14而保持,即使在栅极线成为L时,亦可以保持那时之电压。
[0006]此外,驱动TFT12依照该保持电容14所保持的电压而动作,使对应的驱动电流从EL电源经过有机EL组件16而流往阴极电源,有机EL组件16因而依照该数据电压而发光。
[0007]之后,依序使栅极线成为H,而依序将输入的视频(video)信号作为数据电压供给至对应的像素,借此使配置成矩阵状的有机EL组件16依照该数据电压而发光,而进行视频信号的显示。
[0008]在此,在这样的像素电路中,如果配置成矩阵状的像素电路的驱动TFT的阈值电压参差不齐,那么亮度亦会不均匀而导致显示质量的降低。此外,关于构成显示面板全体的像素电路的TFT,由于不易维持其特性为一致,因此也难以防止其导通(ON)与不导通(OFF)的阈值发生参差不齐的情形。
[0009]因此,关于用于防止对TFT的阈值变动影响的电路,有例如日本特表2002-514320号公报以及日本特开2005-128521号公报等中所公开的方案。
[0011]然而,在这些方案中,必须具备2条以上用于进行各个像素电路的控制的控制线。亦即,在上述图5的电路中,只需具备栅极线来作为除了于垂直方向延伸的数据线、电源线之外的控制线,但是于日本特表2002-514320号公报以及日本特开2005-128521号公报中,除了栅极线之外还须具备至少2条控制线。
[0012]因此,不仅控制线,控制线与晶体管之间的连接线等也增加,而有开口率下降的问题。
[0013]因此,有效率地配置配线等而维持相对较高的开口率的方案,为人所期盼。
发明内容
[0016]在本发明中,将与栅极线平行而配置的栅极线以外的2条控制线,包夹栅极线而配置。借此,可以有效率地配置配线并维持相对较高的开口率。此外,优选的是在不存在像素电极的栅极线与控制线之间的空间中,至少配置1个与电源线的接触点(contact)。
附图说明
[0060]图1是实施例所涉及的像素电路的构成图。
图2是动作说明图。
图3是放电程序说明图。
图4是重设程序说明图。
图5是电位固定程序说明图。
图6是发光程序说明图。
图7是从重设至电位固定程序电位变化的状态说明图。
图8是面板的全体构成图。
图9是数据设定的时序例图。
图10是数据设定的其它时序例图。
图11是实施例所涉及的像素电路的布局图。
图12是以往的像素电路的一例图。
主要组件符号说明
10选择TFT 12驱动TFT
14保持电容 16、EL 有机EL组件
112、120、132半导体层 118金属配线
Cp寄生电容 Cs电容
CS电容设定线 CV阴极电源
DL数据线 ENB使能信号、使能线
ES发光设定线 GL栅极线
HSR水平开关电路 PVdd电源线
SC电容电极 T1选择晶体管
T1g、T2g、T3g、T4g、T5g栅极电极
T2电位控制晶体管 T3短路晶体管
T4驱动晶体管 T5驱动控制晶体管
Vg栅极电压 Vsig数据电压
VSR垂直开关电路
具体实施方式
[0017]以下根据附图来说明本发明的实施形态。
[0018]图1显示实施例所涉及的像素电路的构成。数据线DL在垂直方向上延伸,将关于像素的显示亮度的数据信号(数据电压Vsig)供给至像素电路。数据线DL对于1列的像素设置1条,并对在垂直方向的像素依序供给各像素的数据电压Vsig。
[0019]在此数据线DL上,连接有n沟道的选择晶体管T1的漏极,此选择晶体管T1的源极与电容Cs的一端连接。选择晶体管T1的栅极与在水平方向延伸的栅极线GL连接。
[0020]此外,针对1行的像素设置有电容设定线CS,在此电容设定线CS上,连接有p沟道的电位控制晶体管T2的栅极。此电容设定线CS,于栅极线GL成为H电平的稍微之前成为L电平,于栅极线GL返回L电平之后返回H电平。因此,基本上于选择晶体管T1为导通(ON)时,电位控制晶体管T2为不导通(OFF),选择晶体管T1为不导通时,电位控制晶体管T2为导通。电位控制晶体管T2的源极与电源线PVdd连接,漏极与电容Cs及选择晶体管T1的源极连接。电源线PVdd亦于垂直方向上延伸,将电源电压PVdd供给至垂直方向的各个像素。
[0021]电容Cs的另一端与p沟道的驱动晶体管T4的栅极连接。驱动晶体管T4的源极与电源线PVdd连接,漏极与n沟道的驱动控制晶体管T5的漏极连接。驱动控制晶体管T5的源极与有机EL组件EL的阳极连接,栅极则与在水平方向延伸的发光设定线ES连接。此外,有机EL组件EL的阴极与低电压的阴极电源CV连接。
[0022]此外,驱动晶体管T4的栅极与n沟道的短路晶体管T3的漏极连接,此短路晶体管T3的源极与驱动晶体管T4的漏极连接,栅极与栅极线GL连接。
[0023]如此,在本实施例中,在垂直方向上配置有数据线DL及电源线PVdd这2条线,在水平方向上,除了栅极线GL之外,配置有电容设定线CS及发光设定线ES这2条控制线。
[0024]接下来说明该像素电路的动作。
[0025]如图2所示,该像素电路依据栅极线GL、电容设定线CS、发光设定线ES的状态(H电平、L电平),而具有(i)放电(GL=H电平、CS=L电平、ES=H电平),(ii)重设(GL=H电平、CS=L电平、ES=L电平),(iii)电位固定(GL=L电平、CS=H电平、ES=L电平),(iv)发光(GL=L电平、CS=H电平、ES=H电平)的4种状态,并重复进行此这4种状态。亦即,在使数据线DL的数据成为有效的状态下,进行(i)放电,之后通过(ii)重设而决定电容Cs的充电电压,之后于(iii)中将栅极电压Vg固定,之后(iv)以依据固定后的栅极电压的驱动电流使有机EL组件EL发光。虽然电容设定线CS如上述,于栅极线GL成为H电平时成为L电平,于栅极线GL成为L电平时成为H电平,但可以使电容设定线CS于栅极线GL成为H电平之前成为L电平,于栅极线GL返回L电平之后成为H电平,借此防止选择晶体管T1及电位控制晶体管T2同时导通。
[0026]此外,如图所示,数据线DL的数据于(i)放电程序之前成为有效,于(iii)固定程序之后成为无效。因此,从(i)放电程序至(iii)固定程序为止,在数据线中设定有效的数据。
[0027]以下针对各个状态进行说明。在图3至图6中,以虚线来表示不导通的晶体管。
[0028]放电(GL=H电平、CS=L电平、ES=H电平)
首先,于数据电压Vsig供给至数据线DL的状态下,使栅极线GL、发光设定线ES两者成为H电平(高电平),使电容设定线CS成为L电平。借此,使选择晶体管T1、驱动控制晶体管T5、短路晶体管T3成为导通,使电位控制晶体管T2成为不导通。因此,如图3所示,于电容Cs的选择晶体管T1侧的电压Vn=Vsig的状态下,来自于电源线PVdd的电流经过驱动晶体管T4、驱动控制晶体管T5、有机EL组件EL而流往阴极电源CV,借此使驱动晶体管T4的栅极中所保持的电荷被拉引出。因此,驱动晶体管T4的栅极电压Vg成为预定的低电压。
[0029](ii)重设(GL=H电平、CS=L电平、ES=L电平)
从上述的放电状态,将发光设定线ES变更为L电平(低电平)。借此,如图4所示,驱动控制晶体管T5成为不导通,使驱动晶体管T4的栅极电压Vg被重设为Vg=Vg0=PVdd-|Vtp|。在此,此Vtp为驱动晶体管T4的阈值电压。亦即,由于驱动晶体管T4于其源极与电源PVdd连接的状态下,通过短路晶体管T3而使其栅极漏极之间成为短路,因此其栅极电压被设定为仅较电源PVdd降低驱动晶体管T4的阈值电压|Vtp|的电压,而成为不导通。此时,电容Cs的选择晶体管T1侧的电位Vn=Vsig,|Vsig-(PVdd-|Vtp|)|的电压充电于电容Cs中。
[0030](iii)电位固定(GL=L电平、CS=H电平、ES=L电平)
接着,使栅极线GL成为L电平而使选择晶体管T1、短路晶体管T3成为不导通,之后使电容设定线CS成为H电平而使电位控制晶体管T2成为导通。借此,如图5所示,驱动晶体管T4的栅极从漏极分离。之后,由于电位控制晶体管T2导通,因此Vn=PVdd。因此,驱动晶体管T4的栅极电压Vg随着Vn的变化而浮动(shift)。此外,由于在驱动晶体管T4的栅极与源极之间存在有寄生电容Cp,因此栅极电压Vg会受到此Cp的影响。
[0031](iv)发光(GL=L电平、CS=H电平、ES=H电平)
接着,使发光设定线ES成为H电平,借此,如图6所示,驱动控制晶体管T5导通,因此来自驱动晶体管T4的驱动电流流通过有机EL组件EL。此时的驱动电流成为由驱动晶体管T4的栅极电压所决定的驱动晶体管T4的漏极电流,但是该漏极电流与驱动晶体管T4的阈值电压Vtp并无关系,因此可以抑制伴随着阈值电压的变动的发光量的变动。
[0032]接下来根据图7来说明此情形。
[0033]如上述般,于(ii)重设后,如图中的○所示般,Vn(=Vsig)为Vsig(max)至Vsig(min)之间的值,Vg为从PVdd减去驱动晶体管T4的阈值电压Vtp后的电压Vg0。亦即,Vg=Vg0=PVdd+Vtp(Vtp<0),Vn=Vsig。
[0034]之后,一旦进入(iii)的电位固定,则Vn从Vsig改变至PVdd,因此其变化量ΔVg,若考虑到Cs、Cp的电容,则可以表示为ΔVg=Cs(PVdd-Vsig)/(Cs+Cp)。
[0035]因此,如图中的●所示,Vn、Vg各成为Vn=PVdd,Vg=Vtp+ΔVg=PVdd+Vtp+Cs(PVdd-Vsig)/(Cs+Cp)。
[0036]在此,由于Vgs=Vg-PVdd,因此Vgs=Vtp+Cs(PVdd-Vsig)/(Cs+Cp)。
[0037]另一方面,漏极电流I以I=(1/2)β(Vgs-Vtp)2表示,因此通过代入上式,可以由下列式子表示漏极电流I。
I=(1/2)β{Vtp+Cs(PVdd-Vsig)/(Cs+Cp)-Vtp}2
=(1/2)β{Cs(PVdd-Vsig)/(Cs+Cp)}2
=(1/2)βα(Vsig-PVdd)2
在此,α={Cs/(Cs+Cp)}2,β为驱动晶体管T4的放大率,β=μεGw/Gl,μ为载子移动率,ε为介电常数,Gw为栅极宽度,Gl为栅极长度。
[0038]如此,于漏极电流I的式子中未包含Vtp,而与Vsig-PVdd的2次方成比例。因此可以排除驱动晶体管T4的阈值电压变动的影响,而达成依据数据电压Vsig发光。
[0039]在上述说明中,仅针对1个像素的动作进行说明。实际上,显示面板中将像素配置为矩阵状,并对各个像素供给依据对应的亮度信号的数据电压Vsig而使各个有机EL组件发光。亦即,如图8所示,于显示面板中设置有水平开关电路HSR及垂直开关电路VSR,并通过这些开关电路的输出来控制数据线DL、栅极线GL及其它发光设定线ES等的状态。尤其是于水平方向的各个像素对应有1条栅极线GL,且该栅极线GL由垂直开关电路VSR以一次一条的方式依序使之活化。接着,于1条栅极线GL活化的1个水平期间中,通过水平开关电路HSR将数据电压以点的顺序依序供给至所有的数据线DL,而使数据写入1条水平线份的像素电路。之后,于各个像素电路中,于1个垂直期间之后,依据写入的数据电压而发光。
[0040]接下来根据图9,说明对1条水平线内的各个像素的数据写入步骤。
[0041]首先,于表示1个水平期间的开始的使能信号ENB成为L电平之后,以点的顺序将数据电压Vsig写入所有的数据线DL。亦即,于数据线DL上连接有电容等,并通过设定电压信号,使该数据电压Vsig保持于数据线DL中。因此,可以将各列像素的数据电压Vsig依序设定于对应的数据线中,借此将数据电压Vsig设定于所有的数据线DL。
[0042]之后,于此数据的设定结束阶段,使Hout成为H电平并使栅极线GL成为H电平而使之活化,进行如上述之1个水平方向各个像素动作,进行各个像素的数据写入而发光。
[0043]如此,可以依序将一般的视频信号(数据电压Vsig)写入数据线DL,并将此设定于像素电路而进行发光。
[0044]接下来根据图10来说明其它的方式。于此例中,于使能线ENB为L电平的期间中,使发光设定线ES成为L电平,于使能线ENB上升为H电平时,使栅极线GL成为H电平(活化)。于此状态下,依序将数据电压Vsig设定于数据线DL。此外,于将数据电压Vsig设定于所有的数据线DL时,使发光设定线ES成为H电平而进行上述放电,之后使发光设定线ES返回L电平。栅极线GL与使能线ENB的下降同步而返回L电平,并于使能线ENB成为L电平时使使能线ENB返回H电平。借此而进行与上述例子相同的动作。此外,于栅极线GL为H电平的期间中,电容设定线CS为L电平,且较栅极线GL的上升略微提早成为L电平,较栅极线GL的下降略为延迟返回H电平。
[0045]图11显示利用图1所示的像素电路的显示面板的布局。
[0046]首先,电容设定线CS沿着各行像素的上端部而延伸。在图中的像素中,数据线DL于列方向上于各个像素的右端部分延伸。此外,于各数据线DL的左侧边上,电源线PVdd以几乎平行的方式于列方向延伸。于图中所示的像素的下段的像素中,于各个像素的左端部分配置有数据线DL及电源线PVdd。
[0047]此外,于像素的中央稍微上部,栅极线GL横贯像素而延伸。此外,发光设定线ES沿着各个像素的下端部而配置。
[0048]于栅极线GL接近像素的右端的部分,设置有向上方突出的突出部分,此是成为n沟道的选择晶体管T1的栅极电极T1g。亦即,于此栅极电极T1g的厚度方向的下方,隔着栅极绝缘膜而设置有半导体层112,此半导体层112沿着栅极线GL而延伸,且其右端通过接触点(contact)而与数据线DL连接。
[0049]此外,半导体层112于栅极电极T1g的下方往左方向延伸,此例中,朝电容设定线CS的方向扩展成大致方形。此外,于此扩展成方形部分,隔着栅极绝缘膜而形成有与栅极电极为同一层的电容电极SC,此电容电极SC隔着栅极绝缘膜而与半导体层112对应部分形成为电容Cs。
[0050]此外,构成电容Cs的半导体层112的一部分,沿着电容设定线CS而往右侧延伸,并通过接触点(contact)而与电源线PVdd连接。此外,从电容设定线CS突出的突出部分,位于半导体层112的电容Cs侧与电源线PVdd侧的中间部分的厚度方向上方,此突出部分隔着栅极绝缘膜而位于半导体层112的厚度方向上方,其成为n沟道的电位控制晶体管T2。
[0051]于像素中央部的栅极线GL的正上方的电容Cs,设置有接触点(contact),并通过此接触点而连接有金属配线118,此金属配线118横跨栅极线GL而到达栅极线GL的下方,因此可以通过此接触点而与半导体层120连接。
[0052]半导体层120首先往右方向延伸,接着沿着数据线DL及电源线PVdd之间而往下方延伸,于中间部分设置有往左侧延伸的分支部,并且于发光设定线ES的前方往左方向弯曲。于此半导体层120的沿着栅极线GL往右方向延伸部分的厚度方向上方,有从栅极线GL延伸的突出部分隔着栅极绝缘膜而设置,其成为n沟道型短路晶体管T3的栅极电极T3g。亦即,此部分构成用于连接驱动晶体管T4的栅极与源极的短路晶体管T3。
[0053]在与短路晶体管T3连接的接触点的下方,金属配线118通过接触点而连接于与栅极线GL同一层的栅极配线,此栅极配线与电源线PVdd平行而延伸,在此例中成为p沟道的驱动晶体管T4的栅极电极T4g。亦即,于此栅极电极T4g的厚度方向下方,隔着栅极绝缘膜而设置有在上下方向延伸的半导体层132,此半导体层132的一端(漏极:图中为上侧)通过接触点而与电源线PVdd连接。半导体层132下侧,往左侧弯曲后通过接触点而与金属配线连接,此金属配线通过接触点而与上述半导体层120的从中间部往左侧延伸的分支部连接。
[0054]此外,半导体层120的下端部沿着发光设定线ES而往左侧延伸,于此部分的厚度方向上方,发光设定线ES的一部分隔着栅极绝缘膜而突出于其上,形成n沟道的驱动控制晶体管T5的栅极电极T5g,因而形成驱动控制晶体管T5。于半导体层120的下端左侧的端部,通过接触点而连接有像素电极。此外,于此像素电极的厚度方向上方,隔着有机发光层而形成有全像素共通的阴极,因而形成有机EL组件。
[0055]就厚度方向来看,于玻璃等透明基板上形成TFT,再在上面形成各像素的透明电极(阳极),再在上面隔着有机发光层而形成全像素共通的铝等的阴极。TFT首先于玻璃基板上形成缓冲层,再在上面的预定位置形成半导体层112、120、132。然后覆盖半导体层而形成栅极绝缘膜,再在上面以钼或铬等形成栅极线GL、电容电极等。然后覆盖该栅极线GL等层而形成层间绝缘膜,再在层间绝缘膜的上层形成电源线PVdd、数据线DL等金属(例如铝)配线等。之后,覆盖该等金属配线而形成丙烯酸树脂等的平面化层,再在该平面化层的上面,构成有ITO(氧化铟锡)、IZO(氧化铟锌)等透明电极(像素电极)。
[0056]如此,根据本实施例中,于像素的上侧配置有电容设定线CS,于像素下侧配置有发光设定线ES,且栅极线GL配置于较电容设定线CS稍微下侧的位置。
[0057]通过这样的配置,可以将电位控制晶体管T2及选择晶体管T1配置于栅极线GL的上侧。尤其是沿着栅极线GL而配置选择晶体管T1,借此可以将栅极线GL的突出部作为选择晶体管T1的栅极电极T1g。另一方面,由于电位控制晶体管T2沿着电容设定线CS而形成,因此亦可以容易地形成电位控制晶体管T2的栅极电极T2g。此外,电位控制晶体管T2的与电源线PVdd的接触点亦位于像素的角落上,形成有效率的配置。此外,可以于电位控制晶体管T2与选择晶体管T1之间的空间中形成电容Cs,因此可以有效利用栅极线GL上侧的空间。
[0058]此外,使短路晶体管T3沿着栅极线GL的下侧而配置,使驱动控制晶体管T5沿着发光设定线ES而形成,因此亦可以容易地形成短路晶体管T3及驱动控制晶体管T5的栅极电极T3g、T5g。再者,短路晶体管T3及驱动控制晶体管T5的连接利用半导体层120,并将此半导体层120配置于电源线PVdd与数据线DL之间的空间的厚度方向下侧,因此可以降低该配线对开口率所造成的影响。此外,使驱动晶体管T4沿着电源线PVdd而配置,因此可以抑制开口率的降低而成为有效率的配置。
[0059]此外,上述图11所示的布局,只要是水平方向的控制线除了栅极线之外还有2条电路,都同样适用。例如亦可以适用于日本特表2002-514320号公报所记载的电路。
Claims (14)
1.一种显示装置,将像素配置成矩阵状的显示装置,其中,
各个像素包含:由来自栅极线的选择信号使之导通与不导通,以控制来自数据线的数据信号的接收的选择晶体管;使依据经过该选择晶体管而接收的数据信号的电流流通的驱动晶体管;及依照流通于该驱动晶体管的电流而发光的发光组件,
所述栅极线沿着各像素行而配置于行方向,
为了控制所述驱动晶体管的动作,除了栅极线之外,还沿着各条像素行而配置两条控制线,
在所述两条控制线之间配置栅极线。
2.根据权利要求1所述的显示装置,其中,所述选择晶体管的控制端与所述栅极线连接,且一端与所述数据线连接,另一端经过电容而与所述驱动晶体管的控制端连接。
3.根据权利要求2所述的显示装置,其中,于所述选择晶体管的另一端及所述电容的连接部、与电源线之间设置有电位控制晶体管,该电位控制晶体管的控制端连接有为所述两条控制线中的一条控制线的电容设定线。
4.根据权利要求3所述的显示装置,其中,所述驱动晶体管的一端与所述电源线连接,另一端经过所述驱动控制晶体管而与所述发光组件连接,所述驱动控制晶体管的控制端连接有为所述两条控制线中的一条控制线的发光设定线。
5.根据权利要求4所述的显示装置,其中,于所述驱动晶体管的另一端及所述驱动控制晶体管的连接部、与所述驱动晶体管的控制端之间设置有短路晶体管,所述短路晶体管的控制端与所述栅极线连接,且所述选择晶体管与所述短路晶体管以相同时序导通与不导通。
6.根据权利要求5所述的显示装置,其中,于所述电容设定线成为非作用电平且所述电位控制晶体管为不导通的状态下,使所述栅极线成为作用电平且使所述选择晶体管与所述短路晶体管成为导通,借此,将依据数据信号的第1电压供给至所述电容的一端,将从所述电源线的电源电压下降所述驱动晶体管的阈值电压份之后的第2电压供给至所述电容的另一端,而将所述第1电压与所述第2电压之差的电压充电至所述电容。
7.根据权利要求6所述的显示装置,其中,于所述栅极线成为作用电平之前,使所述电容设定线成为非作用电平,于所述栅极线成为非作用电平之后,使所述电容设定线成为作用电平,借此防止所述选择晶体管与所述电位控制晶体管同时导通。
8.根据权利要求7所述的显示装置,其中,于所述栅极线成为作用电平之后,所述发光设定线成为非作用电平;于所述栅极线成为非作用电平且所述电容设定线成为作用电平之后,所述发光设定线成为作用电平。
9.根据权利要求1所述的显示装置,其中,将电流供给至所述驱动晶体管的电源线沿着各像素列而配置;
用于与该电源线形成电性连接的一个接触点设置于栅极线与一条控制线之间,另一个接触点则设置于栅极线与另一条控制线之间。
10.根据权利要求5所述的显示装置,其中,所述选择晶体管及所述电位控制晶体管,配置于所述栅极线与所述电容设定线之间;
所述短路晶体管、所述驱动晶体管及所述驱动控制晶体管,配置于所述栅极线与所述发光设定线之间。
11.根据权利要求10所述的显示装置,其中,所述电容及所述电位控制晶体管,配置于所述栅极线与所述电容设定线之间。
12.根据权利要求11所述的显示装置,其中,所述栅极线向一侧突出而形成所述选择晶体管的栅极电极,向另一侧突出而形成所述短路晶体管的栅极电极。
13.根据权利要求12所述的显示装置,其中,形成所述短路晶体管的活性层的半导体层,直接延伸而与所述驱动控制晶体管的活性层连接。
14.根据权利要求13所述的显示装置,其中,所述驱动晶体管及所述驱动控制晶体管,经过金属配线而连接。
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CN102708789A (zh) * | 2011-12-01 | 2012-10-03 | 京东方科技集团股份有限公司 | 像素单元驱动电路和方法、像素单元以及显示装置 |
CN103021332A (zh) * | 2012-12-04 | 2013-04-03 | 彩虹(佛山)平板显示有限公司 | 一种用于显示器的驱动*** |
CN109509431A (zh) * | 2017-09-14 | 2019-03-22 | 京东方科技集团股份有限公司 | 像素电路及其驱动方法、显示装置 |
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KR100795678B1 (ko) | 2008-01-21 |
JP5013697B2 (ja) | 2012-08-29 |
KR20070042878A (ko) | 2007-04-24 |
US8289235B2 (en) | 2012-10-16 |
US20130001569A1 (en) | 2013-01-03 |
US8922467B2 (en) | 2014-12-30 |
US8692749B2 (en) | 2014-04-08 |
CN100530309C (zh) | 2009-08-19 |
TWI344633B (en) | 2011-07-01 |
US20070085782A1 (en) | 2007-04-19 |
US20140061686A1 (en) | 2014-03-06 |
TW200717421A (en) | 2007-05-01 |
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