CN1893007A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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Publication number
CN1893007A
CN1893007A CNA2006101000714A CN200610100071A CN1893007A CN 1893007 A CN1893007 A CN 1893007A CN A2006101000714 A CNA2006101000714 A CN A2006101000714A CN 200610100071 A CN200610100071 A CN 200610100071A CN 1893007 A CN1893007 A CN 1893007A
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Prior art keywords
resin
resin bed
semiconductor device
conductive layer
projection
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CNA2006101000714A
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CN100452337C (zh
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田中秀一
伊东春树
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

本发明的目的在于实现导电层的密接性的提高和迁移的防止。半导体装置的制造方法，包括：(a)在具有电极垫(16)以及钝化膜(18)的半导体基板(10)的上方形成第一树脂层(20b)的工序；(b)固化第一树脂层(20b)的工序；(c)至少在第一树脂层(20)的根基部形成第二树脂层(30a)的工序，该第二树脂层(30a)的上升相比固化后的第一树脂层(20)更平缓；(d)通过固化第二树脂层(30a)，而形成包括第一以及第二树脂层(20、30)的树脂突起(40)的工序；(e)形成与电极垫(16)电连接，且经过树脂突起(40)的上方的导电层(50)的工序。

Description

半导体装置的制造方法
技术领域
本发明涉及半导体装置的制造方法。
背景技术
为了实现电连接的可靠性的提高，开发了将在树脂突起上形成有导电层的树脂的树脂中心突起(core bump)作为外部端子的半导体装置(参照特开平2-272737号公报)。据此，在半导体基板上形成有树脂突起后，从电极垫到树脂突起上形成导电层。一般在形成导电层的工序中，为了除去电极垫上的氧化层，而进行Ar逆溅射。但是，若进行Ar逆溅射，则由此树脂突起的表面的炭化进行，其结果，树脂的绝缘电阻降低，有可能会引起迁移(migration)。另外，上述结构的情况，导电层因为以通过形成立体的形状的树脂突起上的方式而形成，所以要求防止导电层的剥离或断线。
发明内容
本发明的目的在于，实现导电层的密接性的提高以及迁移的防止。
本发明的半导体装置的制造方法，包括：
(a)在具有电极垫以及钝化膜的半导体基板的上方形成第一树脂层的工序；
(b)固化(cure)所述第一树脂层的工序；
(c)至少在所述第一树脂层的根基部形成第二树脂层的工序；
(d)通过固化所述第二树脂层，形成包含所述第一以及第二树脂层并且与固化后的所述第一树脂层相比上升变得更平缓的树脂突起的工序；
(e)形成与所述电极垫电连接，且经过所述树脂突起的上方的导电层的工序。
根据本发明，通过形成第二树脂层，而能够使树脂突起的上升平缓，因此能够实现防止导电层的剥离以及断线，能够实现其密接性的提高。
还有，在本发明中，在特定的A的上方设有B，包括在A上直接设有B的情况，和在A上经由其他构件而设有B的情况。这在以下的发明中相同。
(2)在该半导体装置的制造方法中，也可以
在所述(e)工序中，
在形成所述导电层前，通过Ar气体，从所述电极垫的表面除去氧化膜，并且，使所述树脂突起的表面的炭化进展，
在形成了所述导电层后，将所述导电层作为掩模部分地除去所述树脂突起。
据此，通过Ar气体，使树脂突起的炭化进展，即使形成炭化层(或等离子聚合层)，树脂突起的上升也平缓地形成，因此可以容易地不残留炭化层等地除去树脂突起。特别是，炭化层等虽然容易残存于树脂突起的根基部，但是根据本发明能够容易地除去残留于树脂突起的根基部的炭化层等。
(3)在该半导体装置的制造方法中，也可以
所述第二树脂层的固化前的树脂材料，与所述第一树脂层的固化前的树脂材料相比，相对于所述钝化膜的润湿性更高。
据此，易于平缓地形成树脂突起的上升。
(4)在该半导体装置的制造方法中，也可以
在所述(c)工序中，
在所述第一树脂层的全周上形成所述第二树脂层。
(5)在该半导体装置的制造方法中，也可以
通过涂布于所述半导体基板的上方，然后进行刻蚀，将所述第二树脂层至少形成在所述第一树脂层的根基部。
(6)在该半导体装置的制造方法中，也可以
在所述(c)工序中，
通过液滴吐出法，形成所述第二树脂层。
附图说明
图1是说明本实施方式的半导体装置的制造方法的图。
图2是说明本实施方式的半导体装置的制造方法的图。
图3是说明本实施方式的半导体装置的制造方法的图。
图4是说明本实施方式的半导体装置的制造方法的图。
图5是说明本实施方式的半导体装置的制造方法的图。
图6是说明本实施方式的半导体装置的制造方法的图。
图7是说明本实施方式的半导体装置的制造方法的图。
图8是说明本实施方式的半导体装置的制造方法的图。
图9是说明本实施方式的半导体装置的制造方法的图。
图10是说明本实施方式的半导体装置的制造方法的图。
图11是图10的XI-XI线剖面图。
图12是图10的XII-XII线剖面图。
图13是说明本实施方式的半导体装置的制造方法的图。
图14是表示本实施方式的电子设备的图。
图15是表示本实施方式的电子设备的图。
图16是表示本实施方式的电子设备的图。
图17是说明本实施方式的变形例的半导体装置的制造方法的图。
图中：10-半导体基板；16-电极垫；17-氧化层；18-钝化层；20-第一树脂层；30-第二树脂层；40、42-树脂突起；50-导电层、60-树脂中心突起、100-半导体装置、120-第一树脂层；130-第二树脂层；140-树脂突起。
具体实施方式
以下参照附图说明本发明的实施方式。
图1～图13是说明本实施方式的半导体装置的制造方法的图。
(1)首先，如图1以及图2所示，。准备半导体基板10。半导体基板10是例如半导体晶片(参照图1)。此时，半导体基板10，具有形成半导体芯片的多个的芯片区域12，在各自的芯片区域12内形成有集成电路14。即，将半导体基板10分割成多个半导体芯片时，各个半导体芯片分别具有集成电路14。集成电路14，至少含有晶体管等有源元件。芯片区域12，例如在俯视的情况下为矩形形状(例如长方形)。在各自的芯片区域12中，形成有多个电极垫(例如铝垫)16。多个电极垫16，可以沿芯片区域12相对的2边(例如长边侧的2边)或4边而排列。此时，在各边排列有1列或多列的电极垫16。电极垫16排列于芯片区域12的端部时，集成电路14也可以形成于通过多个电极垫16围住的中央部。或者，电极垫16，也可以形成于在与集成电路14在俯视时重叠的区域中。电极垫16，通过内部配线(未图示)而与集成电路电连接。
在半导体基板10的表面(集成电路14的形成面)，形成有钝化膜(保护膜)18。钝化膜18，由无机系或有机系的任一种形成均可，例如可以通过硅氧化膜、硅氮化膜的至少一层形成。在钝化膜18上，形成有将电极垫16开口的开口部19。通过开口部19，电极垫16的至少一部分(例如仅中央部)露出。还有，在电极垫16上，大多时候形成有氧化层17。氧化层17例如是自然氧化而形成，覆盖电极垫16的表面。
(2)接着，如图3～图6所示，形成第一树脂层20。
第一树脂层20，在半导体基板10上(详细地说在钝化膜18上)，可以形成于在俯视的情况下与电极垫16不同的区域中。第一树脂层20的形成区域没有限定，但是例如可以形成为具有规定的宽度的直线状。此时，可以以沿着半导体基板10的芯片区域12的边界(例如长边方向)而延出(例如平行)的方式形成。
具体地说，首先，如图3所示，通过例如旋涂法将感光性的第一树脂层20a涂布于半导体基板10上。其后，如图4所示，将具有开口部24的掩模22配置于半导体基板10，照射光能26而进行曝光。作为第一树脂层20a，在光能26的照射部分上使用显影液的溶解性降低的负片型时，能够仅在从掩模22的开口部24到露出区域残留树脂。或者，相反，作为第一树脂层20a，在光能26的照射部分上使用显影液的溶解性增加的正片型时，能够仅在通过掩模22覆盖的区域残留树脂。其后，通过进行显影工序，如图5所示，能够将第一树脂层20b以规定形状形成图案。
在此，作为第一树脂层20的树脂材料的一例，可例举出聚酰亚胺树脂、丙烯酸树脂、苯酚树脂、环氧树脂、硅树脂、改性聚酰亚胺树脂等弹性树脂材料。另外，第一树脂层20，可以是作为例如具有苯环以及其缩合的环的有机化合物的芳香族化合物的聚酰亚胺、聚苯并唑、苯并环丁烯或环氧等。
其后，如图6所示，固化第一树脂层20b。详细地说，通过加热第一树脂层20b，使树脂熔融，其后使其硬化收缩。此时的固化条件，可以是使第一树脂层20的硬化收缩结束的条件，也可以是不致于结束而至少使硬化收缩开始的条件。后者的情况，通过后述的再度固化工序，而能够使第一树脂层20的硬化收缩结束。形成图案后的第一树脂层20b由多个平面构成时(例如形成大致长方体时)，通过固化工序，而能够形成表面成为曲面的第一树脂层20。例如，能够使第一树脂层20以剖面形成大致半圆形状的方式形成。此时，第一树脂层20的根基部，以从半导体基板10的上面大致垂直上升的方式形成。
(3)接着，如图7～图9所示，形成第二树脂层30。
第二树脂层30，以最终的树脂突起40与固化后的第一树脂层20相比上升平缓地形成的方式而形成于第一树脂层20的至少根基部。第二树脂层30，最终的固化后的形状与第一树脂层20相比上升平缓即可，可以根据其而适当地调整固化前的涂布形状以及涂布区域。
具体地说，例如，如图7所示，通过例如旋涂法将感光性的第二树脂层30a涂布于半导体基板10上。第二树脂层20a，以覆盖第一树脂层20的方式涂布，例如可以涂布于整个半导体基板10上。其后，由O2等离子32等进行刻蚀处理(灰化处理(ashing)、等离子处理)。如此，如图8所示，可以使第二树脂层30b在第一树脂层20的至少根基部形成。第二树脂层30b，也可以仅在第一树脂层20的根基部形成，也可以以覆盖包括其根基部以及顶头部的全体的方式形成。无论如何形成第二树脂层30b，均以从第一树脂层20的根基部向外侧的钝化膜18上扩大的方式形成。第二树脂层30b，在俯视中可在第一树脂层20的全周形成。
作为变形例，也可以通过液滴吐出法(例如喷墨法)而形成第二树脂层30a。据此，根据喷墨法可知，通过应用实用于喷墨打印机用的技术，能够不浪费地经济地高速设置墨水(树脂材料)。
在此，作为第二树脂层30的树脂材料，能够应用上述的第一树脂层20中的说明内容。例如，固化后的第一以及第二树脂层20、30，可以为相同的树脂。另外，第二树脂层30的固化前(涂布时的第二树脂层30a)的树脂材料可以是与第一树脂层20的固化前(涂布时的第一树脂层20a)的树脂材料相比相对于钝化膜18的润湿性高(粘性低)的材料。由此，能够使第二树脂层30从第一树脂层20的根基部向钝化膜18上平缓地倾斜而形成。还有，树脂材料的润湿性，可以通过调整含有的添加剂等而适当地调整。
其后，如图9所示，固化第二树脂层30b。详细地说，通过加热第二树脂层30b，使树脂熔化，其后使其硬化收缩。在第一树脂层20的硬化收缩没有完了时，通过本工序能够使第一树脂层20的硬化收缩完成。如此，通过固化后的第一以及第二树脂层20、30，而能够形成树脂突起40。
树脂突起40的剖面，形成大致半圆形状，具有上升平缓的倾斜面而形成。树脂突起40的上升角度(上升附近的倾斜面的切线和钝化膜18的表面所成的角度(称为接触角))θ，至少为θ＜90°(最佳为θ0°)。另外，树脂突起40的上升，以向外方(斜上方)形成凹状的方式弯曲而形成。如上所述，使第二树脂层30在第一树脂层20的全周形成时(参照图11)，能够在树脂突起40的全周上使上升具有平缓的倾斜面而形成。由此，能够使后述的导电层50带着高的密接性而从所有的方向在树脂突起40上延伸。
(4)接着，如图10～图12所示，形成与电极垫16电连接，并且经过树脂突起40上的导电层50。还有，图10是导电层的形成工序后的部分俯视图，图11是图10的XI-XI线剖面图，图12是图10的XII-XII线剖面图。
首先，在形成导电层50前，除去电极垫16上的氧化层17。氧化层17，例如通过自然氧化而生成或通过上述的树脂固化工序而生成。作为除去氧化层17的方法，例如能够适用Ar气体的逆溅射。若在半导体基板10上全面进行Ar气体的逆溅射，则由此在树脂突起40的表面上的炭化进展。在树脂突起40的表面，形成炭化层或成为炭化层前的层(例如等离子聚合层)。还有，本实施方式，在如此形成炭化层时特别有益。
导电层50，通过溅射法或蒸镀法而使导电箔成膜，其后，通过形成图案而形成导电箔。导电层50，例如能够由形成基底的第一层(例如TiW层)52、和在其上的第二层(例如Au层)54构成的多个层形成。此时，通过第一以及第二层52、54形成导电箔，可以以保护层作为掩模通过刻蚀而使第二层52形成图案，也可以以形成图案后的第二层54作为掩模而使第一层53形成图案。成为基底的第一层52，能够用于金属扩散防止、密接性提高或作为镀敷层而利用。作为变形例，还可以通过溅射法或蒸镀法形成作为基底的第一层52，通过无电解镀或电镀形成其上的第二层54。由此，能够容易地形成厚的第二层54。或，导电层50，可由单一层(例如Au层)形成。还有，导电层50的材质不限于上述，例如，可以使用Cu、Ni、Pd、Al、Cr等。
导电层50，是电连接电极垫16和树脂突起40之间的配线层。导电层50至少以经过电极垫16上、钝化膜18上、以及树脂突起40上而形成。在本实施方式中，树脂突起40的上升平缓地形成，因此能够实现导电层50的密接性。因此，能够实现导电层50的剥离以及断线的防止。在图11所示的例中，使导电层50以超过树脂突起40，进而达到钝化膜18上的方式形成。换而言之，使导电层50以从树脂突起40在多个方向(例如反对方向)分支而到达钝化膜18上的方式形成。由此，能够实现相对于导电层50的基底的密接性的进一步提高。还有，导电层50，具有在树脂突起40上形成的电连接部56。
如图12以及图13所示，形成导电层50后，将导电层50作为掩模而可以部分地除去树脂突起40。由此，能够实现例如实装时的粘结剂的排出性的提高。例如，树脂突起40以具有规定的宽度的直线状形成，在树脂突起40的长度方向上多个电连接部56隔有规定的间隔排列时，将从邻接的电连接部56彼此之间露出的部分通过各向异性的蚀刻剂(例如O2等离子)58而蚀刻除去。此时，为了防止钝化膜18的损伤，而以邻接的电连接部56彼此之间设置树脂的残渣44的方式进行刻蚀。根据本实施方式，因为树脂突起40的上升平缓地形成，所以各向异性的腐蚀剂容易进入树脂突起40的根基部，由此，能够容易地除去历来增加的形成于树脂突起40的根基部的炭化层等。因此，防止以炭化层等为起因的迁移，能够提高可靠性。
如此，能够制造具有多个树脂中心突起60的半导体装置100。树脂中心突起60，形成于半导体基板10的一方的面(集成电路14的形成面)上，包括：树脂突起42；和形成于树脂突起42上的电连接部56。据此，因为树脂突起42成为中心，其自身具有弹力性，所以能够实现实际安装时的应力缓和功能和电连接可靠性的提高。还有，本实施方式的半导体装置，具有从上述的半导体装置的制造方法的内容导出的结构。
(电子机器)
图14是表示本发明的实施方式的电子设备的图。电子设备(例如显示设备)1000，含有半导体装置100。在图14所示的例中，电子设备1000，包括：半导体装置100；由树脂膜构成的第一基板200；由玻璃等构成的第二基板300。半导体装置100，例如面朝下安装于第一基板200，详细地说，形成于第一基板200的配线图和半导体装置100的树脂中心突起60被电连接。在半导体装置100和第一基板200之间，设有未图示的绝缘性粘结剂(例如NCF(Non Conductive Film)或NCP(Non Conductive Paste))。或者，也可以省略掉第一基板200，而将半导体装置100面朝下实装于第二基板300。作为电子设备1000的例，例如可例举出液晶显示器、等离子显示器、EL(Electrical Luminescence)显示器等。还有，在图15中表示作为本发明实施方式的电子机器一例的笔记本型电脑，图16中表示移动电话。
(变形例)
图17是说明本实施方式的变形例的半导体装置的制造方法的图。在本变形例中，树脂突起140的形态和上述不同。
第一以及第二树脂层120、130的形成工序的详细操作能够适用上述的内容。但是，在本变形例中，在导电层50的形成工序前，对于各个的电极垫16任一个的树脂突起140以成对的方式，相互间隔而形成了多个树脂突起140。例如，第一树脂层120，以圆柱状形成图案后，通过固化工序，而能够以半球状形成。第二树脂层130，能够在各自的第一树脂层120的全周而形成。
导电层50，例如电连接任一个的电极垫16和任一个的树脂突起140之间。此时，导电层50，可以以仅覆盖一个树脂突起140的一部分的方式形成，也可以以覆盖其全部的方式形成。前者的情况，由于树脂突起140的一部分露出，从而外力被开放，因此能够防止安装时的电连接部56(导电层50)的裂缝。
还有，在本变形例中，因为使树脂突起140预先隔开而形成，因此如上述例，能够省略形成导电层50后的树脂突起的一部分除去工序。
本变形例的其他详细操作，能够适用上述的内容，在本变形例中也能达到上述效果。
本发明，并不限于上述的实施方式，可以进行各种变更。例如，本发明包括与实施方式说明的结构实质上相同的结构(例如，功能、方法以及结果相同的结构、或目的以及结果相同的结构)。另外，本发明，含有替代实施方式说明的结构的非实质的部分的结构。另外，本发明包括具有和实施方式说明的结构相同的作用效果的结构，或能够达到相同的目的的结构。另外，本发明，包括在实施方式说明的结构中增加公知技术的结构。

Claims (6)

1.一种半导体装置的制造方法，其中，包括：
(a)在具有电极垫以及钝化膜的半导体基板的上方形成第一树脂层的工序；
(b)固化所述第一树脂层的工序；
(c)至少在所述第一树脂层的根基部形成第二树脂层的工序；
(d)通过固化所述第二树脂层，形成树脂突起的工序，该树脂突起包含所述第一以及第二树脂层，并且与固化后的所述第一树脂层相比上升更平缓；
(e)形成导电层的工序，该导电层与所述电极垫电连接，且经过所述树脂突起的上方。
2.根据权利要求1所述的半导体装置的制造方法，其中，
在所述(e)工序中，
在形成所述导电层前，通过Ar气体，从所述电极垫的表面除去氧化膜，并且，使所述树脂突起的表面的炭化进展，
在形成了所述导电层后，将所述导电层作为掩模，部分地除去所述树脂突起。
3.根据权利要求1或2所述的半导体装置的制造方法，其中，
所述第二树脂层的固化前的树脂材料，与所述第一树脂层的固化前的树脂材料相比，相对于所述钝化膜的润湿性更高。
4.根据权利要求1至3中任一项所述的半导体装置的制造方法，其中，
在所述(c)工序中，
在所述第一树脂层的全周上形成所述第二树脂层。
5.根据权利要求1至4中任一项所述的半导体装置的制造方法，其中，
在所述(c)工序中，
通过涂布于所述半导体基板的上方，然后进行刻蚀，将所述第二树脂层至少形成在所述第一树脂层的根基部。
6.根据权利要求1至4中任一项所述的半导体装置的制造方法，其中，
在所述(c)工序中，
通过液滴吐出法，形成所述第二树脂层。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101527288B (zh) * 2008-03-04 2011-06-15 台湾薄膜电晶体液晶显示器产业协会 接点结构以及接合结构
CN105633030A (zh) * 2014-11-25 2016-06-01 精工爱普生株式会社 电子部件及其制造方法

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US8021976B2 (en) 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US6936531B2 (en) * 1998-12-21 2005-08-30 Megic Corporation Process of fabricating a chip structure
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US7902679B2 (en) * 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US7099293B2 (en) 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
US7932603B2 (en) * 2001-12-13 2011-04-26 Megica Corporation Chip structure and process for forming the same
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US7265045B2 (en) 2002-10-24 2007-09-04 Megica Corporation Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
JP4686967B2 (ja) * 2003-10-14 2011-05-25 セイコーエプソン株式会社 光素子の製造方法
US7394161B2 (en) * 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
US8067837B2 (en) 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
US8294279B2 (en) 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
JP4853609B2 (ja) * 2005-07-05 2012-01-11 セイコーエプソン株式会社 半導体装置の製造方法
US7582966B2 (en) 2006-09-06 2009-09-01 Megica Corporation Semiconductor chip and method for fabricating the same
US8133808B2 (en) 2006-09-18 2012-03-13 Tessera, Inc. Wafer level chip package and a method of fabricating thereof
JP4147433B2 (ja) * 2007-02-19 2008-09-10 セイコーエプソン株式会社 半導体装置及びその製造方法
JP4572376B2 (ja) * 2007-07-30 2010-11-04 セイコーエプソン株式会社 半導体装置の製造方法および電子デバイスの製造方法
JP5077540B2 (ja) * 2007-08-10 2012-11-21 セイコーエプソン株式会社 半導体装置の製造方法
TWI341628B (en) * 2008-02-12 2011-05-01 Taiwan Tft Lcd Ass Contact structure and bonding structure
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JP4737466B2 (ja) * 2009-02-09 2011-08-03 セイコーエプソン株式会社 半導体装置及びその製造方法
US20100264522A1 (en) * 2009-04-20 2010-10-21 Chien-Pin Chen Semiconductor device having at least one bump without overlapping specific pad or directly contacting specific pad
JP2011061035A (ja) * 2009-09-10 2011-03-24 Renesas Electronics Corp 半導体装置の製造方法及びマスク
JP5386302B2 (ja) * 2009-10-27 2014-01-15 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP6015379B2 (ja) * 2012-11-26 2016-10-26 セイコーエプソン株式会社 半導体装置
JP6459690B2 (ja) * 2015-03-25 2019-01-30 セイコーエプソン株式会社 電子部品及びその製造方法
JP6729188B2 (ja) * 2016-08-31 2020-07-22 セイコーエプソン株式会社 接合構造体、圧電デバイス、液体噴射ヘッド、液体噴射装置、及び、接合構造体の製造方法
JP6840969B2 (ja) * 2016-09-21 2021-03-10 セイコーエプソン株式会社 Ｍｅｍｓデバイス、液体噴射ヘッド、及び、液体噴射装置
KR101897653B1 (ko) * 2017-03-06 2018-09-12 엘비세미콘 주식회사 컴플라이언트 범프의 제조방법

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02272737A (ja) 1989-04-14 1990-11-07 Citizen Watch Co Ltd 半導体の突起電極構造及び突起電極形成方法
JPH0590269A (ja) * 1991-09-27 1993-04-09 Seiko Epson Corp 突起電極の構造および突起電極の形成方法
JP3070514B2 (ja) * 1997-04-28 2000-07-31 日本電気株式会社 突起電極を有する半導体装置、半導体装置の実装方法およびその実装構造
JP3952346B2 (ja) * 1998-05-20 2007-08-01 株式会社デンソー 回転電機及びその製造方法
TW478089B (en) * 1999-10-29 2002-03-01 Hitachi Ltd Semiconductor device and the manufacturing method thereof
JP3347118B2 (ja) * 2000-01-26 2002-11-20 三菱電機株式会社 交流発電機
US6710446B2 (en) * 1999-12-30 2004-03-23 Renesas Technology Corporation Semiconductor device comprising stress relaxation layers and method for manufacturing the same
JP3707606B2 (ja) * 2000-02-07 2005-10-19 三菱電機株式会社 回転電機の巻線組立およびその製造方法ならびにその巻線組立を用いた回転電機の固定子
JP3894483B2 (ja) * 2002-09-04 2007-03-22 三菱電機株式会社 回転電機の巻線部材および巻線組立の製造方法並びにその巻線部材の製造装置
JP3969295B2 (ja) * 2002-12-02 2007-09-05 セイコーエプソン株式会社 半導体装置及びその製造方法と回路基板及び電気光学装置、並びに電子機器
JP2005101527A (ja) 2003-08-21 2005-04-14 Seiko Epson Corp 電子部品の実装構造、電気光学装置、電子機器及び電子部品の実装方法
JP3938128B2 (ja) 2003-09-30 2007-06-27 セイコーエプソン株式会社 半導体装置とその製造方法、回路基板、電気光学装置、及び電子機器
JP4218622B2 (ja) 2003-10-09 2009-02-04 セイコーエプソン株式会社 半導体装置の製造方法
JP3873986B2 (ja) 2004-04-16 2007-01-31 セイコーエプソン株式会社 電子部品、実装構造体、電気光学装置および電子機器
JP2005340761A (ja) 2004-04-27 2005-12-08 Seiko Epson Corp 半導体装置の実装方法、回路基板、電気光学装置並びに電子機器
JP3994989B2 (ja) 2004-06-14 2007-10-24 セイコーエプソン株式会社 半導体装置、回路基板、電気光学装置および電子機器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101527288B (zh) * 2008-03-04 2011-06-15 台湾薄膜电晶体液晶显示器产业协会 接点结构以及接合结构
CN105633030A (zh) * 2014-11-25 2016-06-01 精工爱普生株式会社 电子部件及其制造方法

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