CN1832335A - CMOS superwide band low noise discharger - Google Patents

Abstract

This invention relates to a CMOS LNA circuit used in a UWB system receiver composed of a matching stage, a amplifying stage and a load stage, in which, the matching stage matches the signal source with input impedance very well, the amplifying stage can keep the circuit working under low voltages at the same time when securing high gain and a certain input actual impedance and the load stage connects inductance and impedance in series to guarantee smooth gain in the working frequency band.

Description

A kind of CMOS superwide band low noise discharger

Technical field

The invention belongs to the radio frequency integrated circuit design field, be specifically related to a kind of CMOS ultra-wideband low-noise amplifier circuit that under low-power consumption is used, still can reach high-gain, low noise and good input coupling and be suitable for low voltage application.

Background technology

Ultra broadband (UWB) technique functions comes from late 1950s, uses in communication equipments such as radar mainly as military technology before this.Along with the develop rapidly of radio communication, people have higher requirement to high-speed radiocommunication, and super-broadband tech is proposed again again, and receives much attention.UWB uses continuous carrier wave different with common communication mode, and its adopts extremely short pulse signal to come transmission information, and the time of each pulse persistance has only the time of tens psecs to several nanoseconds usually.The bandwidth that these pulses are shared even up to several GHz, so maximum data transfer rate can reach hundreds of Mbps.In high-speed communication, the transmitting power of UWB equipment is but very little, only is more than one percent of existing equipment, is similar to noise for common non-UWB receiver, therefore theoretically, UWB can with existing radio equipment shared bandwidth.So UWB is the data communication mode of a kind of high speed and low-power consumption, it is expected to be widely used at wireless communication field.At present, famous big companies such as Intel, Freescale, Sony are carrying out the exploitation and the popularization of UWB wireless device.

FCC (FCC) has announced in 2002 and has allowed civilian UWB frequency range, i.e. 3.1～10.6GHz.At present, in the definition of UWB system, there are two kinds of schemes, direct sequence (DS-CDMA) and many band OFDM (MB-OFDM).For fear of conflicting with the 5GHz working frequency range of WLAN-802.11a, present scheme roughly is divided into two big frequency ranges: low-frequency range is approximately 3.1～5.2GHz, as the exploitation frequency range of first generation UWB system; High band is approximately 5.8～10.6GHz.In addition, in the system configuration of these two kinds of schemes, all used requisite module in the radio communication---low noise amplifier (LNA).

Low noise amplifier is one of module of most critical in the radio-frequency receiver front-end.In traditional arrowband LNA, generally require circuit that low noise factor, suitable gain, good input coupling and high linearity are arranged.And reach in the radio ultra wide band system of several GHz in bandwidth, because the circuit work frequency height, therefore good input coupling and the smooth suitable gain in whole frequency then is most important also the most inaccessible performance requirement except that noise characteristic.

For the UWB system, low-power consumption is its basic demand.But, owing to very big noise is arranged in the input signal, according to system noise cascade formula as can be known, must provide enough gains can not cause excessive influence to systematic function to guarantee a back level noise at the low noise amplifier of receiving terminal, simultaneously, enough gain need consume high power consumption and could realize.Therefore the contradiction that has certain relation between the gain requirement of LNA and power consumption require, how increasing gain when reducing power consumption as much as possible is the important topic that is applied to LNA design in the UWB system.

Secondly,, when carrying out the chip-scale design,, usually adopt the very little technology of characteristic size, 0.18 μ m or littler for example, and the low voltage operating often that undersized metal-oxide-semiconductor is followed in order to improve the cut-off frequency of metal-oxide-semiconductor because UWB system works frequency is very high.For the circuit of practical application, in order to reduce the interference of substrate noise, usually adopt the differential configuration of belt current mirror, and current mirror to consume a part of voltage that drives excessively, this has just given prominence to the difficulty that designs under the low-voltage more.Therefore, designing the low noise amplifier that can work under low-voltage for the chip-scale design of ultra broadband, is inevitable challenge.

In JSSC 2004, document [1] has proposed a kind of structure based on traditional narrow LNA, and its power consumption is very little, but it has used the source negative feedback structure, makes this circuit gain have only 9.6dB, and for the UWB system, this can't satisfy system requirements; And this one 100 Ω left and right sides of structure output termination load resistance, it has consumed certain voltage remaining, therefore is not suitable for the differential applications of belt current mirror under the low-voltage.

List of references:

[1]Andrea?Bevilacqua，Ali?M?Niknejad.An?Ultrawideband?CMOS?Low-Noise?Amplifier?for3.1-10.6-GHz?Wireless?Receivers[J].IEEE?J?Solid-State?Circuits，2004，39(12)：2259-2268.

Summary of the invention

The objective of the invention is to design a kind of UWB of being applied to system receiver, high-gain is arranged under low-power consumption and be suitable for the circuit structure of the CMOS low noise amplifier of low voltage operating.

The low ultrasonic amplifier circuit of the CMOS of the present invention's design, by matching stage 1, amplifying stage 2 and load stage 3 connect to form successively, and wherein, matching stage is a multistage LC series shunt network, and amplifying stage is a cmos circuit, and load stage is the inductance resistance series circuit.Its structure as shown in Figure 1.

The effect of every part is as follows: matching network makes signal source and input impedance matched well; Amplifying stage also makes circuit work under low-voltage when guaranteeing high-gain and certain input true impedance; Load stage is inductance and resistance series connection, guarantees that circuit has certain gain and flat gain in working band.

Among the present invention, the dummy input circuit of matching stage and amplifying stage is common forms a second order or the above LC bandpass filtering of second order network, and it is connected by a series inductance with amplification grade circuit.

Among the present invention, amplification grade circuit is made up of PMOS pipe and two NMOS pipes, and one of them PMOS pipe and NMOS pipe grid altogether leak altogether and be connected, and PMOS-NMOS is right in formation, and input signal enters from grid, exports from draining; This PMOS pipe source electrode connects a series inductance, and this NMOS manages source ground or connects current mirror; Another NMOS pipe is grid level altogether, and the drain electrode that its source electrode and PMOS-NMOS are right directly is connected, and grid connects bias direct current voltage, drains to be connected with load stage.

Among the present invention, load stage is an inductance resistance series circuit, the one termination power, and another termination is the drain electrode of grid level NMOS pipe altogether.

Matching way can have resistive degeneration, common gate input and three kinds of modes of matching network coupling.The mode of resistive degeneration can obtain the better matching property energy when improving gain, but the method has been introduced feedback loop in input and output, and therefore stability is very poor.The mode of common gate input does not need complicated matching network, exactly because but import and will mate with signal source, the gain of its input stage will be subjected to very big influence, thereby directly causes the deterioration of circuit noise performance.Based on above consideration, the present invention has adopted the mode of matching network coupling.

The matching network of this circuit is the logical wave-wave network of a multistage LC joint, and it is exactly in fact a LC band pass filter.Its effect is that the input impedance that amplifying stage produces is converted into genertor impedance, to guarantee the input coupling, also is that circuit can access higher input power.Because the bandwidth of coupling reaches several GHz, thus input matching network to require be more than the second order at least, and frequency range is high more, exponent number requires high more.Choosing of matching network structure, consider the characteristics that integrated circuit is realized, promptly the bondwire of chip pin is an inductance, filter is T type structure preferably.Fig. 2 has provided the examples of circuits of a second order LC filter.R wherein _sBe the resistance of input signal source, R _InBe the equivalent input resistance of amplifying stage, L ₂For matching stage is connected inductance L with amplifying stage _gWith series inductance L such as amplifying stages _iSum, C ₂Equivalent series electric capacity for amplifying stage.

Amplifying stage is the core of this circuit, and its circuit structure as shown in Figure 3.It is right that it is input as PMOS-NMOS.Wherein PMOS manages M _pSource electrode connects inductance L _p, use the mode of inductance and metal-oxide-semiconductor serial connection to produce true impedance, its value is $R=\frac{\mathrm{\ω}{L}_p}{C_{\mathrm{gsp}}},$ L wherein _pBe tandem electric inductance sense value, C _GspBe M _pPipe grid source electric capacity.Because NMOS pipe M _N1Mobility ratio M _pGreatly, in TSMC0.18 μ m RF technology, both ratio reaches 5: 1, also is that NMOS is better than PMOS on amplifying power, so in order to guarantee the circuit high-gain, select NMOS pipe M _N1As main amplifying stage; Simultaneously, in order to overcome the shortcoming of inductor degeneration, M _N1Pipe does not insert tandem electric inductance, but has adopted the common source connection, i.e. M among Fig. 3 _N1The source electrode of pipe ground connection or connect current mirror when both-end is used when single-ended applications is to guarantee can to reach bigger gain under the same power consumption.

Cascaded stages is a NMOS pipe M of grid connection altogether _N2This metal-oxide-semiconductor reduces to import the output impedance of PMOS-NMOS to pipe on the one hand, to guarantee PMOS-NMOS to the tube current amplifying power constant the time, its voltage amplification ability weakens, so, according to the principle of Miller effect, also just can reduce of the influence of input pipe gate leakage capacitance to circuit; On the other hand, this metal-oxide-semiconductor can be isolated the input and output level, guarantees that circuit has good isolation.

The load stage of this circuit is an inductance resistance series circuit.In the design of arrowband LNA, usually adopt inductance capacitance resonance to choose required frequency, still, in the broadband, flat gain is prior requirement, the parasitic capacitance of load end can make the serious decay of front end gain, therefore uses the series connection of inductance resistance.Wherein inductance can weaken the influence of output capacitor load, guarantees that circuit has high output impedance when high band; Resistance can reduce the Q value of inductance, makes output impedance smooth in working frequency range, rather than simple LC resonance, has guaranteed promptly that also gain is smooth in working frequency range.

Improvements of the present invention and principle thereof

This circuit is at purpose of design, be two requirements of differential applications under high-gain and the low-voltage under the low-power consumption, the structure that proposes based on JSSC 2004 " An Ultrawideband CMOS Low-Noise Amplifier for 3.1-10.6-GHzWireless Receivers " literary composition of present extensive use is improved.

At first be to have carried out corresponding improvement at differential applications under the low-voltage.For structure proposed above, suppose in its differential configuration that is applied in the belt current mirror.Because load end has adopted resistance inductance cascaded structure, its resistance has about 100, if single-ended current sinking 4mA, then this resistance consumption voltage 0.4V; In addition, if the current mirror attrition voltage remaining 0.3V of supposition differential pair tube, so for low-voltage (for example 1.8V) differential applications, the two-stage NMOS pipe that cascode connects can only have the supersaturation voltage of 1.1V.This realizes that difficulty is very big, unstable working condition for the radio circuit that certain linearity requires and operating current is bigger is arranged.

This circuit has been introduced a PMOS pipe on custom circuit, itself and resistance branch are shunted, and reduces consumed current on the resistance, that is to say the voltage remaining that has improved for the MOS offset design.In addition the voltage remaining that consumes of PMOS pipe with the isolation metal-oxide-semiconductor on the resistance branch consume similar, that is to say in the fully differential of belt current mirror is used from the voltage source to ground, to have only 3 grades of metal-oxide-semiconductors serial connections, lacked the resistance one-level, improved the voltage remaining of design.

Secondly improve at the purpose of low-power consumption high-gain.In general,, can realize, but many one-levels amplifying circuit that also with regard to many power consumptions of one times, this uses for UWB, is not rational selection by the mode of multistage amplification iff requiring high-gain.For structure above, its amplification has only one-level, and in order to reach input coupling, amplifies NMOS pipe source electrode and inserted an inductance, has also promptly introduced negative feedback, makes that circuit gain is very little, and the highest in the working frequency range have only 9.6dB.

This circuit is separately considered the input coupling and two performances that gain.The input coupling realizes that by the inductance that PMOS pipe source electrode inserts the NMOS pipe that gain is played a major role then adopts common source to connect, and has avoided the influence of negative feedback to gain.Simultaneously, because current multiplexing, this circuit only is equivalent to one-level and amplifies, and has reached the requirement of low-power consumption high-gain.

Description of drawings

Fig. 1. the structural diagrams of broadband LNA.

Fig. 2. second order matching network diagram.

Fig. 3. the amplification grade circuit diagram.

Fig. 4. the input equivalent electric circuit.

Fig. 5. exemplary circuit figure.

Fig. 6. example S11 simulation result.

Fig. 7. example S21 and NF simulation result.Wherein, A point place frequency is 3.96G, and gain S21 is 16.0755dB; B point place frequency is 3.60593G, and noise factor is 1.65093dB.

Fig. 8. example kf simulation result.Wherein, A point place frequency is 5.77175G, and the coefficient of stability is 10.7384.

Fig. 9 Example II P3 simulation result.

Embodiment

Concrete enforcement of the present invention mainly comprises three parts: the design of matching stage, the design of amplifying stage, the design of load stage.

Matching network is a logical LC filter of band from essence, according to traditional filter design method, need be after determining input and load resistance, and tabling look-up according to the requirement of passband and stopband obtains each component parameters of required order filtration device.But, the prerequisite of this method is that load resistance will have definite value.For this LNA, because output loading is:

$R=\frac{\mathrm{\ω}{L}_p}{C_{\mathrm{gsp}}}---\left(1\right)$

Wherein ω is the angular frequency of work, L _pBe the inductance that PMOS pipe source electrode inserts, C _GspBe the grid source electric capacity of PMOS pipe, as can be seen, the output loading of filter is a value with frequency change from the formula (1).Therefore adopt traditional filter design method can not well realize coupling.

Based on above reason, when realizing the input matching network of this circuit, not have with reference to traditional filter design method, but with the method for practicality more.Consider that any input impedance can be corresponding one by one with the point on the Smith circle diagram, therefore can retouch the input impedance of different frequent points on the Smith circle diagram, observe the position of input impedance after certain reactance component of process of each frequency then, after all frequency process conversion of several elements, can both be distributed in round dot around, also just reached the purpose of coupling.Concrete realization can be used Smith circle diagram cad tools, as Smith Charter etc.

For the design of amplifying stage, mainly be choosing of NMOS pipe size, take all factors into consideration the requirement of gain and impedance matching.

Expression formula according to gain:

$A_v=(g_{\mathrm{mn}}+\frac{g_{\mathrm{mp}}}{1+g_{\mathrm{mp}}{L}_{p}s})Z_{\mathrm{out}},---\left(2\right)$

Wherein, g _MnBe the mutual conductance of NMOS pipe, g _MpBe the small-signal transconductance of PMOS pipe, Z _OutLoad for output.From formula (2), as can be seen, the gain of circuit be increased, the size of NMOS pipe can be increased.

Consider the requirement of impedance matching.Because $\mathrm{\Γ}=\left|\frac{Z_{\mathrm{in}}-Z_S}{Z_{\mathrm{in}}+Z_S}\right|,$ Wherein Г is an input reflection coefficient, Z _InBe input impedance, ZS is a genertor impedance, and in general, the imaginary part of input impedance can be eliminated by matching network, so the reflection coefficient of the maximum that circuit can reach is: ${\mathrm{\Γ}}_{\max }=\left|\frac{R_{\mathrm{in}}-R_S}{R_{\mathrm{in}}+R_S}\right|,$ Therefore, if input coupling herein will reach the maximum-10dB of system requirements, just R must be arranged _In〉=24 Ω.Fig. 4 is the equivalent electric circuit of this circuit input end, and by circuit as can be known, the real part of input impedance is:

$\mathrm{Re}\left[Z_{\mathrm{in}}\right]=\frac{g_{\mathrm{mp}}{L}_p{C}_{\mathrm{gsp}}}{g_{\mathrm{mp}}^2{L}_p^2{C}_{\mathrm{gsn}}^2{\mathrm{\ω}}^2+C_{\mathrm{gsn}}^2{C}_{\mathrm{gsp}}^2{\mathrm{\ω}}^2{(L_p\mathrm{\ω}-\frac{1}{C_{\mathrm{gsp}}\mathrm{\ω}}-\frac{1}{C_{\mathrm{gsn}}\mathrm{\ω}})}^2}---\left(3\right)$

C wherein _GspBe PMOS grid source electric capacity, C _GsnBe NMOS grid source electric capacity, by expression formula as can be known, along with the increase of NMOS size, C _GsnIncrease, the real part of input impedance can reduce.That is to say that the size of NMOS pipe need be got rational value according to the requirement that gains and input is mated, to guarantee reaching under the prerequisite of coupling raising gain as much as possible in satisfied input.

The output stage significant feature is to weaken the influence of output parasitic capacitance to gain, to be increased in the flatness that gains in the working frequency range.Because output load impedance is:

$Z_{\mathrm{out}}=\frac{L_{d}s+R}{R{C}_{d}s+1-L_d{C}_d{\mathrm{\ω}}^2},---\left(4\right)$

L wherein _dBe the inductance of output loading end, C _dBe the output parasitic capacitance, R is the resistance of connecting with inductance.By expression formula (2) and (4) as can be seen, circuit gain is increased, can increase inductance value, but will guarantee L _dC _dω ²＜1; The circuit gain flatness is increased, can increase resistance R, increase R simultaneously output impedance is reduced, this just needs one well to trade off.

Provided the example of a specific implementation below.

As shown in Figure 5, this example circuit is the differential applications of belt current mirror, and its working frequency range is UWB Band1, i.e. 3.1～5.2GHz.With its structure of single-ended explanation.Be input as second order LC band pass filter, L ₁, C ₁, L _G1Constitute matching network with the equivalent inductance and the electric capacity of amplifying stage; M _N1, M _P1, M _N2And L _P1Constitute amplifying stage; L _D1And R ₁Constitute load stage.Output has added a source follower M on the circuit of original design _B1As Buffer, its output impedance is 50 Ω, to make things convenient for the test of output.

The emulation of this circuit is adopted Cadence SpectreRF instrument based on TSMC 0.18 μ m RF technology.Supply voltage is 1.8V, and this exemplary circuit both-end current sinking is 8mA, and simulation result such as Fig. 6 are to shown in Figure 8.This result shows, and in working frequency range, matching degree S11 can reach-and below the 10dB, the gain S21 of band Buffer is 16dB, and in general, Buffer can make about gain decline 3dB, so the gain of this circuit is about 19dB.Noise factor is 1.65～2.37dB, the coefficient of stability can reach more than 10 at all working frequency range, the third order intermodulation point IIP3 of circuit is-10dBm, good linearty has been described, these results show: the work that this structure still can be stable under low-voltage, and under low-power consumption, can reach the performance of high-gain.

Claims (4)

1, the low ultrasonic amplifier circuit of a kind of CMOS, it is characterized in that being connected to form successively by matching stage (1), amplifying stage (2) and load stage (3), wherein, matching stage is a multistage LC series shunt network, amplifying stage is a cmos circuit, and load stage is the inductance resistance series circuit.

2, amplifier circuit according to claim 1 it is characterized in that the dummy input circuit of described matching stage and amplifying stage is formed a second order or the above LC bandpass filtering of second order network jointly, and it is connected by a series inductance with amplification grade circuit.

3, amplifier circuit according to claim 1, it is characterized in that described amplification grade circuit is managed by a PMOS and two NMOS pipes are formed, one of them PMOS pipe leaks altogether with the common grid of NMOS pipe and is connected, it is right to form PMOS-NMOS, input signal enters from grid, from drain electrode output, this PMOS pipe source electrode connects a series inductance, and this NMOS manages source ground or connects current mirror; Another NMOS pipe is grid level altogether, and the drain electrode that its source electrode and PMOS-NMOS are right directly is connected, and grid connects bias direct current voltage, drains to be connected with load stage.

4, amplifier circuit according to claim 1 is characterized in that described load stage is an inductance resistance series circuit, the one termination power, and another termination is the drain electrode of grid level NMOS pipe altogether.

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