CN1825760A - Data transmission controller and sampling frequency converter - Google Patents

Data transmission controller and sampling frequency converter Download PDF

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Publication number
CN1825760A
CN1825760A CN 200610058028 CN200610058028A CN1825760A CN 1825760 A CN1825760 A CN 1825760A CN 200610058028 CN200610058028 CN 200610058028 CN 200610058028 A CN200610058028 A CN 200610058028A CN 1825760 A CN1825760 A CN 1825760A
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data
request signal
data amount
interpolation
frequency control
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CN100521532C (en
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望月孝祥
西冈直俊
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Yamaha Corp
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Yamaha Corp
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Abstract

In a data transmission controller apparatus, a first-in first-out storage stores newly inputted data in response to a write request signal, and reads and outputs the stored data which has been stored earliest in response to a read request signal. A remaining data amount detection portion detects a remaining data amount of the stored data which remain in the first-in first-out storage. A variable frequency oscillating portion generates an enable signal at a time rate according to frequency control information so as to enable generation of the write request signal or read request signal. A frequency control portion corrects the frequency control information so as to return the remaining data amount to an appropriate value when the remaining data amount detected by the remaining data amount detection portion varies away from the appropriate value toward an upper limit value or varies away from the appropriate value toward a lower limit value.

Description

Data Transmission Controlling and sampling frequency converter
Technical field
The present invention relates to a kind of Data Transmission Control Unit and a kind of sampling frequency converter that uses this Data Transmission Control Unit that reduces shake (jitter) function that have.Specifically, the present invention relates to a kind of sampling frequency converter that is applicable to digital audio-frequency apparatus etc.
Background technology
In fields such as digital audio, usually will be at two exchanged between equipment voice datas, these two equipment and independently clock synchronization ground work separately.In the case, the clock synchronization of equipment and this equipment self ground dateout formerly.Clock synchronization ground input data at back equipment and this equipment self.Usually, the clock of two equipment comprises shake.In order to reduce shake, between two equipment, insert FIFO (first-in first-out buffer).Usually by these FIFO transmission data.Except using FIFO, PLL (phase-locked loop) control can be set also.This PLL control monitors remaining data amount among the FIFO, make the shake of clock may not can cause like this to overflow on the FIFO or under overflow.For example, when the remaining data quantitative change must be bigger than suitable value, this PLL control improved the data output speed among the FIFO.For example, when the remaining data quantitative change must be than suitable value hour, this PLL control reduces the data output speed among the FIFO.In fields such as digital audio, provide the equipment that meets various sample frequencys.Usually, the equipment with different sample frequencys can be connected to each other.In this case, sampling frequency converter is used for the sample frequency from the sampled data of the output of equipment formerly is adjusted into sample frequency at back equipment.Publication number be 11-55075 disclosed Japanese Patent Application Publication above-mentioned FIFO and PLL control is applied to the technology of sampling frequency converter.
Above-mentioned conventional art improves or reduces data output speed or data input speed among the FIFO according to the difference between remaining data amount among the FIFO and the described suitable value.When excessively improving according to this difference or having reduced speed, the remaining data amount can change along with the time, and data transfer operation may become unstable.That is, have time delay between the result that adjustment and remaining data amount in data output speed etc. improve or reduce.At time lapse, still adjust data output speed etc.When the remaining data quantitative change must be stablized, the variation of remaining data amount improved a little.
Digital audio-frequency apparatus etc. use the various sample frequencys such as 32kHz, 44.1kHz and 48kHz.May there be the situation connected to one another of the equipment with different sample frequencys.When receiver side equipment reads the serial data of the original signal waveform that sends from transmitter side equipment with fixed speed operation, signal output waveform along the time axle distortion.Therefore, the incorrect original signal waveform of reproducing.In order to address this problem, transmitter side equipment can use sampling frequency converter.Such sampling frequency converter can have the interpolative operation device.The past data of the specified quantity of this sampling frequency converter cumulative orders input.When the reception of receiver side equipment had the data request signal of given sample frequency, this sampling frequency converter was got this time point as interpolated point.This sampling frequency converter is by carrying out the data that interpolative operation is created in this interpolated point to cumulative data, and the data that produce are offered receiver side equipment.
When in above-mentioned sampling frequency converter data being offered receiver side equipment, the sampled point of these data is corresponding with the moment that receives data request signal.This data request signal need be accurately so that do not comprise shake.Yet, certain restriction is arranged for from data request signal, removing shake.Shake must appear when data request signal.When producing significantly shake, it upsets the equal intervals that offers the data of receiver side equipment from sampling frequency converter.When receiver side equipment when given interval is reproduced or is write down such data, signal waveform reproduction or record is with respect to the original signal waveform distortion that data showed before the sample frequency conversion.
Summary of the invention
Consider foregoing and make the present invention.Therefore, first purpose of the present invention provides a kind of transmission control unit (TCU) and a kind of sampling frequency converter that uses this transmission control unit (TCU), this sampling frequency converter can suitably improve or reduce data output speed or data input speed, thereby promptly the remaining data amount among the FIFO is converged to suitable value, and stably transmit data.Therefore, second purpose of the present invention provides a kind of sampling frequency converter, even from the data request signal that receiver side equipment provides, comprise shake, the data of the sample frequency that this sampling frequency converter also can output device be asked to some extent and can not make wave distortion.
In the first string of the present invention, a kind of transmission control unit is provided, comprising: the first in first out storage area, it stores the data of new input in response to written request signal, and reads and export the storage data of oldest stored in response to reading request signal; Remaining data amount test section, it detects the remaining data amount of remaining storage data in the described first in first out storage area; The variable frequency oscillating part, it produces enable signal with the time rate that depends on FREQUENCY CONTROL information, thereby allows to produce written request signal or reading request signal; And FREQUENCY CONTROL part, when the detected remaining data amount in described remaining data amount test section change from suitable value towards higher limit or from described suitable value when lower limit changes, perhaps when described remaining data amount reached described higher limit or described lower limit, described FREQUENCY CONTROL was partly proofreaied and correct described FREQUENCY CONTROL information so that make described remaining data amount get back to described suitable value.Preferably, when described remaining data amount begins to change from described suitable value towards described higher limit or begins from described suitable value when described lower limit changes, described FREQUENCY CONTROL is partly proofreaied and correct described FREQUENCY CONTROL information.
A kind of sample frequency conversion equipment is provided again, comprises: the interpolation part, it compares interpolative data according to interpolation; And transmission control section, it is based on the data of FREQUENCY CONTROL message transmission interpolation, and wherein, described interpolation partly comprises: preserve part, it sequentially receives the data with first sample frequency, and the data that receive are saved as the input serial data that is used for interpolative operation; And interpolative operation part, it carries out interpolative operation by using the interpolation that produces with described transmission control section than corresponding interpolation coefficient and the described input serial data of preserving in the part that is used for interpolative operation of preserving of use, thereby produce interpolative data with second sample frequency, and wherein, described transmission control section comprises: the first in first out storage area, it stores the interpolative data of partly exporting from described interpolation and have described second sample frequency in response to written request signal, and reads and export the storage data of oldest stored in response to reading request signal; Remaining data amount test section, it detects the remaining data amount of the data of storing in the described first in first out storage area; The variable frequency oscillating part, it produces enable signal with the time rate that depends on described FREQUENCY CONTROL information, thereby allows to produce written request signal, and described variable frequency oscillating part produces the interpolation ratio that changes with the speed that depends on described FREQUENCY CONTROL information; And FREQUENCY CONTROL part, when the detected remaining data amount in described remaining data amount test section change from suitable value towards higher limit or from described suitable value when lower limit changes, perhaps when described remaining data amount reached described higher limit or described lower limit, described FREQUENCY CONTROL was partly proofreaied and correct described FREQUENCY CONTROL information so that make described remaining data amount get back to described suitable value.
A kind of sample frequency conversion equipment also is provided, comprises: the interpolation part, it compares interpolative data according to interpolation; And transmission control section, it arrives described interpolation part based on FREQUENCY CONTROL information with described transfer of data, wherein, described interpolation partly comprises: preserve part, it sequentially receives the data with first sample frequency from described transmission control section, and the data that receive are saved as the input serial data that is used for interpolative operation; And interpolative operation part, it carries out interpolative operation by using the interpolation that produces with described transmission control section than corresponding interpolation coefficient and the described input serial data of preserving in the part that is used for interpolative operation of preserving of use, thereby produce interpolative data with second sample frequency, and wherein, described transmission control section comprises: the first in first out storage area, it is stored in response to written request signal from data input and that have described first sample frequency of equipment formerly, and read the storage data of oldest stored in response to reading request signal, and export the storage data of described oldest stored to described interpolation part; Remaining data amount test section, it detects the remaining data amount of the data of storing in the described first in first out storage area; The variable frequency oscillating part, it produces enable signal with the time rate that depends on described FREQUENCY CONTROL information, thereby allows to produce written request signal, and described variable frequency oscillating part produces the interpolation ratio that changes with the speed that depends on described FREQUENCY CONTROL information; And FREQUENCY CONTROL part, when the detected remaining data amount in described remaining data amount test section change from suitable value towards higher limit or from described suitable value when lower limit changes, perhaps when described remaining data amount reached described higher limit or described lower limit, described FREQUENCY CONTROL was partly proofreaied and correct described FREQUENCY CONTROL information so that make described remaining data amount get back to described suitable value.
A kind of sample frequency conversion equipment further is provided again, comprises: the interpolation part, it is according to the interpolation coefficient interpolative data; And transmission control section, it is based on the data of FREQUENCY CONTROL message transmission interpolation, and wherein, described interpolation partly comprises: preserve part, it sequentially receives the data with first sample frequency, and the data that receive are saved as the input serial data that is used for interpolative operation; And interpolative operation part, it is by using the interpolation coefficient that is produced by described transmission control section and using the described input serial data of preserving in the part that is used for interpolative operation of preserving to carry out interpolative operation, thereby produce interpolative data with second sample frequency, and wherein, described transmission control section comprises: the first in first out storage area, it stores the interpolative data of partly exporting from described interpolation and have described second sample frequency in response to written request signal, and reads and export the storage data of oldest stored in response to reading request signal; Remaining data amount test section, it detects the remaining data amount of the data of storing in the described first in first out storage area; FREQUENCY CONTROL information generation section, its generation are used for controlling effectively the FREQUENCY CONTROL information that the remaining data amount is got back to suitable value; Written request signal produces part, and it produces described written request signal in the moment that obtains by the described FREQUENCY CONTROL information of accumulative total; And interpolation coefficient generation part, it produces described interpolation coefficient in the moment that produces described written request signal.Preferably, described written request signal produces part and produces written request signal, and described written request signal and master clock are synchronous, and the time rate that has is identical with the mean time rate of described reading request signal.
According to first scheme of the present invention, device of the present invention is only proofreaied and correct and is made described remaining data amount get back to the required minimum FREQUENCY CONTROL information of suitable value.Therefore, can prevent the fluctuation of described remaining data amount and with described remaining data amount rapid adjustment to suitable value.Therefore, can realize the stable data transmission.This transmission control unit (TCU) is used for sampling frequency converter can be realized the high quality sample frequency inverted and influenced by wave distortion.
In alternative plan of the present invention, a kind of sample frequency conversion equipment is provided, comprising: the first storage part, the data of the specified quantity of its storage order ground input; The second storage part, it stores the data of new input in response to written request signal, and sequentially reads the data of oldest stored in response to reading request signal; The writing rate adjustment member, it produces written request signal, and described written request signal and master clock are synchronous, and the time rate that has is identical with the mean time rate of described reading request signal; Interpolation coefficient produces part, and interpolation coefficient is calculated in its generation corresponding to described written request signal constantly; And interpolative operation part, it carries out interpolative operation by using described interpolation coefficient to produce part in the generation interpolation coefficient that calculates constantly and the data that use is stored in described first storage part of described written request signal, and will offer the described second storage part by the data that described interpolative operation obtains.
Preferably, described writing rate adjustment member comprises: valid data amount test section, and it detects the valid data amount of remaining storage data bulk in described second storage part of expression; The written request signal control section, thus the operation that it is carried out and master clock is synchronous produces with the periodically variable phase information corresponding to the speed of described FREQUENCY CONTROL information, and the written request signal of the cycle synchronisation of its generation and described phase information; And the FREQUENCY CONTROL part, its control frequency control information is so that converge on suitable value with described valid data amount, and wherein, described interpolation coefficient produces part and constantly calculates described interpolation coefficient according to described phase information in the generation of described written request signal.
Preferably, sample frequency conversion equipment of the present invention also comprises the N fast sampler that doubles, the described N sample frequency that fast sampler will import data that doubles multiply by factor N (N is the integer more than or equal to 2), and will have take advantage of the input data of sample frequency offer the described first storage part, wherein, described interpolative operation part is carried out the linear interpolation computing to the input data that are stored in described first storage part.
According to alternative plan of the present invention, synchronously produce described written request signal with described master clock.Be used to interpolation with the corresponding interpolation coefficient of the moment that produces this written request signal and will be stored in data in described second storage part.Even produce shake, will be stored in the influence that the data in described second storage part also can be avoided shaking in the moment that produces described reading request signal.
Description of drawings
Fig. 1 is the block diagram that illustrates according to first embodiment of the sampling frequency converter of first scheme of the present invention.
Fig. 2 is the block diagram according to the exemplary configurations of the interpolation part of first embodiment.
Fig. 3 is the oscillogram that the operation of interpolation part is shown.
Fig. 4 illustrates the diagrammatic sketch that produces the method for correcting value according to first embodiment.
Fig. 5 illustrates according to the diagrammatic sketch of the value of first embodiment generation except that " 0 " as the situation of correcting value.
Fig. 6 illustrates the sequential chart that the time according to the remaining data amount of first embodiment changes.
Fig. 7 is the block diagram that illustrates according to second embodiment of the sampling frequency converter of alternative plan of the present invention.
Fig. 8 is the block diagram that illustrates according to the embodiment of the sampling frequency converter of alternative plan of the present invention.
Fig. 9 is the block diagram that illustrates according to the detailed structure of the 1/L demultiplication of this embodiment speed sampler (down-sampler).
Figure 10 illustrates the block diagram of adjusting the detailed structure of circuit according to the writing rate of this embodiment.
Figure 11 is the diagrammatic sketch that illustrates according to the content of the Δ T of this embodiment table.
Figure 12 illustrates the sequential chart that produces the operation of part according to the written request signal of this embodiment.
Figure 13 is the diagrammatic sketch that the comparison between this embodiment effect and the conventional art is shown.
Embodiment
Embodiments of the invention are described in further detail below with reference to accompanying drawings.
＜the first embodiment 〉
Fig. 1 is the block diagram that illustrates according to first embodiment of the sampling frequency converter of first scheme of the present invention.This sampling frequency converter is made of transmission control unit (TCU) 100A, interpolation part 200A and interface 300A basically.
As shown in Figure 2, interpolation part 200A has n level shift register 201, interpolation coefficient produces part 202 and convolution part (convoluting portion) 203.Shift register 201 is sequentially accepted the data of first sample frequency from the equipment formerly before the interpolation part 200A.Shift register 201 is preserved accepted n segment data as the input serial data that is used for interpolative operation.
Interpolation is offered interpolation coefficient than Δ t from transmission control unit (TCU) 100A produce part 202.Interpolation is represented the phase place of the sampled point of the data that will produce among the interpolation part 200A than Δ t.More particularly, as shown in Figure 3, adopt described interpolative operation to obtain to be kept at the input serial data D that is used for interpolative operation in the shift register 201 according to the interpolation part 200A of this embodiment 0To D N-1In data D M+1With data D mBetween data P kThe time axle on, interpolation than Δ t represent will in be inserted in data D M+1Sampled point and data D mSampled point between data P kSampled point.Interpolation coefficient produce part 202 for example be store with various types of interpolations than corresponding not on the same group the ROM of interpolation coefficient value of Δ t.Interpolation coefficient produces part 202 outputs and the interpolation that provides from transmission control unit (TCU) 100A than the corresponding one group of interpolation coefficient value a of Δ t 0To a N-1
The data input enable signal IE that will be synchronized with master clock φ from transmission control unit (TCU) 100A offers convolution part 203.In response to this data input enable signal IE, convolution part 203 will be kept at the input serial data D that is used for interpolative operation in the shift register 201 0To D N-1With the interpolation coefficient value a that produces part 202 outputs from interpolation coefficient 0To a N-1Carry out convolution, the data P that output has second sample frequency kMaster clock φ has the frequency identical with first sample frequency.Transmission control unit (TCU) 100A offers interpolation part 200A with the data input enable signal IE that the time rate (time rate) that is equivalent to second sample frequency will be synchronized with master clock φ.When this rate will described after a while produces the structure of data input enable signal IE.
The sampled point of data that will interpolation with corresponding to the speed of second sample frequency the time move on the axle.Therefore, as shown in Figure 3, the data P of current interpolation and then kThe data P that obtains afterwards K-1Phase advance to the data D that is stored in the shift register 201 mPhase place before.In the case, interpolative data P k, follow next data P of interpolation K-1For this reason, shift register 201 will be from the new data D of equipment formerly -1Be taken into.Abandon data D the earliest in the shift register 201 N-1Carry out the operation that the phase place that makes data that will interpolation is advanced gradually by repeatedly FREQUENCY CONTROL information y being joined current interpolation than Δ t.Ratio according to first sample frequency and second sample frequency is determined FREQUENCY CONTROL information y.Transmission control unit (TCU) 100A carries out this operation.To be described in detail below.
Transmission control unit (TCU) 100A among Fig. 1 receives and preserves the serial data of second sample frequency from above-mentioned interpolation part 200A.Transmission control unit (TCU) 100A exports this serial data in the moment that is synchronized with from the reading request signal RR of interface 300A.Interface 300A outputs to transmission control unit (TCU) 100A in response to the data request signal LRCK from external equipment with reading request signal RR.Interface 300A will be correspondingly outputs to subsequently DSP from the data of transmission control unit (TCU) 100A output with the form of serial bit string SDO.
The structure of transmission control unit (TCU) 100A below will be described.
For example, FIFO 10 is the first-in first-out buffers that are made of RAM (random access memory).FIFO 10 according to this embodiment can store 8 input data that become by the designated bit array at most.The data P that provides from interpolation part 200A sequentially is provided FIFO 10 k, and from the earliest a data P kBeginning in the mode of first in first out with data P kSequentially output to interface 300A.When master clock φ by with door 101 and when being provided as written request signal WR, write control section 30 and produce write address and written request signal WE, and they are offered FIFO 10.According to written request signal WE, the input data P of FIFO 10 will be offered kWrite among the FIFO 10 zone with the write address appointment.In response to reading request signal RR, read control section 40 generations and read address and reading request signal RE, and they are offered FIFO 10 from interface 300A.Control is read the address to specify remaining of not reading to import in the data the earliest among the FIFO 10.Read the input data of reading the address appointment with this according to reading request signal RE from FIFO 10, and provide it to interface 300A.
When providing master clock φ with door 102, remaining data amount test section 50 is detected from writing write address that control section 30 produces and poor between the address of reading from reading that control section produces.That is, this difference expression remaining data amount Δ S, this remaining data amount Δ S is equivalent to the quantity of not reading to import data of current residual among the FIFO10.Vector detection circuit 51 detects following vector: promptly, the remaining data amount Δ S of this vector representation 50 outputs from remaining data amount test section is along with the variation of time.
Vector detection circuit 51 has three pointer Valid_0, Valid_1 and Valid_ptr.Pointer Valid_ptr storage current residual data volume Δ S.When the value of the value of pointer Valid_ptr and pointer Valid_0 not simultaneously, give pointer Valid_0 with the value of pointer Valid_ptr.Give pointer Valid_1 with the value that keeps up to now among the pointer Valid_0.
Usually, the relation of Valid_0＞Valid_1 represents that the remaining data amount Δ S among the FIFO 10 increases.The relation of Valid_0＜Valid_1 represents that the remaining data amount Δ S among the FIFO 10 reduces.Yet, may exist remaining data amount Δ S from the situation of increase state to the minimizing state variation, also may there be opposite situation.Can not only determine this variation according to pointer Valid_0 and Valid_1.In order to address this problem, detect the vector of the time dependent pattern of expression remaining data amount Δ S according to three pointer Valid_0, Valid_1 and Valid_ptr according to the vector detection circuit 51 of this embodiment.
The remaining data amount Δ S of 50 outputs represents the remaining data amount the FIFO 10 from remaining data amount test section.At this moment, remaining data amount Δ S represents the nearest data P that is write kWith by the nearest data P that reads of reading request signal RR kBetween phase difference.Above-mentionedly read control section 40, write control section 30, remaining data amount test section 50, vector detection circuit 51, FREQUENCY CONTROL part 60 and variable frequency oscillating part 70 constitute PLL 80, this PLL 80 converges to suitable value with phase difference.
Constitute FREQUENCY CONTROL part 60 by conversion portion 61, full adder 62, latch cicuit 63 and amplitude limiter 64.Conversion portion 61 has the table that remaining data amount Δ S is converted to correction amount delta T.Conversion portion 61 is according to this table with from the instruction works of vector detection circuit 51, be converted to correction amount delta T with current residual data volume Δ S that will 50 outputs from remaining data amount test section.Fig. 4 shows the converted contents of being carried out by vector detection circuit 51 and conversion portion 61.Fig. 5 (a) shows the pattern that remaining data amount Δ S changes when in addition the correction amount delta T of conversion portion 61 output " 0 " to 5 (d).
Shown in Fig. 5 (a), and remaining data amount Δ S increase (Valid_1＜Valid_0＜Valid_ptr).In addition, the currency of the value representation remaining data amount Δ S of pointer Valid_ptr, and cross over and surpass suitable value " 4 " (according to the example among Fig. 4, Valid_ptr=5 and 6).In the case, vector detection circuit 51 is issued conversion portion 61 is used to increase FREQUENCY CONTROL information with output correction amount delta T with instruction.As a result, the positive correction amount Δ T of the difference of its sizableness of conversion portion 61 output between current residual data volume Δ S and suitable value " 4 ".Fig. 5 (c) shows the situation that current residual data volume Δ S reaches and remain on the upper limit " 7 ".In the case, the positive correction amount Δ T (Δ T=+3 in this example) of the difference of its sizableness of conversion portion 61 output between current residual data volume Δ S and suitable value " 4 ", and irrelevant with the changing pattern of up to now remaining data amount Δ S.Our hypothesis detects the upper limit " 7 " thereby as remaining data amount Δ S output positive correction amount Δ T=+3, detects the upper limit " 7 " thereafter once more.In the case, remaining data amount Δ S may not can increase.Only because remaining data amount Δ S equals the upper limit " 7 ", so export positive correction amount Δ T=+3 once more.
On the other hand, shown in Fig. 5 (b), remaining data amount Δ S minimizing (Valid_1＞Valid_0＞Valid_prt).In addition, the currency of the value representation remaining data amount Δ S of pointer Valid_ptr, and drop to and be lower than suitable value " 4 " (according to the example among Fig. 4, Valid_ptr=3 and 2).In the case, vector detection circuit 51 is issued conversion portion 61 is used to reduce FREQUENCY CONTROL information with output correction amount delta T with instruction.As a result, the negative correcting quantity Δ T of the difference of its sizableness of conversion portion 61 output between current residual data volume Δ S and suitable value " 4 ".Fig. 5 (d) shows the situation that current residual data volume Δ S reaches lower limit " 0 ".In the case, conversion portion 61 output negative correcting quantity Δ T (Δ T=-3 in this example), and irrelevant with the changing pattern of remaining data amount Δ S up to now.
When remaining data amount Δ S represents other state beyond the above-mentioned state, the current state of vector detection circuit 51 indication conversion portions 61 holding frequency control informations.In the case, conversion portion 61 outputs " 0 " are as correction amount delta T.In brief, when remaining data amount test section 50 detected remaining data amount Δ S change from suitable value towards higher limit or from suitable value when lower limit changes, perhaps when remaining data amount Δ S reaches higher limit shown in Fig. 5 (c) or the lower limit shown in Fig. 5 (d), FREQUENCY CONTROL part 60 emending frequency control information y are so that make remaining data amount Δ S get back to suitable value.More particularly, S begins to change towards higher limit from suitable value shown in Fig. 5 (a) when remaining data amount Δ, or begins from suitable value when lower limit changes FREQUENCY CONTROL part 60 emending frequency control information y shown in Fig. 5 (b).
The details of the processing of carrying out by remaining data amount test section 50, vector detection circuit 51 and conversion portion 61 described above.
Full adder 62 and latch cicuit 63 provide the means according to correction amount delta T emending frequency control information y.At first, according to being kept at current FREQUENCY CONTROL information y in the latch cicuit 63 and the correction amount delta T that provides from conversion portion 61, the operation that full adder 62 is carried out by following equation (1) expression.When with door 103 master clock φ being offered latch cicuit 63, latch cicuit 63 latchs as the new FREQUENCY CONTROL information y from the dateout of full adder 62.Amplitude limiter 64 is restricted to FREQUENCY CONTROL information y and is less than or equal to the given upper limit.Limited FREQUENCY CONTROL information y is offered variable frequency oscillating part 70.
y＜-y+ΔT ...(1)
Configuration latch cicuit 63 is to carry out initialization.When sampling frequency converter began to operate, with the initial value y of FREQUENCY CONTROL information, the value that promptly is expressed from the next was given latch cicuit 63.
The y=constant * (f1/f2) ... (2)
Wherein, f1 represents first sample frequency before the sample frequency conversion, and f2 represents second sample frequency after the sample frequency conversion.
Variable frequency oscillating part 70 by full adder 71, latch cicuit 72, produce circuit 75 with door 73, down counter 74, enable signal and latch cicuit 76 constitutes.Full adder 71 will be from the FREQUENCY CONTROL information y of FREQUENCY CONTROL part 60 output and interpolation than Δ t (that is, from the fractional part of the dateout of latch cicuit 72) addition, and the output result.FREQUENCY CONTROL information y and interpolation are carried out above-mentioned " operation that the phase place of data that will interpolation is advanced gradually " than the operation of Δ t addition.When providing master clock φ with door 73, latch cicuit 72 latchs the dateout from full adder 71, and the output result.Default data are offered down counter 74, and described default data are promptly by will deducting the value that " 1 " obtains from the integer part of the dateout that latchs circuit 72.When determining (assert) enable signal EN (will describe), down counter 74 is synchronous with master clock φ, thereby default data are taken into as count value.Thereafter, down counter 74 carries out countdown according to master clock φ.Enable signal produces circuit 75 and for example is made of latch cicuit.When the count value of down counter 74 became " 0 ", enable signal generation circuit 75 and master clock φ were synchronously to determine enable signal EN.In the above-mentioned 63 initialized whiles of latch cicuit, enable signal is produced circuit 75 initialization.When enable signal being produced circuit 75 initialization, the configuration enable signal produces circuit 75, so that irrelevantly determine enable signal EN with the count value of down counter 74.When having determined enable signal EN, latch cicuit 76 latchs the fractional part from the dateout of latch cicuit 72, and it is outputed to interpolation part 200A as interpolation than Δ t.When having determined enable signal EN, with door 101 master clock φ is outputed to as written request signal WR and to write control section 30.With door 104 master clock φ is outputed to interpolation part 200A as data input enable signal IE.When having determined enable signal EN, master clock φ is offered latch cicuit 72, remaining data amount test section 50 and latch cicuit 63 with door 73,102 and 103.When with door 73 master clock φ being offered latch cicuit 72, the integer part of the data of storage can increase by 2 or more in the latch cicuit 72.As described above with reference to Figure 3, this phase place that is illustrated in the data of obtaining among the interpolation part 200A is current unlike the data D that is kept in the shift register 201 mPhase place leading.In the case, down counter 74 carries out the countdown of a plurality of clocks.Thereafter, interpolation part 200A accepts the required new data of interpolative operation from equipment formerly, and this new data is input to shift register 201.
Below described the structure of transmission control unit (TCU) 100A in detail.
The operation of embodiment is below described.
When beginning to operate, carries out sampling frequency converter initialization operation.The initial value y of the FREQUENCY CONTROL information that this initialization operation provides above-mentioned equation (2) writes the latch cicuit 63 among the transmission control unit (TCU) 100A.And then during initialization operation, enable signal produces circuit 75 and determines enable signal EN.Therefore, the FREQUENCY CONTROL information y that will write latch cicuit subsequently writes latch cicuit 72 via amplitude limiter 64 and full adder 71.The integer part of writing the FREQUENCY CONTROL information y in the latch cicuit 72 is defaulted in the down counter 74.Thereafter, down counter 74 carries out countdown according to master clock φ.When the count value of down counter 74 became " 0 ", enable signal produced circuit 75 and determines enable signal EN.As a result, with master clock φ by offering latch cicuit 72 with door 73.At this moment, will write latch cicuit 72 from the dateout of full adder 71.This dateout is by will be from the FREQUENCY CONTROL information of FREQUENCY CONTROL part 60 output and the result that obtains from the fractional part addition of the dateout of latch cicuit 72.To default in the down counter 74 from the integer part of the dateout that latchs circuit 72.Fractional part is write in the latch cicuit 76 than Δ t as interpolation.As the result who repeats these operations, produce enable signal EN with density average time corresponding to FREQUENCY CONTROL information.In addition, produced with the interpolation that changes corresponding to the speed of this FREQUENCY CONTROL information than Δ t.
When producing enable signal EN, master clock φ by with door 101 and 104.Master clock φ offered as written request signal WR and data input enable signal IE write control section 30 and interpolation part 200A.And, when producing enable signal EN, master clock φ by with door 102 and 103.Master clock φ offered remaining data amount test section 50 and latch cicuit 63 thereafter.
When data being imported enable signal IE and offer interpolation part 200A, interpolation part 200A has deposited the input data and has carried out convolution corresponding to interpolation than the coefficient string that is used for interpolative operation of Δ t n simultaneously.With the data P of this interpolative operation result as second sample frequency kOutput.
When written request signal WR being offered when writing control section 30, writing control section 30 increases write addresses, and written request signal WR is offered FIFO 10.As a result, will write among the FIFO 10 zone from the dateout of interpolation part 200A by the write address appointment.
Clock LRCK is offered interface 300A from external equipment, and correspondingly export reading request signal RR.According to this reading request signal RR, read control section 40 address of reading of the earliest the data of designated store in FIFO 10 is offered FIFO10 together with reading request signal RE.As a result, read the earliest data from FIFO 10, and provide it to interface 300A.
Has such situation: promptly, determined enable signal EN and by providing master clock φ with door 102.In the case, remaining data amount test section 50 is according to the write address of the up-to-date FIFO of offering 10 and the difference of reading between the address were obtained remaining data amount Δ S at that time.When definite enable signal EN, carry out the operation of obtaining remaining data amount Δ S.The remaining data amount Δ S that pointer Valid_ptr storage remaining data amount test section 50 is obtained.When the value of pointer Valid_ptr is different from the value of pointer Valid_0, give pointer Valid_0 with the value of pointer Valid_ptr.Give pointer Valid_1 with the value that keeps among the pointer Valid_0 up to now.
According to pointer Valid_ptr, Valid_0 and Valid_1, vector detection circuit 51 is dealt into conversion portion to determine that increasing or reducing FREQUENCY CONTROL information still is the maintenance currency with instruction.According to this instruction, the remaining data amount Δ S that conversion portion 61 will provide from remaining data amount test section 50 (=Valid_ptr) be converted to correction amount delta T.As a result, output calibration amount Δ T as described below.We suppose that remaining data amount Δ S increases, and the currency of remaining data amount Δ S surpasses suitable value " 4 ".In the case, output positive correction amount Δ T makes it to equal poor between current residual data volume Δ S and the suitable value " 4 ".When remaining data amount Δ S was set to the upper limit " 7 ", output was set to the positive correction amount Δ T of " 3 ".On the other hand, we suppose that remaining data amount Δ S reduces, and the currency of remaining data amount Δ S is less than suitable value " 4 ".In the case, output negative correcting quantity Δ T makes it to equal poor between current residual data volume Δ S and the suitable value " 4 ".When remaining data amount Δ S was set to lower limit " 0 ", output was set to the negative correcting quantity Δ T of " 3 ".In other cases, output is set to the correction amount delta T of " 0 ".
Correction amount delta T that full adder 62 will be exported in this way and the current FREQUENCY CONTROL information y addition that is stored in the latch cicuit 63.According to from the master clock φ of door 103, this result is write latch cicuit 63 as new FREQUENCY CONTROL information y.Therefore, when output positive correction amount Δ T, FREQUENCY CONTROL information y increases.When output negative correcting quantity Δ T, FREQUENCY CONTROL information y reduces.When output was set to the correction amount delta T of " 0 ", FREQUENCY CONTROL information y kept currency.
In this way, FREQUENCY CONTROL part 60 increases or reduces FREQUENCY CONTROL information y according to correction amount delta T.Variable frequency oscillating part 70 is according to the FREQUENCY CONTROL information y output enable signal EN that adjusts.Increase the average that FREQUENCY CONTROL information y has improved master clock φ, described master clock φ sent in time period till beginning when count value is reset to " 0 " from default down counter 74 time.Therefore, the mean time rate of enable signal EN descends.Therefore, the speed of data being write FIFO 10 reduces.On the contrary, reduce the mean time rate that FREQUENCY CONTROL information y has improved enable signal EN.The speed of data being write FIFO 10 improves.
When being lower than data reading rate (, the frequency of reading request signal RR or time rate), remaining data amount Δ S reduces when data writing rate in FIFO 10 (that is, the frequency of enable signal EN or time rate).When negative correcting quantity Δ T occurring in the minimizing process, FREQUENCY CONTROL information y reduces.The data writing rate improves.On the contrary, when the data writing rate was higher than the data reading rate in FIFO 10, remaining data amount Δ S increased.When positive correction amount Δ T occurring in the increase process, FREQUENCY CONTROL information y increases.The data writing rate reduces.Because increase or minimizing according to remaining data amount Δ S provide PLL control, so writing rate is followed reading rate in FIFO.Remaining data amount Δ S in FIFO is converged to suitable value " 4 ".
Fig. 6 is the exemplary time dependent sequential chart of remaining data amount Δ S that illustrates according to present embodiment.In Fig. 6, satisfy such condition by the interval of label Δ 1 expression, that is, remaining data amount Δ S increases gradually, at the point of Δ S=" 6 ", concern that Valid_1＜Valid_0＜Valid_ptr is effective, and Valid_ptr is greater than suitable value " 4 ".Therefore, at this point, produce positive correction amount Δ T (suitable value=+ 2 of this positive correction amount Δ T=Valid_ptr-) to increase FREQUENCY CONTROL information y and to reduce data input speed among the FIFO 10.Thereafter, because do not satisfy the condition that produces plus or minus correction amount delta T, so, produce the correction amount delta T that is set to " 0 ".At the point of being represented by label A2, remaining data amount Δ S reaches the upper limit " 7 ".At this point, satisfy the condition that produces positive correction amount Δ T.Therefore, produce positive correction amount Δ T (suitable value=+ 3 of this positive correction amount Δ T=Valid_ptr-) to reduce the data input speed among the FIFO 10.
According to example shown in Figure 6, positive correction amount Δ T occurs twice.Thus, the remaining data amount Δ S that disperses in suitable value " 4 " top gets back to suitable value " 4 ".By interval that label A3 represent satisfy such condition, promptly thereafter,, remaining data amount Δ S is with the time-sloped minimizing more slow than the interval of being represented by label A1, at the point of Δ S=" 3 ", concern that Valid_1＞Valid_0＞Valid_ptr is effective, and Valid_ptr is less than suitable value " 4 ".Therefore, at this point, produce negative correcting quantity Δ T (value=-1 that this negative correcting quantity Δ T=Valid_ptr-is suitable) to reduce FREQUENCY CONTROL information y and to improve data input speed among the FIFO 10.The absolute value of the correction amount delta T that produce this moment is less than the absolute value of the correction amount delta T that produces in the moment of being represented by above-mentioned label A1 or A2.Therefore, the action intensity that has occurred making remaining data amount Δ S get back to suitable value " 4 " (for convenience's sake, below this intensity is called to appropriate value recurrence power).This strength ratio the termination in the interval of representing by label A1 constantly or by label A2 represent the moment produced a little less than the recurrence power of appropriate value.Yet in the interval of being represented by label A3, the amplitude of variation of remaining data amount Δ S is decay fully.Expect that this recurrence power to appropriate value is little as this degree.Its reason is: when the variation of remaining data amount Δ S decayed fully, the too big appropriate value intensity of getting back to made remaining data amount Δ S disperse from suitable value " 4 " on the contrary.
Be right after after the interval of being represented by label A3, remaining data amount Δ S repeats vibration in the scope of suitable value " 4 " ± 1.This is because the conversion between the data input and output constantly in FIFO 10.Data are input to FIFO 10 causes Δ S to become suitable value " 4 "+1.Cause Δ S to become suitable value " 4 "-1 from data of FIFO 10 outputs.Under this state, in FIFO 10 the data input speed fully and the data output speed synchronous.Remaining data amount Δ S in FIFO 10 is stable.
Though it is not shown among Fig. 6, because for example the frequency of the reading request signal RR that provides from interface 300A departs from from the initial second desired sample frequency f2, so FREQUENCY CONTROL information can comprise invalid initialization value.In the case, remaining data amount Δ S departs from from suitable value fully.Can repeatedly continuously the upper limit " 7 " or lower limit " 0 " detection be remaining data amount Δ S.In the case, when the upper limit " 7 " (lower limit " 0 ") being detected, produce positive correction amount Δ T=+3 (negative correcting quantity Δ T=-3) for remaining data amount Δ S.In this way, FREQUENCY CONTROL information is fast near the value that is suitable for the frequency of reading request signal RR.Thereafter, according to the operation shown in Fig. 6, S converges to suitable value with remaining data amount Δ.
As mentioned above, this embodiment produces plus or minus correction amount delta T, thereby, when remaining data amount Δ S demonstrates the state that departs from suitable value and when remaining data amount Δ S departs from fully, make remaining data amount Δ S get back to suitable value.In addition, generation value " 0 " is as correction amount delta T.Only make remaining data amount Δ S get back to the correction amount delta T of suitable value necessary interval just the generation.Remaining data amount Δ S1 can be adjusted to suitable value rapidly and can not produce remaining data amount Δ S over time.Therefore, can realize to make hardly the quality data transmission of wave distortion.
＜the second embodiment 〉
Fig. 7 is the block diagram that illustrates according to second embodiment of the sampling frequency converter of first scheme of the present invention.According to second embodiment, interface 300B is before transmission control unit (TCU) 100B, and interpolation part 200B is after transmission control unit (TCU) 100B.Interface 300B not only offers transmission control unit (TCU) 100B with the written request signal WR but also the data Din that will have first sample frequency.Dispose interpolation part 200B in the mode that is similar to interpolation part 200A.Interpolation part 200B uses built-in shift register to preserve from the serial data of the specified quantity in the past that FIFO 10 presents.Be similar to above-mentioned first embodiment, interpolation part 200B will carry out convolution with the interpolation that provides from the latch cicuit 76 coefficient string that be used for interpolative operation and the described serial data more corresponding than Δ t.With the synchronous moment of output clock CKout with second sample frequency, interpolation part 200B produces the dateout P as convolution results kAs described below, the structure of transmission control unit (TCU) 100B is different from the structure of transmission control unit (TCU) 100A.The written request signal WR that interface 300B directly will have a frequency identical with first sample frequency offers and writes control section 30.Replace among first embodiment with door 101 and 104, provide reading request signal to produce part 105 at this and produce reading request signal RR.To offer reading request signal from the enable signal EN that enable signal produces circuit 75 output and produce part 105 and interpolation part 200B.The enable signal EN that offers interpolation part 200B is as data output enable signal, and the data that this data output enable signal allows to have second sample frequency are carried out interpolative operation and output.Others are identical with the description among above-mentioned first embodiment.
Transmission control unit (TCU) 100B is synchronized with the master clock φ with frequency identical with second sample frequency, and provides PLL control so that remaining data amount Δ S is stable.During this control and treatment, determine enable signal EN with the time density that is synchronized with master clock φ, and enable signal EN is corresponding to first sample frequency.When having determined enable signal EN, interpolation part 200B is being synchronized with the moment output read request enable signal RRE of output clock CKout.When having determined enable signal EN, when exporting read request enable signal RRE thereafter, reading request signal generation part 105 outputs to reading request signal RR reads control section 40.At this moment, read control section 40 and will read the address and add " 1 ", and output reading request signal RE.As a result, read not read data the earliest among the FIFO 10, and provide it to interpolation part 200B.Interpolation part 200B will write the first order of shift register from the data that FIFO 10 provides.Existing data shift in the shift register to subsequently level, is abandoned the data in the last level.According to the generation of output clock CKout, interpolation part 200B uses the serial data preserved in the shift register and carries out interpolative operation with the interpolation coefficient string that is used for interpolative operation more corresponding than Δ t.Interpolation part 200B and output clock CKout synchronously export the data with second sample frequency as the interpolative operation result.
Above-mentioned first embodiment provides PLL control, makes that the data input speed is followed the data output speed in FIFO 10.Second embodiment provides PLL control, makes that the data output speed is followed the data input speed in FIFO 10.This PLL control is provided in the same manner as in the first embodiment.Therefore, second embodiment also provides the effect that is provided with first embodiment identical effect.
Sampling frequency converter in the alternative plan of the present invention is described with reference to the accompanying drawings.
Fig. 8 is the block diagram that illustrates according to the structure of the sampling frequency converter of this embodiment.In Fig. 8, anti-aliasing (anti-aliasing) LPF 1 is such circuit: promptly, it is handled to prevent overlapping noise occurring in the sample frequency transition period for input audio data provides LPF.Receive the input audio data of first sample frequency with 48kHz according to the sampling frequency converter of present embodiment.Select second sample frequency in 9 kinds of sample frequencys of sampling frequency converter between from 8kHz to 48kHz, and the input audio data that receives is converted to the voice data of second sample frequency that is used to export.Anti-aliasing LPF 1 get selected second sample frequency half as cut-off frequency, and will from input audio data, remove more than or equal to the component of this cut-off frequency.
The fast sampler 2 of 8 multiplications is such circuit: promptly, it carries out 8 multiplication speed samplings to the data of exporting from anti-aliasing LPF 1 with first sample frequency, and these data are output as the voice data with 384kHz sample frequency.The fast sampler 3 of 1/L demultiplication is such circuit: promptly, it utilizes linear interpolation to come the voice datas with 384kHz sample frequency from fast sampler 2 outputs of 8 multiplications are carried out the sampling of 1/L demultiplication speed, and exports the voice data with second sample frequency.Selected second sample frequency has determined the factor that slows down and sample.
FIFO (first in first out) the 4th is used to store the first-in first-out buffer from the voice data with second sample frequency of 1/L demultiplication speed sampler 3 outputs.According to the FIFO reading request signal, FIFO 4 begins sequentially to export according to first-in first-out rule the voice data of storage from first voice data the earliest.Serial line interface 5 is such circuit: promptly, its provide control with the voice data that will have second sample frequency offer after equipment.The data request signal LRCK and the bit clock BCLK of the equipment after the leisure in the future offer serial line interface 5.Data request signal LRCK has the frequency identical with second sample frequency.When data request signal LRCK was offered serial line interface 5, the FIFO reading request signal is offered FIFO 4 to serial line interface 5 and writing rate is adjusted circuit 6.Serial line interface 5 will be converted to serial data SDO from the voice data of FIFO 4 corresponding outputs, and by each and the bit clock BCLK that makes serial data SDO synchronously serial data SDO is offered after equipment.
Writing rate is adjusted circuit 6 and is produced the FIFO written request signal, and it is outputed to FIFO4 and linear interpolation coefficient generation circuit 7.The FIFO written request signal has rate or density when identical with mean time rate that produces the FIFO reading request signal or density, and is synchronized with the master clock φ of 384kHz.More particularly, be synchronized with master clock φ, writing rate is adjusted circuit 6 and is depended on that by accumulative total the FREQUENCY CONTROL information of second sample frequency produces phase information.When overflowing on phase information, writing rate is adjusted circuit 6 and is produced the FIFO written request signal.On the other hand, writing rate is adjusted circuit 6 increases or reduces FREQUENCY CONTROL information according to valid data amount (that is, among the FIFO 4 not the quantity of read data), and the time rate of adjustment FIFO written request signal.In this way, produce the FIFO written request signal with the time rate identical with the time rate of FIFO reading request signal.Therefore, the valid data amount among the FIFO 4 converges to suitable value.Phase information when the linear interpolation coefficient produces circuit 7 according to generation FIFO written request signal is obtained the linear interpolation coefficient, and this linear interpolation coefficient is offered 1/L demultiplication speed sampler 3.
According to this embodiment, sequentially upgrade phase information by being synchronized with the calculation process that master clock φ carries out.Phase information during according to generation FIFO written request signal produces the linear interpolation coefficient.Control FIFO written request signal, thus make it rate when identical with the FIFO reading request signal and produced, and produce the FIFO written request signal in the moment that is being synchronized with master clock φ.Even shake occurred when producing data request signal LRCK and FIFO reading request signal, 1/L demultiplication speed sampler 3 has also produced the voice data with second sample frequency.With the data that produce by FIFO 4 and serial line interface 5 offer after equipment.
The overview of this embodiment has been described.
Fig. 9 is the block diagram that the detailed structure of the 1/L demultiplication speed sampler 3 in the sampling frequency converter of diagrammatic illustration is shown.Figure 10 illustrates the block diagram that writing rate is adjusted the detailed structure of circuit 6.Below with reference to the sampling frequency converter of these figure detailed descriptions according to this embodiment.
1/L demultiplication speed sampler 3 at first will be described.In Fig. 9, interim 2 grades of FIFO 31 are made of 2 grades of FIFO of L passage and 2 grades of FIFO of R passage.When the master clock φ of 384kHz was provided, interim 2 grades of FIFO, 31 inputs were from the L passage and the R channel audio data of fast sampler 2 outputs of 8 multiplications, and preservation two the up-to-date voice datas corresponding with these passages.Operating data storage area 32 is made of register 32a and 32b, the voice data at these interpolated point two ends that during register 32a and the 32b storage linear interpolation interpolated point are clipped in the middle.When producing the FIFO written request signal, register 32a stores the L passage and the R channel audio data of being stored in the second level of interim 2 grades of FIFO 31.Register 32b stores the L passage and the R channel audio data of being stored in the first order of interim 2 grades of FIFO 31.The voice data A and the B that are stored among register 32a and the 32b are used for interpolative operation, in the hope of going out to have the voice data of second sample frequency.
Subtracter 33, multiplier 34, adder 35 and register 36 provide such means: promptly, carry out interpolative operation obtaining voice data with second sample frequency according to voice data A and B, and the output result.Under timesharing control, during till when from generation FIFO written request signal the time, beginning to next written request signal of generation, these circuit are carried out interpolative operations obtaining the voice data with second sample frequency at each passage in L and the R passage, and the result is offered FIFO 4 by register 36.
More particularly, deduct the voice data A that is stored among the register 32a of operating data storage area 32 among the L channel audio data B of subtracter 33 from the register 32b that is stored in operating data storage area 32, and export the data B-A that obtains.Multiplier 34 usefulness just multiply by data B-A from the linear interpolation factor alpha of linear interpolation coefficient generation circuit 7 outputs, and dateout (B-A) * α.The linear interpolation factor alpha is such numerical value: promptly, its expression along the time which point of axle between voice data A and B should use interpolative operation to obtain voice data with second sample frequency.The method of calculating the linear interpolation factor alpha will be described after a while.Adder 35 will be from the L channel audio data A addition multiplier 34 data (B-A) * α that obtains and the register 32a that is stored in operating data storage area 32.Register 36 is preserved A+ as a result (the B-A) * α of addition as the L channel audio data with second sample frequency.Be the processing that example has been described subtracter 33, multiplier 34, adder 35 and register 36 with the L passage.Carry out similarly processing for the voice data of R passage.Register 36 saving results.
Referring now to Figure 10, will describe writing rate and adjust circuit 6.FIFO 4 is accumulation 16 grades of FIFO of the voice data with second sample frequency of generation like this.Write pointer (writepointer) the 601st, such circuit: promptly, when the FIFO written request signal occurs, write address is added " 1 " and write address is offered FIFO 4.Thereafter, write pointer 601 is write the zone by the write address appointment among the FIFO 4 with the current L passage that is provided by register 36 and R channel audio data.Read pointer 602 is such circuit: promptly, when the FIFO reading request signal occurs, will read the address and add " 1 " and will read the address and offer FIFO 4.Thereafter, read pointer 602 from FIFO 4 by reading to read L passage and R channel audio data in the current specified zone, address, and voice data is offered serial line interface 5.
Valid data pointer 603 is such circuit: promptly, it deducts the read address of output from read pointer 602 from output from the write address of write pointer 601, and output is as the valid data amount of subtraction result.The valid data scale shows the not read data quantity in the voice data of writing FIFO 4.
The valid data amount that 604 monitorings of vector detection circuit are exported from valid data pointer 603, and export such vector up/down information: promptly, this vector up/down information representation is applied to following which kind of pattern the valid data amount over time.(a) the valid data amount increases.(b) the valid data amount reduces.(c) the valid data amount of Zeng Jiaing has been changed into and has been tending towards reducing.(d) the valid data amount of Jian Shaoing has been changed into and has been tending towards increasing.
FREQUENCY CONTROL part 610 is provided for producing the means of FREQUENCY CONTROL information Δ y, and this FREQUENCY CONTROL information Δ y determines the frequency of FIFO written request signal.It is the circuit of cumulative frequency control information Δ y when master clock φ occurring that written request signal produces part 620.When overflowing on phase information y (value that promptly adds up), written request signal produces part 620 and produces the FIFO written request signal.Next coming in order are described the structure of these circuit.
FREQUENCY CONTROL part 610 is made of Δ T table 611, adder 612, latch 613 and addition value table 614.The storage of addition value table 614 is corresponding to the initial value of the FREQUENCY CONTROL information Δ y of various second sample frequencys.Written request signal produces part 620 and can be synchronized with the master clock φ of 384kHz and repeat the cumulative frequency control information.In the case, y is configured to such value with FREQUENCY CONTROL information Δ, thereby makes phase information y as aggregate-value to overflow on the time density that is equivalent to second sample frequency.More particularly, we suppose that the span of phase information y is set to f2 from 0 to M-1 and second sample frequency.FREQUENCY CONTROL information Δ y be initialized as following value thereafter.
Δy＝M/(384kHz/f2) ...(3)
＝M/L
Latch 613 can be initialised.When sampling frequency converter is started working, from addition value table 614 reading frequency control information Δ y.Should be noted that, FREQUENCY CONTROL information Δ y with by after the second sample frequency f2 of device request be associated.At this moment, latch 613 is initialized as FREQUENCY CONTROL information Δ y.Then, when producing the master clock φ of 384kHz, just use from the FREQUENCY CONTROL information Δ y in the dateout renewal latch 613 of adder 612.
Have such situation, that is, cause the valid data amount the FIFO 4 may depart from suitable value owing to exported incorrect FREQUENCY CONTROL information Δ y from latch.In the case, Δ T table 611 and adder 612 provide the means that FREQUENCY CONTROL information Δ y are corrected to suitable value.Δ T table 611 is used for the combination of valid data amount and vector up/down is converted to correction amount delta T.Figure 11 shows the content of the conversion process of being carried out by Δ T table 611.
As shown in figure 11, vector up/down can represent that the valid data amount reduces.When effective data volume during less than suitable value " 8 ", poor corresponding between valid data amount and the suitable value " 8 " of Δ T table 611 output positive correction amount Δ T, the absolute value of this positive correction amount Δ T.Adder 612 is increased FREQUENCY CONTROL information Δ y with positive correction amount Δ T mutually with current FREQUENCY CONTROL information Δ y.This has improved the time density of FIFO written request signal, reduces thereby suppressed the valid data amount.And vector up/down can represent that the valid data amount increases.When effective data volume during greater than suitable value " 8 ", poor corresponding between valid data amount and the suitable value " 8 " of Δ T table 611 output negative correcting quantity Δ T, the absolute value of this negative correcting quantity Δ T.Adder 612 is reduced consequent FREQUENCY CONTROL information Δ y with negative correcting quantity Δ T mutually with current FREQUENCY CONTROL information Δ y.This has reduced the time density of FIFO written request signal, increases thereby suppressed the valid data amount.
Written request signal produces part 620 and is made of adder 621 and latch 622.The FREQUENCY CONTROL information Δ y that adder 621 will be provided by FREQUENCY CONTROL part 610 and from the current phase information y addition of latch 622 outputs.When master clock φ was provided, latch 622 input was from the dateout of adder 621, and it is saved as new phase information y.Figure 12 shows the operation that written request signal produces part 620.As shown in figure 12, when producing master clock φ, phase information y is that unit increases with Δ y.When the accumulated result of FREQUENCY CONTROL information Δ y caused the coboundary M-1 that has surpassed phase information y, latch 622 was stored as new phase information y with plussage β.When phase information y overflowed on by this way, the MSB of the phase information y that latch 622 is comprised dropped to " 0 " from " 1 ".The trailing edge of this MSB is offered FIFO 4, write pointer 601 and linear interpolation coefficient generation circuit 7 as the FIFO written request signal.
Linear interpolation coefficient among Fig. 9 produces the value β that circuit 7 is preserved among Figure 12, that is, and and at the phase information y of the time point that has produced the FIFO written request signal from latch 622 outputs.Following equation is used for calculating the linear interpolation factor alpha according to this β.
α＝β/(M/L)
In this equation, M/L belongs to the initial value M/L of the FREQUENCY CONTROL information Δ y that is stored in the addition value table 614, and corresponding to by after equipment second sample frequency of asking.
The linear interpolation factor alpha that 3 uses of 1/L demultiplication speed sampler obtain is like this carried out the linear interpolation to the voice data with second sample frequency between data A and B.To write among the FIFO 4 by the voice data that this linear interpolation obtains.
According to above-mentioned sampling frequency converter, FREQUENCY CONTROL part 610 produces FREQUENCY CONTROL information Δ y.Written request signal produces part 620 and is synchronized with master clock φ cumulative frequency control information Δ y.When on phase information y, overflowing, produce the FIFO written request signal as accumulated result.1/L demultiplication speed sampler 3 is carried out the linear interpolation of voice data.Acquisition is as linear interpolation result's the voice data with second sample frequency, and it is write among the FIFO 4.FREQUENCY CONTROL part 610 provides control to increase or to reduce FREQUENCY CONTROL information Δ y, so that the valid data amount among the FIFO 4 is adjusted to suitable value.This need be synchronized with master clock φ and produce the FIFO written request signal with time density identical with density average time of FIFO reading request signal.Phase information y when producing the FIFO written request signal that is synchronized with master clock φ by using calculates the linear interpolation factor alpha that is used for linear interpolation.Even shake occurred when producing data request signal LRCK and FIFO reading request signal, this embodiment also can produce the voice data with second sample frequency and the influence of not shaken, and with this voice data offer after equipment.
Figure 13 shows the effect of this embodiment and the comparison between the conventional art.The utilization of traditional sampling frequency converter from after moment of equipment receiving data request signal determine interpolated point.Sampling frequency converter utilizes before the interpolated point and two voice data A afterwards and B carry out linear interpolation to obtain the voice data at interpolated point.Therefore, the influence of the shake during owing to the generation data request signal, this interpolation causes obtaining voice data X or Y.When after the voice data of equipment after reproducing the sample frequency conversion time, have the problem of wave distortion.On the contrary, this embodiment has determined the interpolated point of voice data, and the interpolated point of this voice data is that the phase information y when being synchronized with the FIFO written request signal of master clock φ according to generation obtains by linear interpolation.The influence of the shake when therefore, the position of this interpolated point is not produced data request signal.According to this embodiment, sample frequency conversion is only because linear interpolation mistake but not shake just may cause wave distortion.Therefore, compare with conventional art, this embodiment can reduce wave distortion.
Though described the embodiment of alternative plan of the present invention at this, the present invention can realize in a different manner.According to the foregoing description, for example, the input audio data with first sample frequency is carried out 8 multiplication speed samplings to produce the voice data of 384kHz.Carry out voice data that 1/L demultiplication speed sampling with generation have second sample frequency thereafter.And the sampling of available 1/L demultiplication speed replaces 8 multiplication speed samplings to carry out high order (high-level) interpolation.

Claims (10)

1. transmission control unit comprises:
The first in first out storage area, it stores the data of new input in response to written request signal, and reads and export the storage data of oldest stored in response to reading request signal;
Remaining data amount test section, it detects the remaining data amount of remaining storage data in the described first in first out storage area;
The variable frequency oscillating part, it produces enable signal with the time rate that depends on FREQUENCY CONTROL information, thereby allows to produce written request signal or reading request signal; And
The FREQUENCY CONTROL part, when the detected remaining data amount in described remaining data amount test section change from suitable value towards higher limit or from described suitable value when lower limit changes, perhaps when described remaining data amount reached described higher limit or described lower limit, described FREQUENCY CONTROL was partly proofreaied and correct described FREQUENCY CONTROL information so that make described remaining data amount get back to described suitable value.
2. transmission control unit as claimed in claim 1, wherein, when described remaining data amount begins to change from described suitable value towards described higher limit or begins from described suitable value when described lower limit changes, described FREQUENCY CONTROL is partly proofreaied and correct described FREQUENCY CONTROL information.
3. transmission control unit comprises:
The first in first out storage area, it stores the data of new input in response to written request signal, and reads and export the storage data of oldest stored in response to reading request signal;
Remaining data amount test section, it detects the remaining data amount of remaining storage data in the described first in first out storage area;
The variable frequency oscillating part, it produces enable signal with the time rate that depends on FREQUENCY CONTROL information, thereby allows to produce written request signal or reading request signal; And
The FREQUENCY CONTROL part, only begin from suitable value towards higher limit to change or begin from described suitable value when lower limit changes when the detected remaining data amount in described remaining data amount test section, described FREQUENCY CONTROL is partly proofreaied and correct described FREQUENCY CONTROL information so that make described remaining data amount get back to described suitable value.
4. sample frequency conversion equipment comprises:
The interpolation part, it compares interpolative data according to interpolation; And
The transmission control section, it is based on the data of FREQUENCY CONTROL message transmission interpolation,
Wherein, described interpolation partly comprises:
Preserve part, it sequentially receives the data with first sample frequency, and the data that receive are saved as the input serial data that is used for interpolative operation; And
The interpolative operation part, it carries out interpolative operation by using the interpolation that produces with described transmission control section than corresponding interpolation coefficient and the described input serial data of preserving in the part that is used for interpolative operation of preserving of use, thereby produce interpolative data with second sample frequency, and
Wherein, described transmission control section comprises:
The first in first out storage area, it stores the interpolative data of partly exporting from described interpolation and have described second sample frequency in response to written request signal, and reads and export the storage data of oldest stored in response to reading request signal;
Remaining data amount test section, it detects the remaining data amount of the data of storing in the described first in first out storage area;
The variable frequency oscillating part, it produces enable signal with the time rate that depends on described FREQUENCY CONTROL information, thereby allows to produce written request signal, and described variable frequency oscillating part produces the interpolation ratio that changes with the speed that depends on described FREQUENCY CONTROL information; And
The FREQUENCY CONTROL part, when the detected remaining data amount in described remaining data amount test section change from suitable value towards higher limit or from described suitable value when lower limit changes, perhaps when described remaining data amount reached described higher limit or described lower limit, described FREQUENCY CONTROL was partly proofreaied and correct described FREQUENCY CONTROL information so that make described remaining data amount get back to described suitable value.
5. sample frequency conversion equipment comprises:
The interpolation part, it compares interpolative data according to interpolation; And
The transmission control section, it arrives described interpolation part based on FREQUENCY CONTROL information with described transfer of data,
Wherein, described interpolation partly comprises:
Preserve part, it sequentially receives the data with first sample frequency from described transmission control section, and the data that receive are saved as the input serial data that is used for interpolative operation; And
The interpolative operation part, it carries out interpolative operation by using the interpolation that produces with described transmission control section than corresponding interpolation coefficient and the described input serial data of preserving in the part that is used for interpolative operation of preserving of use, thereby produce interpolative data with second sample frequency, and
Wherein, described transmission control section comprises:
The first in first out storage area, it is stored in response to written request signal from data input and that have described first sample frequency of equipment formerly, and read the storage data of oldest stored in response to reading request signal, and export the storage data of described oldest stored to described interpolation part;
Remaining data amount test section, it detects the remaining data amount of the data of storing in the described first in first out storage area;
The variable frequency oscillating part, it produces enable signal with the time rate that depends on described FREQUENCY CONTROL information, thereby allows to produce written request signal, and described variable frequency oscillating part produces the interpolation ratio that changes with the speed that depends on described FREQUENCY CONTROL information; And
The FREQUENCY CONTROL part, when the detected remaining data amount in described remaining data amount test section change from suitable value towards higher limit or from described suitable value when lower limit changes, perhaps when described remaining data amount reached described higher limit or described lower limit, described FREQUENCY CONTROL was partly proofreaied and correct described FREQUENCY CONTROL information so that make described remaining data amount get back to described suitable value.
6. sample frequency conversion equipment comprises:
The interpolation part, it is according to the interpolation coefficient interpolative data; And
The transmission control section, it is based on the data of FREQUENCY CONTROL message transmission interpolation,
Wherein, described interpolation partly comprises:
Preserve part, it sequentially receives the data with first sample frequency, and the data that receive are saved as the input serial data that is used for interpolative operation; And
The interpolative operation part, it carries out interpolative operation by using the interpolation coefficient and the described input serial data of preserving in the part that is used for interpolative operation of preserving of use that are produced by described transmission control section, thereby produces the interpolative data with second sample frequency, and
Wherein, described transmission control section comprises:
The first in first out storage area, it stores the interpolative data of partly exporting from described interpolation and have described second sample frequency in response to written request signal, and reads and export the storage data of oldest stored in response to reading request signal;
Remaining data amount test section, it detects the remaining data amount of the data of storing in the described first in first out storage area;
FREQUENCY CONTROL information generation section, its generation are used for controlling effectively the FREQUENCY CONTROL information that the remaining data amount is got back to suitable value;
Written request signal produces part, and it produces described written request signal in the moment that obtains by the described FREQUENCY CONTROL information of accumulative total; And
Interpolation coefficient produces part, and it produces described interpolation coefficient in the moment that produces described written request signal.
7. sample frequency conversion equipment as claimed in claim 6, wherein, described written request signal produces part and produces written request signal, described written request signal synchronous with master clock and have the time rate and described reading request signal the mean time rate identical.
8. sample frequency conversion equipment comprises:
The first storage part, the data of the specified quantity of its storage order ground input;
The second storage part, it stores the data of new input in response to written request signal, and sequentially reads the data of oldest stored in response to reading request signal;
The writing rate adjustment member, it produces written request signal, described written request signal and master clock synchronously and have the time rate and described reading request signal the mean time rate identical;
Interpolation coefficient produces part, and interpolation coefficient is calculated in its generation corresponding to described written request signal constantly; And
The interpolative operation part, it carries out interpolative operation by using described interpolation coefficient to produce part in the generation interpolation coefficient that calculates constantly and the data that use is stored in described first storage part of described written request signal, and will offer the described second storage part by the data that described interpolative operation obtains.
9. sample frequency conversion equipment as claimed in claim 8, wherein, described writing rate adjustment member comprises:
Valid data amount test section, it detects the valid data amount of remaining storage data bulk in described second storage part of expression;
The written request signal control section, thus the operation that it is carried out and master clock is synchronous produces with the periodically variable phase information corresponding to the speed of described FREQUENCY CONTROL information, and the written request signal of the cycle synchronisation of its generation and described phase information; And
FREQUENCY CONTROL part, its control frequency control information be so that converge on suitable value with described valid data amount, and
Wherein, described interpolation coefficient produces part and constantly calculates described interpolation coefficient according to described phase information in the generation of described written request signal.
10. sample frequency conversion equipment as claimed in claim 8, also comprise the N fast sampler that doubles, the described N sample frequency that fast sampler will import data that doubles multiply by factor N (N is the integer more than or equal to 2), and will have take advantage of the input data of sample frequency offer the described first storage part, wherein, described interpolative operation part is carried out the linear interpolation computing to the input data that are stored in described first storage part.
CNB2006100580286A 2005-02-24 2006-02-24 Data transmission controller and sampling frequency converter Expired - Fee Related CN100521532C (en)

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CN102694640A (en) * 2010-12-24 2012-09-26 索尼公司 Data input/output device, information processing device, and data input/output method
CN113485672A (en) * 2021-09-07 2021-10-08 苏州浪潮智能科技有限公司 Information generation method, device, equipment and medium based on FIFO memory
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