CN1151507C - Reproduced signal processing device - Google Patents
Reproduced signal processing device Download PDFInfo
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- CN1151507C CN1151507C CNB008021279A CN00802127A CN1151507C CN 1151507 C CN1151507 C CN 1151507C CN B008021279 A CNB008021279 A CN B008021279A CN 00802127 A CN00802127 A CN 00802127A CN 1151507 C CN1151507 C CN 1151507C
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/02—Analogue recording or reproducing
- G11B20/04—Direct recording or reproducing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
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Abstract
A reproduced signal processing device that is adapted to even high-speed reproduction and consumes less electric power in equalization while not lowering the equalization capability. Equalization is performed by using a frequency division clock for the operating clock. A linear interpolation unit (6) is provided to cover information missing because of the use of the frequency division clock.
Description
Technical field
The present invention relates to reproduced signal processing device, particularly relate to the simulation regenerated signal is transformed into digital reproduced signal, carry out the reproduced signal processing device that automatic equalization is handled.
Background technology
In the past, in the record regenerator of numerical information or communicator etc.,, to be used in the transmission path way or in turn to carry out the automatic equalizer that automatic equalization is handled on the terminal because the signal degradation of the error in data that the quality of the characteristic of said apparatus etc. or transmission path causes etc. in order compensating.
The 7th figure is the block scheme that is illustrated in the formation of the existing reproduced signal processing device in the record regenerator of numerical information.
Reproduced signal processing device shown in the 7th figure has analog-to-digital converter (A/D transducer) 1, digital phase synchronization circuit (digital PLL) 2 and automatic equalizer 9.Automatic equalizer 9 further has transversal filter 4 and control device 5.
Analog-to-digital converter 1 will be input to the simulation regenerated signal of reproduced signal processing device and take a sample into many-valued digital reproduced signal.Digital phase synchronization circuit 2 generate be included in above-mentioned digital reproduced signal in phase place and the consistent reference clock CK (check bit) of reference frequency composition.Transversal filter 4 carries out the wave shape equalization of digital reproduced signal to be handled.Control device 5 by being used as the error between the equalization target value of inferring from the output equalized waveform and the above-mentioned equalized waveform of transversal filter 4 balancing error and the input digit regenerated signal of transversal filter 4, above-mentioned balancing error is become minimumly like that the tap coefficient as the parameter of transversal filter 4 is controlled.
Below we illustrate the work of existing reproduced signal processing device with the 7th figure.
Scanning by unillustrated magnetic head among the figure, the numerical information of playback record on recording medium, when deciding simulation regenerated signal after the processing of frequency band when implementing emphasize to the signal read and being input to analog-to-digital converter 1, this simulation regenerated signal is transformed into many-valued digital reproduced signal.Digital reproduced signal is input to the transversal filter 4 of digital phase synchronization circuit 2 and automatic equalizer 9.Digital phase synchronization circuit 2 extracts reference clock CK from the digital reproduced signal of input, and this reference clock CK is input to analog-to-digital converter 1 and automatic equalizer 9.In analog-to-digital converter 1 and automatic equalizer 9, this reference clock CK is used as work clock.On the other hand, the simulation regenerated signal with input transversal filter 4 is transported to decoding circuit through after the equilibrium treatment in transversal filter 4.In above-mentioned equilibrium treatment, transversal filter 4 is controlled by tap coefficient as parameter.In control device 5 according to as being input to the input digit regenerated signal of transversal filter 4, the output signal of transversal filter 4 and be that the balancing error of the error between the benchmark equalization target value of inferring is set this tap coefficient at any time with this output signal.Usually, in control device 5, we use according to steepest descent method and make the square mean of balancing error become minimum LMS (lowest mean square) algorithm that calculates like that successively.
Here, we illustrate the establishing method of equalization target value.Equalization target value is the frequency characteristic that is used for setting balanced device (FIR wave filter) when carrying out digital equalising, usually, considers that the frequency characteristic of input signal is set.
The figure of an example of the digit regeneration waveform that the 8th (a) figure is expression by will be included in reference clock in the above-mentioned digit regeneration waveform and take a sample as the work clock of analog-to-digital converter 1 time.
1 or 0 the array that is presented at the top of the waveform shown in the 8th (a) figure is as an example that is recorded in the record code of the code in the recording medium, and the sampling spot below this record code is the sampling spot corresponding with this record code.In this stage, because balanced insufficient, so be a kind of state that is difficult to export the amplitude of the reproduction waveform corresponding with short code.In order to try to achieve equalization target value from the waveform shown in the 8th (a) figure, the processing of order below carrying out.
At first, for easy identification with zero during as benchmark in a positive side still in a negative side, the data of input control device 5 and the data of importing be combined (1+D processing) fully before primary sample.Sampled data after having implemented this and handling is shown in the 8th (b) figure.Again,, demonstrate and carry out just 1, the example of negative positive and negative result of determination when being 0 such judgement on the top of the waveform shown in the 8th (b) figure.In fact, by judging with reference to the uppermost position of having implemented the Wave data that 1+D handles.Here, be noted that 1 of record code shown in the 8th (a) figure and positive and negative result of determination shown in the 8th (b) figure is consistent with 0 data side by side.Therefore, when record code was consistent with positive and negative result of determination, positively the equalization target value of She Dinging became possibility.Because so-called record code is consistent with positive and negative result of determination, exactly by following the tracks of 1 and 0 data ordering, the clear in advance following waveform that what cycle will occur holding in order.
Below, in fact how expression distributes equalization target value.For each 4 samplings positive and negative result of determination is merged, this result that adds becomes 0,1, and any one value in five of 2,3,4 is distributed these values accordingly with an equalization target value.The 8th (c) figure is the figure of this appearance of expression.Shown in the 8th (c) figure, the positive and negative result's that adds is 0 to 4 corresponding to E with horizontal line A.Respectively 0 with horizontal line E, 1 with horizontal line D, 2 with horizontal line C, 3 with horizontal line B, 4 is corresponding with horizontal line A.By implementing processing as described above, correctly setting equalization target value becomes possibility.But, should be noted that here as handling and set the equalization target value precondition that record code must be consistent with positive and negative result of determination according to this.That is,, must not miss the sampling of data with being included in reference clock CK in the regenerated signal as the work clock of analog-to-digital converter 1.Observing under the restriction of this condition,, also can ignore these influences fully, setting equalization target value even if take place to form asymmetric that concave point causes owing to The noise with on CD.
As mentioned above, in existing reproduced signal processing device, can in turn carry out the deterioration that wave shape equalization handles compensating signal by the reference clock that extracts with digital phase synchronization circuit 2.
On the other hand, clear and disclosed in the disclosed 62-2724 patent gazette in 62 years in Japan at establishing method with the filter coefficient vector of the transversal filter in the Waveform equalizing device of epharmonic transversal filter, put down in Japan and disclosed the automatic equalizer of control characteristic parameter automatically in the disclosed 3-100971 patent gazette in 3 years again.
But, in existing reproduced signal processing device as described above, because the reference clock CK of the digital reproduced signal that will extract from digital phase synchronization circuit 2 supplies with analog-to-digital converter 1 and automatic equalizer 9 as work clock, carry out the regeneration of simulated data, so analog-to-digital converter 1 and automatic equalizer 9 are always worked continuously at the regeneration period that carries out simulated data.That is, to always consuming electric power continuously as the transversal filter 4 of the inscape of automatic equalizer 9 with to the control device 5 that the parameter of transversal filter 4 is controlled.Because the ratio that automatic equalizer 9 occupies is more than 2 one-tenth, can not ignore its power consumption in reproduced signal processing device again.
In recent years, in digital data regenerator, carrying out the high speed of data rate, so the high multiple of reproduction speed ground is improved.Accelerate reproduction speed, the frequency that is included in the reference clock in the digital reproduced signal with raising is relevant, and is also relevant with the frequency of the work clock that improves analog-to-digital converter 1 and automatic equalizer 9.Like this, the regeneration of high power speed is directly relevant with the increase of power consumption.Again, stable for the regeneration that makes high power speed, must guarantee the precision of signal Processing and have adequate time positively to carry out signal Processing, owing to insert the delay element that is used to guarantee to calculate figure place and guarantees figure place, circuit scale is increased.And the increase of circuit scale just the increase with power consumption is relevant.
Power consumption increases and means the temperature of carrying out integrated situation chips on LSI (large scale integrated circuit) etc. is raise.This LSI is simulation ● during chip that numeral mix to be carried, and when chip temperature rose, the characteristic of the analog element of being made up of chip etc. became and is difficult to satisfy requirements of one's work.That is, in order to give full play to the overall performance as chip, we wish that not only automatic equalizer 9 but also all power consumption of LSI all are very low.
In addition, as a kind of method of the correspondence between the regeneration that is used to realize to cut down power consumption and high power speed, we can consider to reduce the frequency of the work clock that offers automatic equalizer 9 and analog-to-digital converter 1.For example, we can be considered as work clock, are arranged, with the work clock of two divided-frequency clock as automatic equalizer 9 and analog-to-digital converter 1 two times the cycle of the reference clock CK of the digital reproduced signal that is extracted by digital phase synchronization circuit 2.When two divided-frequency is used for work clock, power consumption is reduced make an appointment with half.When therewith together, when analog-to-digital converter 1 provides frequency-dividing clock to carry out work, number of samples being reduced to offer reference clock CK half.
In addition, in existing technology, the minimizing of this number of samples can hinder the steady operation of automatic equalizer 9.Because as by the explanation of the establishing method of above-mentioned equalization target value like that, equalization target value is what to utilize when the continuity generation of the data when being included in reference clock in the digital reproduced signal analog-to-digital converter 1 is taken a sample.So in existing technology, just exist owing to make number of samples reduce half, thus the continuity of infringement data, make setting not only stable but also reliably equalization target value become very difficult, can not carry out the such problem of stable equilibrium treatment.
Summary of the invention
Purpose of the present invention is exactly in order to solve the above problems, and provides not reduce balanced performance, and cuts down power consumption, and the reproduced signal processing device with the corresponding automatic equalizer of high rapid regeneration is also arranged.
The invention provides a kind of reproduced signal processing device, have: simulating signal is taken a sample, be transformed into the analog-to-digital converter of digital signal, above-mentioned digital signal is carried out the automatic equalizer that automatic equalization is handled, the phase locking circuit of the reference clock that phase place in generating its phase place and reference frequency composition and being included in above-mentioned digital signal and reference frequency composition are consistent, make the frequency-dividing clock of the cycle integral multiple of above-mentioned reference clock with generation, this frequency-dividing clock is outputed to the frequency divider of above-mentioned analog-to-digital converter and above-mentioned automatic equalizer as work clock, it is characterized in that: above-mentioned automatic equalizer comprises, above-mentioned digital signal is carried out the transversal filter that wave shape equalization is handled, the linear interpolation treating apparatus that the shortcoming of the number of samples after with above-mentioned frequency-dividing clock the output of above-mentioned transversal filter being taken a sample is carried out interpolation, with infer equalization target value from the output of above-mentioned linear interpolation treating apparatus, and the parameter of above-mentioned transversal filter controlled, make that the balancing error as the error between the output of this equalization target value and above-mentioned transversal filter becomes minimum control device.
If according to the present invention, can obtain to realize that to by using frequency-dividing clock to replace the shortcoming of the sampling spot that reference clock obtains to carry out interpolation equal equalization performance not only can be cut down power consumption simultaneously but also can adapt to the effect of high rapid regeneration when keeping and use reference clock.
Above-mentioned linear interpolation treating apparatus comprises, the totalizer of signal after the output equalizing signal of above-mentioned transversal filter being carried out the bistable multivibrator element that the delay of 1 cycle program of frequency-dividing clock handles and will postponing processing and above-mentioned output equalizing signal addition.
If according to the present invention, can obtain to realize that to by using frequency-dividing clock to replace the shortcoming of the sampling spot that reference clock obtains to carry out interpolation equal equalization performance not only can be cut down power consumption simultaneously but also can adapt to the effect of high rapid regeneration when keeping and use reference clock.
The invention provides another kind of reproduced signal processing device, have: simulating signal is taken a sample, be transformed into the analog-to-digital converter of digital signal, above-mentioned digital signal is carried out the automatic equalizer that automatic equalization is handled, the phase locking circuit of the reference clock that phase place in generating its phase place and reference frequency composition and being included in above-mentioned digital signal and reference frequency composition are consistent, make the frequency-dividing clock of the cycle integral multiple of above-mentioned reference clock with generation, this frequency-dividing clock is outputed to the frequency divider of above-mentioned analog-to-digital converter and above-mentioned automatic equalizer as work clock, it is characterized in that: above-mentioned automatic equalizer comprises, above-mentioned digital signal is carried out the transversal filter that wave shape equalization is handled, the high order interpolation processor that the shortcoming of the number of samples after with above-mentioned frequency-dividing clock the output of above-mentioned transversal filter being taken a sample is carried out interpolation, infer equalization target value from the output of above-mentioned high order interpolation processor, and the parameter of above-mentioned transversal filter controlled, make that the balancing error as the error between the output of this equalization target value and above-mentioned transversal filter becomes minimum control device.
If according to the present invention, can obtain to realize that to by using frequency-dividing clock to replace the shortcoming of the sampling spot that reference clock obtains to carry out interpolation equal equalization performance not only can be cut down power consumption simultaneously but also can adapt to the effect of high rapid regeneration when keeping and use reference clock.Further, the present invention can improve because the characteristic degradation of playback head makes amplitude fading, because the wave form distortion that disc tilt causes, owing to be superimposed upon the information recovery capability that noise effect on the regenerative system etc. makes the deterioration of reproduction waveform data.
Above-mentioned high order interpolation processor comprises, carry out the bistable multivibrator element that the delay of 1 cycle program of frequency-dividing clock is handled, signal after this delay handled carry out tap coefficient weighting a plurality of multipliers and with the totalizer of the output signal addition of above-mentioned a plurality of multipliers.
If according to the present invention, can obtain to realize that to by using frequency-dividing clock to replace the shortcoming of the sampling spot that reference clock obtains to carry out interpolation equal equalization performance not only can be cut down power consumption simultaneously but also can adapt to the effect of high rapid regeneration when keeping and use reference clock.Further, the present invention can improve because the characteristic degradation of playback head makes amplitude fading, because the wave form distortion that disc tilt causes, owing to be superimposed upon the information recovery capability that noise effect on the regenerative system makes the deterioration of reproduction waveform data.
Description of drawings
The 1st figure is the block scheme of expression according to the formation of the reproduced signal processing device of example 1 of the present invention.
The 2nd (a) figure is the figure of expression use according to an example of the input digit regenerated signal of the automatic equalizer of the frequency-dividing clock of example 1 of the present invention.
The 2nd (b) figure is the figure of expression use according to an example of the output equalized waveform of the automatic equalizer of the frequency-dividing clock of example 1 of the present invention.
The 2nd (c) figure is the figure of an example of the output equalized waveform of the expression automatic equalizer that uses reference clock.
The 3rd (a) figure is the figure of expression use according to an example of the output equalized waveform of the automatic equalizer of the frequency-dividing clock of example 1 of the present invention.
The 3rd (b) figure is the figure of expression enforcement according to the result's of the 1+D processing of example 1 an of the present invention example.
The 3rd (c) figure is the figure of expression with an example of the interpolation waveform of implementing to restore according to the Wave data that the timing of example 1 of the present invention is adjusted.
The 4th figure is the block scheme of expression according to the formation of the reproduced signal processing device of example 2 of the present invention.
The 5th figure is the figure of expression according to an example of the high order interpolation processor of example 2 of the present invention.
The 6th figure is the figure of expression as the Nyquist interpolation example of an example of handling according to the high order interpolation of example 2 of the present invention.
The 7th figure is the block scheme of the formation of the existing reproduced signal processing device of expression.
The 8th (a) figure is the figure of an example that is illustrated in the output waveform of the analog-to-digital converter in the existing reproduced signal processing device.
The 8th (b) figure is an example of result of 1+D processing is implemented in expression to the output waveform of the analog-to-digital converter in existing reproduced signal processing device figure.
The 8th (c) figure is that the setting of the equalization target value in existing reproduced signal processing device is carried out in expression, the figure of an example of the output waveform of the result after the enforcement equilibrium.
Embodiment
(example 1)
Below, we are with reference to the reproduced signal processing device of all figure explanations according to example 1 of the present invention.
The 1st figure is the block scheme of expression according to the formation of the reproduced signal processing device of example 1 of the present invention.
Reproduced signal processing device shown in Figure 1 has analog-to-digital converter 1, digital phase synchronization circuit 2, frequency divider 3 and automatic equalizer 8.Automatic equalizer 8 further has transversal filter 4, control device 5 and linear interpolation treating apparatus 6.In addition, the label list identical with the 7th figure is shown in the same parts in the existing reproduced signal processing device, and omits the explanation to them.
3 couples of reference clock CK that extracted by digital phase synchronization circuit 2 of frequency divider handle the frequency division of the cycle integral multiple of this reference clock CK.Linear interpolation treating apparatus 6 is made of unillustrated bistable multivibrator element and totalizer among the figure, by the sampling on analog-to-digital converter 1, replace reference clock CK with frequency-dividing clock CK/N, carry out handling in order to replenish the interpolation of inserting the number of samples shortcoming.
Below, we illustrate the work of reproduced signal processing device with Fig. 1.
The numerical information of scanning playback record on recording medium by unillustrated magnetic head among the figure, will to the signal read implement to emphasize decide the processing of frequency band the simulation regenerated signal be input to analog-to-digital converter 1, this signal transformation is become many-valued digital reproduced signal.Above-mentioned digital reproduced signal is input to the transversal filter 4 of digital phase synchronization circuit 2 and automatic equalizer 8.Digital phase synchronization circuit 2 extracts reference clock CK from the above-mentioned digital reproduced signal of input, with this reference clock CK input frequency divider 3.Frequency divider 3 makes the frequency division of the cycle integral multiple of above-mentioned reference clock CK handle output frequency division clock CK/N.In analog-to-digital converter 1 and automatic equalizer 8, this frequency-dividing clock CK/N is used as work clock.Here, N represents frequency dividing ratio, frequency dividing ratio N=2 in this example 1 (below be designated as " two divided-frequency ").On the other hand, the digital reproduced signal that is input to transversal filter 4 is sent to decoding circuit through after the equilibrium treatment in transversal filter 4.In above-mentioned equilibrium treatment, transversal filter 4 is controlled according to tap coefficient as parameter.At control device 5, according to the digital reproduced signal of conduct by transversal filter 4 inputs, the output signal of transversal filter 4 and the balancing error of the error between the equalization target value are set this tap coefficient at any time.Usually, in control device 5, we use according to steepest descent method and make the square mean of balancing error become the minimum LMS algorithm that calculates like that successively.For the output equalized waveform of transversal filter 4, by frequency-dividing clock CK/N is used as above-mentioned work clock, number of samples reduces when comparing with reference clock CK.Therefore, in order to prevent to become unstable in the setting of the equalization target value of control device 5, be input to control device 5 simultaneously at output equalized waveform with transversal filter 4, carry out equilibrium treatment with 6 pairs of above-mentioned output equalized waveforms of linear interpolation treating apparatus, also will be input to control device 5, make the setting stabilization of equalization target value in the same manner with situation with reference clock CK by the signal that interpolation is carried out in the sampling of shortcoming with frequency-dividing clock CK/N.
Below, we illustrates the linear interpolation processing with the oscillogram of the 2nd (a) figure～the 2 (c) figure and the 3rd (a) figure～the 3 (c) figure etc.
The 2nd (a) figure～the 2 (c) figure and the 3rd (a) figure～the 3 (c) figure have represented digital reproduced signal, equalized waveform and above-mentioned equalized waveform is carried out an example of the waveform after linear interpolation is handled.
The 2nd (a) figure is the figure of an example of expression digital reproduced signal, and ◇ is illustrated in the analog-to-digital converter 1, the point (following note work " sampling spot ") of the simulation regenerated signal being taken a sample with the two divided-frequency clock.The 2nd (b) figure is the figure that the digital reproduced signal of expression by 4 couples the 2nd (a) figure of transversal filter carries out the equalized waveform after the equilibrium treatment, and ◇ represents the sampling spot after the wave shape equalization processing.The 2nd (c) figure is the figure of the equalized waveform (ideal waveform) of expression when the reference clock, the sampling spot when ◇ is illustrated in the analog-to-digital converter 1 reference clock as work clock.In addition, in the 2nd (a) figure～the 2 (c) figure, for the purpose of being familiar with easily, add the solid line that sampling spot is coupled together.
By relatively the 2nd (b) figure and the 2nd (c) figure, we see when replacing reference clock with the two divided-frequency clock, reduce accordingly from the number of samples of the digital reproduced signal of analog-to-digital converter 1 output and the increase of frequency dividing ratio.The processing to replenishing owing to the shortcoming of the sampling spot that causes with frequency-dividing clock like this is that the linear interpolation that carries out in linear interpolation treating apparatus 6 is handled.
The 3rd (a) figure～the 3 (c) figure is that expression uses the two divided-frequency clock to take a sample, and carries out the example that linear interpolation is handled to having implemented the equalized waveform after the equilibrium treatment.In the 3rd (a) figure, ● be illustrated in the analog-to-digital converter 1, with the point that the two divided-frequency clock is taken a sample to digital reproduced signal, the point that should take a sample when reference clock is used in zero expression.That is, when with reference clock during as the work clock of analog-to-digital converter 1, ● and zero both is sampled.In addition, ● and zero timing that begins sampling reverses.Wherein, only use ● it is exactly that interpolation is handled that simulation ground restores zero.At first, in the 3rd (b) figure, represent the 3rd (a) figure's ● carry out the result after 1+D handles with ◇.Here, carry out 1+D and handle and to be,, carry out the delay in 1 cycle of work clock by the bistable multivibrator element and handle, and be added to processing above it by the sampling spot that totalizer will be subjected to equilibrium treatment for certain sampling spot that is subjected to equilibrium treatment.Specifically, this is to certain sampling spot, with its poor with the sampling spot that becomes benchmark (in the 3rd (a) figure, with the sampling spot on the left side as benchmark), is added to next sampling spot,, has only postponed the operation on the sampling spot in 1 cycle of two divided-frequency clock that is.The waveform of the 3rd (c) figure is to shown in the 3rd (a) figure ● and carry out regularly adjusting handling at the ◇ shown in the 3rd (b) figure and obtain, it is the waveform after interpolation is handled.In addition, figure couples together sampling spot with solid line or dotted line for the purpose of being familiar with waveform easily in the 3rd (a) figure～the 3 (c).
Below, the establishing method of the equalization target value when we use frequency-dividing clock with the 3rd (c) figure explanation.This processing is carried out in control device 5.
In the 3rd (c) figure, ● the data that expression is taken a sample practically with frequency-dividing clock, ◇ is a linear interpolation, is about to be input to the output signal of transversal filter 4 of present control device 5 and the output signal of the transversal filter 4 before 1 sampling and adds up, and implements the result after 1+D handles.By to representing the 3rd (c) figure of the sampled data after this interpolation, implement 1+D and handle, continuous 3 ● and 2 ◇ implement the results that 1+D handle, and carry out the positive and negative judgement of each sampling, implement the suitable processing with the 8th (b) figure.But addition results is only utilized the uppermost position of totalizer.By only being added up in the output result's of these totalizers uppermost position because can with described from 0 to 4 five grades of separating in the same manner of prior art, so can set equalization target value in the same manner with situation with reference clock.
Reproduced signal processing device according to this example 1, as explained above, be used as frequency-dividing clock by the work clock that will use in analog-to-digital converter 1 and the automatic equalizer 8, can cut down power consumption, further, because compare the processing interval that can extend in each component part during with the use reference clock, thus also can adapt to high rapid regeneration, and can suppress the increase of circuit scale.
Again, on automatic equalizer 8, have linear interpolation treating apparatus 6, general frequency-dividing clock is crossed the replacement reference clock, can replenish the sampling spot of shortcoming, make the setting of on control device 5, stably carrying out equalization target value become possibility, can keep and the equal equilibrium treatment ability of usefulness reference clock situation.
In addition, in reproduced signal processing device according to this example 1, frequency dividing ratio N=2, but this is an example, for example also can make N=3 etc.But, only handle according to interpolation can be when taking a sample with reference clock same degree ground carry out can increasing frequency dividing ratio in the scope of interpolation.For example, surpass such frequency dividing ratio of minimum repetition period of regenerated signal, can not carry out stable equilibrium treatment in cycle of frequency-dividing clock.
(example 2)
Below, we are with reference to the reproduced signal processing device of all figure explanations according to example 2 of the present invention.
The 4th figure is the block scheme of expression according to the formation of the reproduced signal processing device of this example 2.In addition, the formation identical with above-mentioned example 1 with identical label, and omitted explanation to them.
High order interpolation processor 7 shown in the 4th figure in order to take a sample in analog-to-digital converter 1, replenishes owing to replace the sampling spot of the shortcoming that reference clock causes with frequency-dividing clock, carries out the high order interpolation of Nyquist interpolation etc. and handles.It is the bistable multivibrator element of being handled by the delay in 1 cycle of carrying out frequency-dividing clock that the Nyquist interpolation is handled, signal after this postpone is handled implement the Nyquist interpolation weighting a plurality of multipliers and the totalizer that a plurality of multiplier output signals are added up is constituted.In addition, handling with linear interpolation in example 1 is that to carry out the processing of interpolation with straight line relative, and handling according to the high order interpolation of this example 2 is the processing of carrying out interpolation with the high order curve more than 2 times.
Below, we illustrate the work of reproduced signal processing device with the 4th figure.In addition, about the work identical, omit explanation to them with above-mentioned example 1.
High order interpolation processor 7 play a part with example 1 in the record linear interpolation treating apparatus 6 same, promptly play when number of samples being reduced, will just in time not have the such Wave data of information shortcoming to offer the effect of control device 5 by the work clock that frequency-dividing clock is used as analog-to-digital converter 1 and automatic equalizer 8.The 5th figure is the figure of an example of expression high order interpolation processor 7.High order interpolation processor 7, for example, also can be by delay element 10a to 10f, multiplier 11a is to 11g, the FIR wave filter that totalizer 12 constitutes.C1 represents the weighting coefficient of wave filter to C7, by selecting the Nyquist interpolation characteristic shown in the 6th figure as this coefficient, implements the Nyquist interpolation and handles, and can replenish the number of samples along with the shortcoming that produces as work clock with frequency-dividing clock.Here, the longitudinal axis of the 6th figure is a weighting coefficient, for example, by with certain point during as filter weight coefficient C1, to leave this point that on transverse axis, increases 1T, as weighting coefficient C3, can determine each weighting coefficient C1 the point that further increases 1T to C7 as weighting coefficient C2.In addition, the filter weight coefficient can change weight by settings such as resistance by the change resistance value.During the high order interpolation processor 7 of employing shown in the 5th figure, compare during with usefulness linear interpolation treating apparatus 6, improved the amplitude fading that causes for characteristic degradation significantly owing to playback head, because the wave form distortion that causes of CD canting (inclinations), owing to being superimposed upon the information recovery capability that noise effect on the regenerative system etc. makes the deterioration of reproduction waveform data.
Reproduced signal processing device according to this example 2, as explained above, because by adopting high order interpolation processor 7, will be to offering control device 5 because the information shortcoming of using frequency-dividing clock to cause is carried out the interpolation waveform of interpolation, can set not only stable but also suitable equalization target value, even if so, also can realize and use the equal equalization performance of situation of reference clock with in the situation of frequency-dividing clock.
Again, by adopting high order interpolation processor 7, can improve the amplitude fading that causes for characteristic degradation owing to playback head, because the wave form distortion that causes of CD canting (inclinations), owing to being superimposed upon the information recovery ability that noise effect on the regenerative system etc. makes the deterioration of reproduction waveform data.
The possibility of utilizing on the industry
As mentioned above, the reproduced signal processing device relevant with the present invention is with simulation regeneration letter Number be transformed into digital reproduced signal, this digital reproduced signal is carried out automatic equilibrium treatment Reproduced signal processing device is applicable to the automatic balanced place to the regeneration signal of at a high speed regeneration Reason, or the automatic equilibrium treatment of low power consumption.
Claims (4)
1. reproduced signal processing device has:
Simulating signal is taken a sample, is transformed into the analog-to-digital converter of digital signal,
Above-mentioned digital signal is carried out the automatic equalizer that automatic equalization is handled,
The phase locking circuit of the reference clock that phase place in generating its phase place and reference frequency composition and being included in above-mentioned digital signal and reference frequency composition are consistent and
Generation makes the frequency-dividing clock of the cycle integral multiple of above-mentioned reference clock, and this frequency-dividing clock is outputed to the frequency divider of above-mentioned analog-to-digital converter and above-mentioned automatic equalizer as work clock, it is characterized in that:
Above-mentioned automatic equalizer comprises,
Above-mentioned digital signal is carried out the transversal filter that wave shape equalization is handled,
To the shortcoming of the number of samples after with above-mentioned frequency-dividing clock the output of above-mentioned transversal filter being taken a sample carry out interpolation the linear interpolation treating apparatus and
Infer equalization target value from the output of above-mentioned linear interpolation treating apparatus, and the parameter of above-mentioned transversal filter controlled, make that the balancing error as the error between the output of this equalization target value and above-mentioned transversal filter becomes minimum control device.
2. according to the reproduced signal processing device of record in the claim 1, it is characterized in that:
Above-mentioned linear interpolation treating apparatus comprises,
The output equalizing signal of above-mentioned transversal filter is carried out bistable multivibrator element that the delay of 1 cycle program of frequency-dividing clock handles and
The totalizer of signal after this postpone is handled and above-mentioned output equalizing signal addition.
3. reproduced signal processing device has:
Simulating signal is taken a sample, is transformed into the analog-to-digital converter of digital signal,
Above-mentioned digital signal is carried out the automatic equalizer that automatic equalization is handled,
The phase locking circuit of the reference clock that phase place in generating its phase place and reference frequency composition and being included in above-mentioned digital signal and reference frequency composition are consistent and
Generation makes the frequency-dividing clock of the cycle integral multiple of above-mentioned reference clock, and this frequency-dividing clock is outputed to the frequency divider of above-mentioned analog-to-digital converter and above-mentioned automatic equalizer as work clock, it is characterized in that:
Above-mentioned automatic equalizer comprises,
Above-mentioned digital signal is carried out the transversal filter that wave shape equalization is handled,
The high order interpolation processor that the shortcoming of the number of samples after with above-mentioned frequency-dividing clock the output of above-mentioned transversal filter being taken a sample is carried out interpolation,
Infer equalization target value from the output of above-mentioned high order interpolation processor, and the parameter of above-mentioned transversal filter controlled, make that the balancing error as the error between the output of this equalization target value and above-mentioned transversal filter becomes minimum control device.
4. according to the reproduced signal processing device of record in the claim 3, it is characterized in that:
Above-mentioned high order interpolation processor comprises,
Carry out the bistable multivibrator element that the delay of 1 cycle program of frequency-dividing clock is handled,
Signal after this delay handled carry out tap coefficient weighting a plurality of multipliers and
Totalizer with the output signal addition of above-mentioned a plurality of multipliers.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25458499 | 1999-09-08 | ||
| JP254584/1999 | 1999-09-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1327588A CN1327588A (en) | 2001-12-19 |
| CN1151507C true CN1151507C (en) | 2004-05-26 |
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ID=17267076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB008021279A Expired - Fee Related CN1151507C (en) | 1999-09-08 | 2000-09-08 | Reproduced signal processing device |
Country Status (4)
| Country | Link |
|---|---|
| KR (1) | KR100430184B1 (en) |
| CN (1) | CN1151507C (en) |
| ID (1) | ID28952A (en) |
| WO (1) | WO2001018809A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4581288B2 (en) * | 2000-05-09 | 2010-11-17 | パナソニック株式会社 | Demodulator |
| KR100813074B1 (en) * | 2001-10-25 | 2008-03-14 | 엘지전자 주식회사 | Apparatus for equalizing of optical record media |
| US7274645B2 (en) | 2003-06-10 | 2007-09-25 | Matsushita Electric Industrial Co., Ltd. | Reproduction signal processing apparatus and optical disc player including the same |
| US7304918B2 (en) | 2003-09-24 | 2007-12-04 | Matsushita Electric Industrial Co., Ltd. | Servo error signal generation circuit and servo error signal generation method |
| JP4121444B2 (en) * | 2003-10-31 | 2008-07-23 | 三洋電機株式会社 | Data playback device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3087314B2 (en) * | 1991-01-30 | 2000-09-11 | 日本電気株式会社 | Adaptive filter |
-
2000
- 2000-09-08 WO PCT/JP2000/006121 patent/WO2001018809A1/en active IP Right Grant
- 2000-09-08 ID IDW00200101244A patent/ID28952A/en unknown
- 2000-09-08 CN CNB008021279A patent/CN1151507C/en not_active Expired - Fee Related
- 2000-09-08 KR KR10-2001-7005717A patent/KR100430184B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| ID28952A (en) | 2001-07-19 |
| KR20010086004A (en) | 2001-09-07 |
| CN1327588A (en) | 2001-12-19 |
| WO2001018809A1 (en) | 2001-03-15 |
| KR100430184B1 (en) | 2004-05-03 |
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