CN110166021A - A kind of digital signal processing method for realizing any down-sampled rate conversion - Google Patents
A kind of digital signal processing method for realizing any down-sampled rate conversion Download PDFInfo
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- CN110166021A CN110166021A CN201910428181.0A CN201910428181A CN110166021A CN 110166021 A CN110166021 A CN 110166021A CN 201910428181 A CN201910428181 A CN 201910428181A CN 110166021 A CN110166021 A CN 110166021A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0283—Filters characterised by the filter structure
- H03H17/0286—Combinations of filter structures
- H03H17/0288—Recursive, non-recursive, ladder, lattice structures
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0283—Filters characterised by the filter structure
- H03H17/0286—Combinations of filter structures
- H03H17/0291—Digital and sampled data filters
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Abstract
The invention discloses a kind of digital signal processing methods for realizing any down-sampled rate conversion, belong to the technical field that sample rate is converted in Digital Signal Processing.The present invention realizes the down-sampled rate conversion of high performance any multiple using processing modules such as FIR filter, sampling time computing module, sampling phase computing module, filter factor generation module, sampling switch and output bufferings.The present invention can use the high-speed figures such as high speed FPGA, dsp chip or GPU chip for hardware core, and it is a kind of important improvement to the prior art that the equipment manufactured in this approach, which has the advantages that integration degree is high, it is few to expend resource, rate height can be achieved etc.,.
Description
Technical field
The present invention relates to the technologies that digital signal processing technique field more particularly to digital signal samples rate are converted, especially
Refer to a kind of digital signal processing method for realizing any down-sampled rate conversion.
Background technique
Current, the digital signal processing method of any down-sampled rate conversion is generallyd use based on fitting of a polynomial filter
The FARROW structure of coefficient is realized.For example, the FARROW structure etc. of transposition.
But the FARROW structure of transposition realizes that the filtering performance of any down-sampled rate conversion is filtered with polynomial order and son
Wave device series is related, realizes that the filter of high performance any down-sampled rate conversion will expend a large amount of resource.
Summary of the invention
In view of this, the present invention proposes a kind of digital signal processing method for realizing any down-sampled rate conversion, this method
Real-time calculating based on filter factor is filtered device and designs and be adapted to various down-sampled rates, it can be achieved that whole in which can be convenient
The down-sampled rate conversion of several times, the down-sampled rate conversion of reasonable several times, the even unreasonable down-sampled rate conversion of several times, are particularly suitable for reality
The down-sampled rate conversion of any multiple between existing 1~2.
To achieve the goals above, present invention provide the technical scheme that
A kind of digital signal processing method for realizing any down-sampled rate conversion, this method are used to be f to sample frequencyin's
Input signal x (k) carries out the FIR filtering of N rank, and carrying out sample frequency to the output of FIR filter is foOutput sampling, obtain
To down-sampled output signal y (m), wherein the sample frequency of signal meets fo≤finComprising following steps:
It (1) is f to sample frequencyinInput signal x (k) carry out N rank FIR filtering, the coefficient of FIR filter is by filtering
Coefficient generation module generates；
(2) carrying out sample frequency to the output of FIR filter by sampling switch module is foOutput sampling, through too slow
Down-sampled output signal y (m) is obtained after punching storage, sampling switch module is controlled by sampling time computing module；
(3) sampling time computing module is in sample frequency finLower pair of drivingIt is cumulative to carry out n integers, n
For the integer in 16~48 ranges, it is f that n accumulated values, which enter cumulative overflow checking module to generate frequency,oSignal TmAs
The control signal of FIR filter output sampling, the output T of cumulative overflow checking module in cumulative overflowmIt is 1, is adding up not
The output T for the overflow checking module that adds up when spillingmIt is 0；TmSampling switch module is controlled when being 1 to carry out the output of FIR filter
Sampling, TmSampling switch module is exported without sampling when being 0, whereinIt is to be rounded downwards to the result of calculating；
(4) in filter factor generation module, withN number of table of filter coefficients is searched simultaneously as address, and generates N simultaneously
A filter factor；
(5) sampling control signal T is exportedmIn sample frequency finDriving under control sampling phase computing module switch choosing
It selects, in TmSwitch selection output when being 1The phase-accumulated of n integers is carried out afterwards, in TmIt is switched when being 0
Selection output 0 is to keep n integer accumulated values constant；The output p to add up to n integerskHigh I is taken to obtain phase controlling
Signal Signal controls the FIR filter coefficient that filter factor generation module generates time-varying, and wherein I is less than or equal to n
Integer,Expression rounds up；
(6) N number of table of filter coefficients is contained in filter factor generation module, is stored in advance in each table of filter coefficients
2IA numerical value, the jth number value in arbitrary No. i-th table of filter coefficients is by ideal interpolating functionMultiplied by window functionIt obtains afterwards, wherein i is 0~N-1 range
Interior integer, j are 0~2IInteger in -1 range.
From narration above can be seen that the beneficial effects of the present invention are:
1, the present invention can be realized the down-sampled rate conversion of any multiple, relative to the FARROW based on fitting of a polynomial
The implementation of structure, this method have biggish change to the precision of the adaptability of broadband signal, the flexibility of design, realization
It is kind；
2, present invention uses the window functions of time-varying, the window function relative to traditional fixed coefficient mirror image inhibition on
It is improved (using 15dB or more is improved when Hanning window)；
3, the present invention can be using high speed FPGA (field programmable gate array), DSP (Digital Signal Processing) chip or GPU
The high-speed figures chip such as (graphics processor) is hardware core, with the equipment of this principle manufacture with integration degree is high, volume
Small, structure is simple, high reliablity, it is easily scalable the advantages that.
Detailed description of the invention
Fig. 1 is the principle frame of the digital signal processing method of any down-sampled rate conversion of the realization in the embodiment of the present invention
Figure；
Fig. 2 is the functional block diagram of the sampling time computing module in the embodiment of the present invention；
Fig. 3 is the functional block diagram of the sampling phase computing module in the embodiment of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in further detail.
As shown in Figures 1 to 3, a kind of digital signal processing method for realizing any down-sampled rate conversion comprising following step
It is rapid:
It (1) is f to sample frequencyinInput signal x (k) carry out N rank finite impulse response filter (FIR) filtering,
The coefficient of FIR filter is generated by filter factor generation module.The output of FIR filter is work in finIt, can under sample frequency
It indicates are as follows:
Wherein μk∈ [0,1), to export normalized offset of the sampling instant relative to the current input sample moment, k is
Sequence number of the output signal under input sample frequency.
(2) carrying out sample frequency by sampling switch module to the output of FIR filter is foOutput sampling, through too slow
Down-sampled output signal y (m) is obtained after punching storage, sampling switch module is controlled by sampling time computing module.
Based on the calculated y ' (k) of input sample, being extracted after sampling switch and being converted to sample frequency is foY '
(m), y ' (m) is by finThe f of sample rate expressionoThe signal of sample rate is seen in the time domain discontinuously, by FIFO (first in, first out)
Buffer-stored uses the frequency of standard for foClockreading FIFO output after be converted to the output y (m) of standard.
(3) sampling time computing module is in sample frequency finLower pair of drivingIt is cumulative to carry out n integers, n
For the integer between 16~48, it is f that n accumulated values, which enter cumulative overflow checking module to generate frequency,oSignal TmAs FIR
The control signal of filter output sampling, in cumulative overflow, overflow checking module exports TmIt is 1, the spilling in cumulative do not spill over
Detection module exports TmIt is 0, TmIt controls sampling switch module when being 1 to sample the output of FIR filter, TmIt is sampled when being 0
Switch module is exported without sampling, whereinIt is that lower rounding is carried out to the result of calculating.
It is 32 or higher to reach enough timing accuracies to can use n；Cumulative overflow checking module is by comparing current
Accumulated value and last accumulated value then judge to overflow T if it is less than or equal to last accumulated valuemIt is 1, otherwise judges not overflow
T outmIt is 0.TmFrequency be fo, the clock of driving is fin。
(4) sampling control signal T is exportedmIn sample frequency finDriving under control sampling phase computing module switch choosing
It selects, in TmSwitch selection output when being 1The phase-accumulated of n integers is carried out afterwards, in TmIt is switched when being 0
Selection output 0 keeps n integer accumulated values constant, the cumulative output p of n integerskHigh I is taken to obtain phase control signal Signal controls the FIR filter coefficient that filter factor generation module generates time-varying, and wherein I is whole less than or equal to n
Number,It is rounded in expression.
Wherein, pkIt is the sampled value of the phase accumulator of n integers currently exported, pk-1For the previous of phase accumulator
A output sampled value；It is 32 or higher to reach enough timing accuracies to can use n.
When the generation of FIR filter coefficient is based on look-up table, from n phase-accumulated output sampled value pkIn take high I
(10 desirable) obtains phase control signal for positionIt usesSeeking value as address progress look-up table can be obtained the current k moment
N number of filter coefficient.Pass throughμ can be calculatedk,
When the generation of FIR filter coefficient is based on calculating (or mix and table look-up and calculate in real time) in real time, using all
N-bit data.
(5) in filter factor generation module withN number of filtering is obtained after searching N number of table of filter coefficients simultaneously as address
Coefficient；
The FIR filter of N rank has N number of filter factor, the corresponding table of filter coefficients of each filter factor, N number of filtering
Coefficient table address wire having the same is connected to
(6) N number of table of filter coefficients is contained in filter factor generation module, is stored in advance in each table of filter coefficients
2IA numerical value, the jth number value in arbitrary No. i-th table of filter coefficients is by ideal interpolating function Sa [π (i-N/2+j/2I)]
Multiplied by window function w [2 π (i-N/2+j/2I)/N] after obtain, wherein i be 0~N-1 positive integer, j be 0~2I- 1 positive integer.
It can need to select the window functions such as Hanning window, Hamming window, Blackman window, Lloyd " Butch " Keaser window according to what mirror image inhibited,
Such as selection Hanning window when i-th of filter coefficient table j-th of numerical value calculating formula are as follows:
hij=Sa [π (i-N/2+j/2I)]×{0.5+0.5cos[2π(i-N/2+j/2I)/N]} (4)
According to the look-up table that formula (4) are designed, can reach when realizing down-sampled with the reconstruct FIR filter of 12 ranks
The mirror image of 65dB or more inhibits, and the mirror image of 95dB or more can be reached when realizing down-sampled with the reconstruct FIR filter of 48 ranks
Inhibit.
In short, the present invention is produced using FIR filter, sampling time computing module, sampling phase computing module, filter factor
The processing modules such as raw module, sampling switch and output buffering realize the down-sampled rate conversion of high performance any multiple.This hair
Equipment tool that is bright that the high-speed figures such as high speed FPGA, dsp chip or GPU chip can be used for hardware core, manufacturing in this approach
Have that integration degree is high, it is few to expend resource, the advantages of rate height etc. can be achieved, is a kind of important improvement to the prior art.
The discussion of any of the above embodiment is exemplary only, it is not intended that hint the scope of the present disclosure (including right is wanted
Ask) it is limited to these examples.All within the spirits and principles of the present invention, it is made to the above embodiment it is any omit, modification,
Equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (1)
1. a kind of digital signal processing method for realizing any down-sampled rate conversion, which is characterized in that for being to sample frequency
finInput signal x (k) carry out N rank FIR filtering, and to the output of FIR filter carry out sample frequency be foOutput adopt
Sample obtains down-sampled output signal y (m), and wherein the sample frequency of signal meets fo≤fin, comprising the following steps:
It (1) is f to sample frequencyinInput signal x (k) carry out N rank FIR filtering, the coefficient of FIR filter is by filter factor
Generation module generates；
(2) carrying out sample frequency to the output of FIR filter by sampling switch module is foOutput sampling, deposited by buffering
Down-sampled output signal y (m) is obtained after storage, sampling switch module is controlled by sampling time computing module；
(3) sampling time computing module is in sample frequency finLower pair of drivingIt is cumulative to carry out n integers, n 16
Integer in~48 ranges, it is f that n accumulated values, which enter cumulative overflow checking module to generate frequency,oSignal TmIt is filtered as FIR
The control signal of wave device output sampling, the output T of cumulative overflow checking module in cumulative overflowmIt is 1, in cumulative do not spill over
The output T of cumulative overflow checking modulemIt is 0；TmSampling switch module is controlled when being 1 to sample the output of FIR filter,
TmSampling switch module is exported without sampling when being 0, whereinIt is to be rounded downwards to the result of calculating；
(4) in filter factor generation module, withN number of table of filter coefficients is searched simultaneously as address, and generates N number of filter simultaneously
Wave system number；
(5) sampling control signal T is exportedmIn sample frequency finDriving under control sampling phase computing module switch selection,
In TmSwitch selection output when being 1The phase-accumulated of n integers is carried out afterwards, in TmChoosing is switched when being 0
Output 0 is selected to keep n integer accumulated values constant；The output p to add up to n integerskHigh I is taken to obtain phase control signalSignal controls the FIR filter coefficient that filter factor generation module generates time-varying, and wherein I is whole less than or equal to n
Number,Expression rounds up；
(6) N number of table of filter coefficients is contained in filter factor generation module, has been stored in advance 2 in each table of filter coefficientsIIt is a
Numerical value, the jth number value in arbitrary No. i-th table of filter coefficients is by ideal interpolating function Sa [π (i-N/2+j/2I)] multiply
With window function w [2 π (i-N/2+j/2I)/N] after obtain, wherein i is the integer within the scope of 0~N-1, and j is 0~2IIn -1 range
Integer.
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Cited By (3)
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| CN110620565A (en) * | 2019-08-09 | 2019-12-27 | 西人马帝言(北京)科技有限公司 | Digital extraction filter |
| CN113219224A (en) * | 2021-04-22 | 2021-08-06 | 电子科技大学 | Method for obtaining optimal sampling rate of variable clock waveform generator |
| CN117459065A (en) * | 2023-12-26 | 2024-01-26 | 深圳市九天睿芯科技有限公司 | Method and device for converting PDM signal into PCM signal and electronic equipment |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110620565A (en) * | 2019-08-09 | 2019-12-27 | 西人马帝言(北京)科技有限公司 | Digital extraction filter |
| CN113219224A (en) * | 2021-04-22 | 2021-08-06 | 电子科技大学 | Method for obtaining optimal sampling rate of variable clock waveform generator |
| CN113219224B (en) * | 2021-04-22 | 2022-02-01 | 电子科技大学 | Method for obtaining optimal sampling rate of variable clock waveform generator |
| CN117459065A (en) * | 2023-12-26 | 2024-01-26 | 深圳市九天睿芯科技有限公司 | Method and device for converting PDM signal into PCM signal and electronic equipment |
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