CN1751381A - 杂质导入方法 - Google Patents
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Abstract
本发明提供包括在半导体衬底的表面形成非晶层的工序以及在非晶化的上述半导体衬底上形成浅的杂质导入层的工序的杂质导入方法和该方法所使用的装置,特别是其特征在于,形成非晶层的工序是向上述半导体衬底的表面照射等离子体的工序,形成浅的杂质导入层的工序是向非晶化的上述表面导入杂质的工序。
Description
技术领域
本发明涉及在半导体等的制造工艺中导入杂质的杂质导入方法。
背景技术
在固体基体表面或薄膜的表面上,通常形成有构成固体基体的原子与空气中的氧结合而成的氧化物的膜或用氢终结的膜。这种膜非常薄,通常是小于等于1nm。过去一直用从氧化物等的膜之上进行离子注入等的方法物理性地导入杂质。即,通过用电场等向成为杂质的离子提供能量并在表面进行照射而向固体基体内部导入杂质。
然而,伴随着近些年来器件的精细化人们要求形成浅的结的技术。在这里,作为现有的浅的结的形成技术可以举出低能离子注入技术。低能离子注入技术是一种在从离子源以一定程度高的电压引出离子后在后级使之减速的方法,人们一直在进行着能够将离子束电流值保持为一定程度的大小并能够进行低能的注入等的研究。这样研究的结果,能够形成几十nm左右的浅的杂质层,并已经在工业上应用于半导体的制造。
此外,为了形成浅的结,作为近些年来受到关注的技术可以举出等离子体掺杂技术。所谓等离子体掺杂技术是一种使含有所期望的粒子的等离子体与半导体衬底等的被处理体的表面接触,从而向被处理体表面导入杂质的技术。在这里,由于等离子体最多也就是几百V的低能量,所以适用于浅的杂质层的形成,已进行了形成从十几nm到几十nm左右的浅的结的实验。
还有,在“Technical Digest of Symposium on VLSI Technology.Honolulu,P.110(2000)”中公开了实现现有的最浅的P型结的实验。据报告说该实验结的深度为7nm。
此外,在(1)International Workshop on Junction Technology(IWJT),p.19(2000),(2)J.Vac.Sci.Technol.A16,P.1,(1998),(3)SiliconTechnology-No.39 18th June,2002等中提出了使用气体源的气相掺杂法的方案。这是一种通过在常压氢环境中加热半导体衬底并供给B2H6或PH3而形成P型和N型的杂质扩散层的方法。在这里,通过氢携带气体除去硅上的自然氧化膜来保持清洁表面而具有抑制杂质特别是硼的表面偏析的效果。
此外,为了分解气体通常需要大于等于600℃的温度。例如,在“SiliconTechnology”(No.39 18th June,2002)中公开了通过将半导体衬底加热到900℃并供给40秒1ppm的B2H6气体而形成高浓度的浅的结的实验结果。据此,将硼浓度成为1×1018cm-3的深度当作结深,则结深是与上述同等程度的约7nm。
此外,在International Workshop on Junction Technology(IWJT),p.39-40(2002)中公开了在室温下实现气相掺杂法的技术。这是一种在向氧化物等的膜附着到表面上的固体基体导入物质时,在除去了氧化物等的膜之后附着或导入所期望的粒子的方法。根据该报告,杂质导入层的深度约为3~4nm。
如上所述,利用等离子体掺杂或低能离子注入等的方法,在近些年来进行了形成从十几nm到几十nm左右的浅的结的实验。在实现现有的最浅的P型结的实验中形成了7nm左右的浅的杂质层。然而,随着器件的进一步的精细化人们要求提供更为简单且更为低电阻地形成更浅的杂质层的方法。
作为应对这样的要求的技术,由于等离子体掺杂技术能够以小的加速能量向半导体衬底导入粒子,所以与离子注入相比能够形成浅的导入层。但是,虽然说是小的能量但由于具有加速能量,所以形成浅的导入层是有限度的。此外,提出了在等离子体掺杂时作为掺杂剂向衬底供给自由基(radical)。由于自由基不具有电荷,所以虽然不会因在鞘(sheath)间被加速而被注入到衬底内,但由于是激活的,所以可以认为因与衬底表面反应而被导入到衬底内。使用气体源的气相掺杂法是一种向衬底供给不具有加速能量的掺杂剂并利用表面反应形成杂质扩散层的技术。这种技术被认为是超过了向衬底上照射具有能量的离子的方法的界限的技术。
然而,如上所述,使用气体源的气相掺杂法,为了分解气体,通常需要大于等于600℃的温度。在这样的高温度下作为掩模材料就不能使用光刻胶。为此,需要利用CVD法形成SiO2等并使之图形化,因而存在晶体管形成工艺的工序增加这样的问题。
还有,在要向衬底内导入不具有等离子体掺杂法或气相掺杂法等中的自由基或气体分子等的加速能量的掺杂剂或者加速能量非常小的掺杂剂的情况下,存在难以在短时间内形成高浓度的杂质层的问题。
此外,采用在除去氧化物等的膜后附着或导入所期望的粒子的方法的气相掺杂法,虽然能够在室温下形成高浓度的杂质层,但却存在尚未提出杂质量的控制方法的问题。
作为使本身为半导体衬底的晶体硅非晶化(无定形化)的技术,过去提出了离子注入锗或硅的方法。人们广泛地研究了在向硅衬底内离子注入锗或硅使表面非晶化之后,离子注入硼等的杂质,然后,进行退火工序。作为在离子注入杂质前预先进行非晶化的优点如下。(1)在离子注入硼等的小的杂质时难以导入得深,(2)由于非晶硅与晶体硅相比光的吸收系数高,所以退火时能够有效地使杂质活化。
然而,由离子注入进行的非晶化,存在形成浅的非晶层的效率不充分的问题。
发明内容
本发明的杂质导入方法,其特征在于,包括:在固体基体的表面上形成非晶层的工序;以及在非晶化的上述半导体衬底上形成浅的杂质导入层的工序;其中,形成非晶层的工序是向上述半导体衬底的表面照射等离子体的工序,形成浅的杂质导入层的工序是向非晶化的上述表面导入杂质的工序。此外,本发明的特征在于:还包括在将杂质导入后为了使杂质电激活化而进行退火的工序。
此外,本发明的杂质导入装置,是至少具有使固体基体表面非晶化的装置、导入成为杂质的所期望的粒子的装置、以及使导入的杂质激活化的退火装置的装置组的杂质导入装置。
附图说明
图1是本发明的一个实施例的装置的主要部分剖面图。
图2是表示本发明的一个实施例的衬底的剖面TEM观察结果的图。
图3是表示本发明的一个实施例的非晶层的厚度的等离子体照射偏置电压依赖性的图。
图4是表示本发明的RHEED观察结果的图。
图5是表示比较例的RHEED观察结果的图。
图6是对本发明的一个实施例与比较例比较片电阻值的图。
图7是表示本发明的一个实施例的片电阻值的等离子体照射时间依赖性的图。
图8是表示本发明的一个实施例的片电阻值的偏置电压依赖性的图。
图9是表示本发明的一个实施例的片电阻值与非晶层厚度的关系的图。
具体实施方式
本发明的杂质导入方法的特征在于,在向固体基体表面上照射等离子体而形成非晶层后,或者在固体基体表面上形成非晶层的同时浸透、附着或导入(以下称为导入)作为杂质的所期望的粒子。其理由是通过形成非晶层而易于向固体基体内导入所期望的粒子。此外,在应用于作为固体基体之一的硅衬底的情况下,由于非晶硅与晶体硅比较光的吸收系数高,所以通过在表面形成非晶层能够在退火时有效地使杂质激活化,能够实现极浅结的低电阻化。
在固体基体表面上形成极浅的非晶层的情况下,优选地向固体表面照射等离子体。其理由在于,由于与用现有的离子注入进行的非晶化比较使用了低能的等离子体,所以能够更有效地制作浅的非晶层。在非晶层所具有的效果之中,在想要仅利用在气体或自由基等的超低能状态下易于导入杂质的效果的情况下,可以通过利用从向固体表面照射等离子体的方法、向固体表面离子注入的方法、给固体表面附加非晶层的方法的组中选择的至少一种方法实现非晶层的形成。由于将向固体表面照射等离子体的时间设为不足70秒可以实现良好的吞吐率,所以是优选的。此外,由于离子注入时注入Ge离子能够期待提高电学特性,所以是优选的。
优选地导入杂质的方法是使含有所期望的粒子的气体或者等离子体与该非晶化的固体基体表面接触以向固体基体表面或其附近浸透、附着或导入杂质。其理由是因为只有使象气体或等离子体那样不具有加速能量的或者加速能量非常小的状态的粒子接触才能够形成浅的杂质层。具体地可以举出等离子体、自由基、气体、超低能离子等。作为杂质导入方法的具体名称,在气体的状态下导入时称为气体掺杂,在使等离子体与固体基体表面接触时则称为等离子体掺杂。此外,在用离子注入进行非晶化的情况下,除了能够有效地进行退火之外,通过利用能够用超低能导入杂质的办法还可以实现新颖性。具体地说,在用离子注入进行非晶化的情况下,杂质的导入使用使气体接触固体基体表面的方法。利用这种方法,能够制作非常浅的杂质导入层。
通过控制、调整进行非晶化的固体基体表面的厚度、非晶化的程度,来控制、调整剂量和结深以导入杂质的方法,由于容易控制片电阻值,此外器件特性也容易控制,所以是优选的。进行非晶化的固体基体表面的厚度、非晶化的程度的控制和调整,能够通过改变与向固体表面照射的涉及等离子体的偏置电压、照射时间、偏置功率(bias power)、离子种类、鞘电压而进行。
优选地等离子体包括氩、氦等的稀有气体或氢。其原因是由于稀有气体在化学性能上是稳定的而且难以与固体基体表面发生化学反应,所以被认为将所期望的粒子与固体基体表面的表面附着的比率抑制得小。其结果是除了由非晶化产生的杂质导入之外还能够期待由表面吸着产生的杂质的导入。此外,由于氦、氢在高温下扩散系数大而且在退火后在表面残留量少,因而几乎不会带来电的坏影响,所以是优选的。由于氦兼备化学性能稳定、在高温下的扩散系数大这两方面的特性,所以是特别优选的。
本发明的杂质导入装置,是至少具有使固体基体表面非晶化的装置、导入所期望的粒子的装置、使所导入的期望的粒子激活化的退火装置的装置组的杂质导入装置,由此能够实现本发明的工艺。
还有,由于将2个或2个以上的使固体基体表面非晶化的装置、导入所期望的粒子的装置、使所导入的期望的粒子激活化的退火装置的装置组进行组合或使之一体化能够使装置小型化,所以从提高生产性等方面来看是优选的。
还有,能够提供可用短时间形成高浓度的非常浅的杂质层且剂量的控制比现有技术更为容易,并且能够使退火后的片电阻低电阻化的杂质层的形成方法。
下面,参看附图说明本发明的实施例。但是,本发明并不限定于以下的实施例。
图1对本发明的一个实施例中使用的装置100进行说明。装置100具有:高频电源1;匹配盒2;线圈和天线3;质量流控制器4和5;涡轮分子泵6;电导阀7;干燥泵8;循环器9;DC电源10;匹配盒11、高频电源12和下部电极14。硅衬底等的被处理体13放置到下部电极上。
在图1中,在将硅衬底13送到工艺室15内后,将其设置到下部电极14上。对工艺室15分别连接有稀有气体导入管16和乙硼烷气体的导入管17。另外,稀有气体用于通过向表面照射稀有气体等离子体而使硅衬底表面非晶化。乙硼烷气体用于等离子体化而进行等离子体掺杂,或者用于将气体原样地导入工艺室15内而进行气体掺杂。构成为气体流量能够由质量流控制器4、5分别进行控制。
在以下的实施例中,说明固体基体自身的表面非晶化。但本发明并不限定于此,也能够应用于在固体基体上形成的薄膜的表面。
(实施例1)
在实施例1中,详细地对照射等离子体而形成非晶层的工序进行说明。
在工艺室15内,向作为被处理体13的硅衬底照射等离子体。
所使用的气体是向氩、氦或99.975%的氦内混合进0.025%的乙硼烷的气体。
首先,向硅衬底照射氩等离子体。等离子体照射条件是在照射时间从5秒到60秒、偏置电压从30V到310V的条件下进行。在停止等离子体照射并首先将工艺室15内部抽成真空后,用氮气进行净化后从工艺室15内将衬底取出。并对取出的衬底的剖面进行TEM观察。图2是偏置电压180V等离子体照射时间5秒的氩等离子体照射后的剖面TEM照片。可以看出在硅衬底21上已经形成了4.3nm的厚度的非晶层22。
此外,即使在使用氦等离子体的情况下,也能够确认非晶层的形成。另外,关于使用氦等离子体的情况在实施例2进行说明。
此外,使用99.975%的氦气和0.025%的乙硼烷气体的混合气体的等离子体,在100V的偏置电压进行了60秒的等离子体照射。非晶层的厚度是10nm。此外,用SIMS测定的硼的剂量是7.3×1014cm-2。如上所述,能够同时地进行非晶层的形成和杂质的导入。
(实施例2)
在实施例2中,对用于非晶化的等离子体照射中的非晶层的厚度的控制进行说明。
在工艺室15内向作为被处理体13的硅衬底上照射了氦气体浓度为100%的氦气体的等离子体。分别在等离子体照射时间为7秒和30秒、使偏置电压在从30V到310V的范围内变化的条件下进行等离子体照射。用椭圆仪测定从工艺室15中取出的衬底的非晶层的厚度。图3是偏置电压与非晶层的厚度的关系。可见在等离子体照射下能够在小于等于30秒的短时间内形成2nm~22nm的范围的非晶层。此外,通过使偏置电压变化就能够控制非晶层的厚度。此外,通过改变照射等离子体的时间能够改变非晶层的厚度。
(实施例3)
在实施例3中,表示将本发明的杂质导入方法应用于气体掺杂的例子。在用气体掺杂导入杂质的情况下,研究了因非晶层的有无而产生的片电阻值的差异。下面,对利用非晶化而易于用低能量导入杂质和退火后能够实现低电阻化进行说明。
在工艺室15内,向作为被处理体13的硅衬底照射氩气等离子体。等离子体照射是在等离子体照射时间5秒、偏置电压160V的条件下进行的。在停止等离子体照射并将工艺室15内部抽成真空后,使B2H6气体与衬底表面接触70秒。70秒后停止B2H6气体的供给,在抽成真空后,用氮气进行净化后从工艺室15内取出衬底。
在对所取出的衬底以1100口、3分钟进行退火后,使用4探针法测定了片电阻值。此外,对于只进行了等离子体照射的衬底进行了用RHEED的观察和用椭圆仪的膜厚等的测定。其中,所谓RHEED,是反射高速电子衍射(Reflection High-Energy Electron Diffraction)。
图4表示用RHEED的表面观察的结果。如图4所示,在晶体上未发现特有的亮点,可见通过等离子体照射衬底的表面已非晶化。此外,片电阻值为5.1E3ohm/sq。
此外,使等离子体照射时间在5秒到70秒的范围内改变并使偏置电压在45V到210V的范围内改变进行了同样的实验。在所有条件下衬底表面都已被非晶化。这时,片电阻值分布在大于等于6.5E2ohm/sq而小于等于5.1E3ohm/sq的范围内。
图6是表示因非晶层的有无而产生的片电阻值(Sheet resistance)的差异的图。用白圆圈(○)表示进行了非晶化的本实施例的片电阻值测定结果。同时,用黑圆圈(●)表示未进行非晶化的比较例1的结果。实施例的片电阻值与比较例的片电阻值相比分布为小1个数量级到2个数量级的值。可以认为由于形成了非晶层,即使不提供加速能量也容易向基体内导入B2H6气体,以及通过有效地吸收用于退火的光,与比较例相比片电阻值大大地减小了。
(实施例4)
在实施例4中,进行用等离子体掺杂作为杂质的导入方法时的因非晶层的有无而产生的片电阻值的差异的研究。对于利用非晶化尽管退火后的结深是相同的但却能够实现低电阻化的情况进行说明。
为了使硅衬底表面非晶化,在工艺室15内向作为被处理体13的硅衬底照射氦气浓度为100%的氦气的等离子体。等离子体照射是在等离子体照射时间为7秒、偏置电压为150V的条件下进行的。停止等离子体照射后将工艺室15内部抽成真空。然后,为了进行等离子体掺杂,在偏置电压200V的条件下照射7秒用氦气稀释成5%的B2H6气体的等离子体。在停止等离子体照射并抽成真空后,用氮气进行净化后从工艺室15内取出衬底。然后,为了使杂质电激活化,在升温速度为200℃/秒、降温速度为50℃/秒、最高到达温度为1000℃的峰值高速热退火(spike RTA)的条件下进行了退火。测定了这样制成的试样的片电阻和SIMS分布。
该试样的片电阻值为635ohm/sq。当设在SIMS分布中硼浓度成为1×1018cm-3的深度为结深时,则结深为27.2nm。另一方面,将在比较例2中详细地进行说明,在不进行非晶化而其它的条件都相同的情况下制成的试样的片电阻值为923ohm/sq、结深为28.1nm。即,通过用氦等离子体照射进行非晶化,即使结深大致相同也能够实现30%或30%以上的低电阻化。
(实施例5)
在实施例5中,研究了等离子体照射时间与片电阻值的关系。图7表示结果。
在工艺室15内向作为被处理体13的硅衬底照射氩气的等离子体。氩等离子体照射在从5秒到70秒的范围内改变等离子体照射时间。在偏置电压为45V(用×表示)和160V(用■表示)这2种条件下进行。等离子体照射后的处理都是在相同的条件下进行。即,在停止等离子体照射并将工艺室15内部抽成真空后,使B2H6气体与衬底表面接触70秒。70秒后停止B2H6气体的供给,在抽成真空后,在用氮气进行净化后从工艺室15内取出衬底。在1100口、3分钟的条件下对所取出的衬底进行退火后,使用4探针法测定了片电阻值。
无论在偏置电压为45V和60V的哪一种情况下,片电阻值都随着等离子体照射时间的变长而下降。从该结果可以看出,通过改变等离子体照射时间能够控制片电阻值。
此外,上述的实验结果表明等离子体照射时间越长则剂量就越高。可以认为这是由于等离子体照射时间越长,则硅衬底表面的非晶化程度就越高,所以B2H6气体向基体的导入量越增加。
(实施例6)
在实施例6中,研究了偏置电压与片电阻值的关系。图8表示其结果。在设氩等离子体照射时间为70秒而其它的条件都相同的情况下,使偏置电压变为45V(试样1)、160V(试样2)、210V(试样3)而制成了试样。没有特别指出的条件与实施例5是同样的。
如图8所示,片电阻值随着偏置电压的绝对值的增大而下降。其结果,试样2和试样3的片电阻值下降到小于等于1.0E3ohm/sq。
由此可见,通过改变偏置电压能够控制片电阻值。
此外,上述的实验结果表明偏置电压绝对值越大则剂量就越高。可以认为这是由于偏置电压的绝对值越大,则硅衬底表面的非晶化的程度就越高,从而B2H6气体向基体的导入量就增加。
(实施例7)
在实施例7中,研究了非晶层的厚度与片电阻值的关系。图9表示其结果。横轴的非晶层的厚度是用椭圆仪测定的在实施例6中制成的试样1-3的衬底表面上形成的非晶层的厚度的值。此外,非晶层的厚度为零的数据是作为比较例测定硅衬底时的测定结果。
如图9所示,非晶层的厚度,在试样1約为2nm,在试样2和3约为3nm。此外,可以看出随着非晶层的厚度的增加片电阻值下降了。由该结果可见,片电阻值能够通过改变非晶层的厚度进行控制。此外,可以看出在实施例5和6中所说明的非晶化的程度可以表现为非晶层的厚度。
此外,上述的实验结果表明非晶层的厚度越大则剂量就越高。可以认为这是由于非晶层的厚度越大越增加B2H6气体向基体的导入量。
(比较例1)
除了没有用等离子体照射进行非晶化之外,以与表示本发明的实施方式的实施例3、5、6、7相同的条件进行了实验。比较例1是与气体掺杂有关的例子,其与实施例3对应。在将硅衬底放入工艺室15内并将工艺室15内抽成真空后,使B2H6气体与衬底表面接触70秒。
在70秒后停止B2H6气体的供给并抽成真空后,在进行氮净化后从工艺室15内取出衬底。所取出的衬底在1100口、3分钟的条件下进行退火后,使用4探针发测定了片电阻值。此外,用Secondary Ion MassSpectrometry(以下称为SIMS)测定了硼的剂量。进而用RHEED、椭圆仪观察、测定了导入到工艺室15内之前的硅衬底表面。
图5是比较例的硅衬底的用RHEED进行的表面观察结果。在图5所示的照片的上部观察到了亮点,可以确认是结晶。此外,即使用椭圆仪进行测定也无法确认表面的非晶层。
此外,片电阻值为1.7E5ohm/sq。这个值与形成了非晶层的本实施例的片电阻值比较要大1个数量级或1个数量级以上。根据SIMS的测定结果,硼的剂量是2E12cm-2。可见几乎未导入杂质。
(比较例2)
除了没有用等离子体照射进行非晶化之外,以与发明的实施例4相同的条件进行了实验。即,将作为被处理体13的硅衬底放入工艺室15内。然后,为了进行等离子体掺杂,在偏置电压200V下照射7秒的用氦气稀释成5%的B2H6气体的等离子体。在停止等离子体照射并抽成真空后,在用氮气进行净化后从工艺室15取出衬底。然后,为了使杂质电激活化,在升温速度200℃/秒、降温速度50℃/秒、最高到达温度1000℃的spike RTA的条件下进行了退火。测定了这样制成的试样的片电阻和SIMS分布。
该试样的片电阻为923ohm/sq,结深为28.1nm。这与实施例3的非晶化的试样相比片电阻高了30%或30%以上。
虽然在实施例中对固体基体表面自身的非晶化进行说明,但本发明的固体基体表面,除了基体自身的表面之外也包括在基体上形成的薄膜的表面。因此,在固体基体上形成的薄膜的表面的非晶化也包括在本发明范围内。
如上所述,本实施例的杂质导入方法能够在室温下且用短时间形成非常浅的杂质层,从而能够容易地制造半导体、液晶、生物芯片等的有源元件以及电阻、线圈、电容器等的无源元件。
工业上的利用可能性.
如上所述,本发明提供能够在室温下用短时间形成高浓度的非常浅的杂质层的、而且剂量的控制容易并能够形成可使退火后的片电阻实现低电阻化的杂质层的杂质导入方法。
Claims (21)
1.一种杂质导入方法,其特征在于,包括:
在固体基体表面上形成非晶层的第1工序;以及
在非晶化的上述固体基体上形成浅的杂质导入层的第2工序;
其中,上述第1工序是向上述固体基体的表面照射等离子体的工序,
上述第2工序是向非晶化的上述固体基体的表面导入杂质的工序。
2.根据权利要求1所述的杂质导入方法,其特征在于:上述第2工序是将杂质进行等离子体掺杂的工序。
3.根据权利要求1所述的杂质导入方法,其特征在于:上述第2工序是将杂质进行离子注入的工序。
4.根据权利要求1所述的杂质导入方法,其特征在于:上述第2工序是将杂质进行气体掺杂的工序。
5.根据权利要求1所述的杂质导入方法,其特征在于:在上述第2工序之后包括退火工序,上述退火工序使上述杂质激活化。
6.根据权利要求1所述的杂质导入方法,其特征在于:上述第1工序在上述第2工序之前进行,或者与上述第2工序同时地进行。
7.根据权利要求1所述的杂质导入方法,其特征在于:在同一工艺室内作为连续的工序以in-situ进行上述第1工序和上述第2工序。
8.根据权利要求1所述的杂质导入方法,其特征在于:上述第1工序是向上述固体基体的表面照射等离子体的工序,或者是对上述固体基体附加非晶层的工序。
9.根据权利要求8所述的杂质导入方法,其特征在于:上述固体基体是硅,上述第1工序是通过改变与向上述固体基体的表面照射的等离子体有关的偏置电压、照射时间、偏置功率、离子种类和鞘电压之中的至少一个条件而进行上述非晶层的厚度控制的工序。
10.根据权利要求9所述的杂质导入方法,其特征在于:上述等离子体照射时间是大于等于5秒且小于70秒。
11.根据权利要求8所述的杂质导入方法,其特征在于:上述等离子体是含有从稀有气体、氢和卤素中选择的至少一者的系的等离子体。
12.根据权利要求1所述的杂质导入方法,其特征在于:
上述第1工序是在上述固体基体的表面进行离子注入的工序,
上述第2工序是使用气体掺杂向非晶化的上述固体基体的表面导入上述杂质的工序。
13.根据权利要求12所述的杂质导入方法,其特征在于:上述离子注入是从Si、Ge中选择的至少一种离子的注入。
14.根据权利要求1所述的杂质导入方法,其特征在于:上述第2工序是使含有上述所期望的粒子的气体或等离子体与上述非晶层接触的工序,作为杂质向上述固体基体的表面导入上述粒子。
15.根据权利要求1所述的杂质导入方法,其特征在于:在上述第2工序,以等离子体、自由基、气体、离子的状态导入所期望的粒子。
16.一种杂质导入方法,其特征在于,包括:向固体基体的表面进行大于等于5秒且小于70秒的等离子体照射的工序;以及使从含有所期望的粒子的气体、等离子体、自由基和离子中选择的至少一者与上述固体基体的表面接触的杂质导入工序。
17.根据权利要求16所述的杂质导入方法,其特征在于:上述进行照射的工序是通过改变与向上述固体基体的表面照射的等离子体有关的偏置电压、照射时间、偏置功率、离子种类和鞘电压之中的至少一个条件而控制向上述固体基体的表面导入的杂质量的工序。
18.根据权利要求16所述的杂质导入方法,其特征在于:上述等离子体是含有从稀有气体、氢和卤素中选择的至少一者的气体的系的等离子体。
19.根据权利要求16所述的杂质导入方法,其特征在于:在上述杂质导入工序之后还具有退火工序,上述退火工序使上述杂质激活化。
20.一种杂质导入装置,具有:在固体基体的表面形成非晶层的第1装置;向上述固体基体的表面导入所期望的粒子的第2装置;以及使所导入的上述所期望的粒子激活化的退火用的第3装置;其能够依次或同时地进行向上述固体基体的表面进行的非晶层的形成和向上述非晶层进行的所期望的粒子的导入。
21.根据权利要求20所述的杂质导入装置,其特征在于:使从上述第1装置、第2装置和第3装置中选择的2个或2个以上的装置组合或一体化。
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2004
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- 2004-02-12 CN CNA2004800046349A patent/CN1751381A/zh active Pending
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Cited By (5)
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CN101641764B (zh) * | 2007-02-16 | 2012-03-07 | 瓦里安半导体设备公司 | 多阶等离子体掺杂基板的方法 |
CN102339737A (zh) * | 2010-07-16 | 2012-02-01 | 住友重机械工业株式会社 | 等离子体掺杂装置及等离子体掺杂方法 |
CN102339737B (zh) * | 2010-07-16 | 2015-05-13 | 住友重机械工业株式会社 | 等离子体掺杂装置及等离子体掺杂方法 |
CN103500718A (zh) * | 2013-08-02 | 2014-01-08 | 上海华力微电子有限公司 | 监控集成电路制造中离子注入工艺的方法 |
CN113846384A (zh) * | 2021-09-22 | 2021-12-28 | 中国科学院半导体研究所 | 晶体锗材料的表面非晶化的方法 |
Also Published As
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EP1596427A4 (en) | 2009-06-10 |
TWI328827B (zh) | 2010-08-11 |
US20080124900A1 (en) | 2008-05-29 |
JP4387355B2 (ja) | 2009-12-16 |
US20080160728A1 (en) | 2008-07-03 |
US7709362B2 (en) | 2010-05-04 |
TW200423185A (en) | 2004-11-01 |
US8222128B2 (en) | 2012-07-17 |
US20070254460A1 (en) | 2007-11-01 |
EP1596427A1 (en) | 2005-11-16 |
KR20050098923A (ko) | 2005-10-12 |
WO2004075274A1 (ja) | 2004-09-02 |
US7741199B2 (en) | 2010-06-22 |
US7696072B2 (en) | 2010-04-13 |
KR100739837B1 (ko) | 2007-07-13 |
US7618883B2 (en) | 2009-11-17 |
US20050277273A1 (en) | 2005-12-15 |
US20100167508A1 (en) | 2010-07-01 |
JPWO2004075274A1 (ja) | 2006-06-01 |
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