CN1701429A - 布线板及其制造方法 - Google Patents
布线板及其制造方法 Download PDFInfo
- Publication number
- CN1701429A CN1701429A CNA2004800012094A CN200480001209A CN1701429A CN 1701429 A CN1701429 A CN 1701429A CN A2004800012094 A CNA2004800012094 A CN A2004800012094A CN 200480001209 A CN200480001209 A CN 200480001209A CN 1701429 A CN1701429 A CN 1701429A
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- Prior art keywords
- layer
- plating
- terminal
- wiring
- formation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000004519 manufacturing process Methods 0.000 title claims description 44
- 229910000679 solder Inorganic materials 0.000 claims abstract description 47
- 239000002131 composite material Substances 0.000 claims abstract description 30
- 238000007772 electroless plating Methods 0.000 claims abstract description 29
- 238000009713 electroplating Methods 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 370
- 238000007747 plating Methods 0.000 claims description 165
- 230000015572 biosynthetic process Effects 0.000 claims description 74
- 238000000034 method Methods 0.000 claims description 70
- 239000000463 material Substances 0.000 claims description 59
- 239000011347 resin Substances 0.000 claims description 47
- 229920005989 resin Polymers 0.000 claims description 47
- 238000005530 etching Methods 0.000 claims description 40
- 238000000576 coating method Methods 0.000 claims description 22
- 239000011248 coating agent Substances 0.000 claims description 21
- 238000003475 lamination Methods 0.000 claims description 19
- 229910000952 Be alloy Inorganic materials 0.000 claims description 15
- 239000011241 protective layer Substances 0.000 claims description 6
- 239000010949 copper Substances 0.000 description 63
- 230000014509 gene expression Effects 0.000 description 54
- 239000010931 gold Substances 0.000 description 37
- 239000004065 semiconductor Substances 0.000 description 29
- 238000005868 electrolysis reaction Methods 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 239000011889 copper foil Substances 0.000 description 6
- 238000007650 screen-printing Methods 0.000 description 6
- 238000010301 surface-oxidation reaction Methods 0.000 description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 4
- 239000002585 base Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000004927 fusion Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 238000005493 welding type Methods 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-N Acrylic acid Chemical class OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004760 aramid Substances 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229940070259 deflux Drugs 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005470 impregnation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000032696 parturition Effects 0.000 description 1
- 150000002978 peroxides Chemical class 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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Abstract
基于本发明的布线板具有由1层以上布线层构成的布线部,和在布线部的一侧突出而设置的第1端子部,和在布线部的另一侧设置的第2端子部。在由多层金属层构成的复合材料的表面形成具有第1端子部用开口的防护层,从第1端子部用开口只蚀刻复合材料的第1金属层而形成孔部。从防护层的开口在孔部内实施电镀,用电镀层填埋孔部内形成第1端子部。除去防护层,在复合材料上设置布线层,在该布线层上设置具有第2端子部用开口的阻焊层。在阻焊层的第2端子部用开口处实施电镀形成第2端子。除去复合材料的残留部分制成布线板。
Description
技术领域
本发明涉及层压1层布线层而成的布线板及其制造方法。作为第1端子部在布线层的一侧形成用于连接半导体元件和倒装芯片的突起状的倒装芯片连接用焊球。在其另一侧,在覆盖布线层的阻焊层的开口处电镀形成第2端子部以填埋该开口。
背景技术
近年来,在半导体装置中,半导体元件(是指半导体芯片或单纯的芯片)的外部端子数不断增多。为了提高电特性,通过区域阵列型的倒装芯片接合使其与作为内插器的半导体封装用基板接合。
一直以来,在C4型(通过焊接的倒装芯片连接型)的倒装芯片接合中,为得到与半导体元件一侧的焊球稳定接合的状态,在基板一侧的端子处也必须形成焊球。
此时,通常在通过采用金属掩模的丝网印刷供给焊锡以焊膏后,经过回流工序、除去焊剂工序、平坦化工序,形成基板侧的焊球。
但是,基板侧焊膏的丝网印刷中金属掩模的生产成本高,且间距的缩小存在限制,一般来说,间距限度为150μm左右。
因此,今后在半导体元件侧的布线更加细微化,达到90nm左右的情况下,也考虑进一步缩小端子间距。因此必须通过丝网印刷以外的方法应对更加细微化的发展。
作为丝网印刷以外的方法,也可举出通过金属和金属盐的取代反应在基板上形成焊球,通过对应于细微化间距的化学反应形成焊球的方法,但这种方法的材料费、生产成本高,焊球高度的偏差也存在问题。
而且,使用丝网印刷在基板侧形成焊球与半导体元件侧的焊球相接合时,使它们接触后通过加热,使焊锡熔融而接合。此时,由于基板侧的焊球高度的偏差,存在与半导体元件侧的焊球接合不充分的危险性。
此外,在不使半导体元件侧的焊球熔融而仅使基板侧的焊球熔融进行倒装芯片接合时,也存在基板侧的焊球表面氧化使其与半导体元件侧的焊球的湿润性降低的问题。
此外,通常,在基板表面配有阻焊层,设置有用于与半导体元件侧的焊球接合的端子,在NSMD(非焊接屏蔽界定)的情况下,基板侧端子因其形状会与阻焊层产生错位。此外,对于热产生的应力下落以及其他撞击,也容易产生故障,使可靠度下降,结果有时也发生由端子形状引起的接合不良。
特别是,焊球间距细微化时,阻焊层的开口径变小,阻焊层的开口形状为SMD(焊点屏蔽界定)的情况下,若不给予焊锡,接合就不完全。
这里,如图7(a)所示,端子部721的区域没有被阻焊层722限定的形态称为NSMD,如图7(b)或7(c)所示,端子部721的区域被阻焊层722限定的形态称为SMD。
在SMD中,即使给予焊锡,当阻焊层的壁的角度接近垂直时,在上表面部(D1部分)的焊锡处应力集中,有热冲击时寿命下降的危险。
另一方面,阻焊层的断面形状的壁面角度为钝角时,开口部底部的大小由于层厚、层灵敏度不同而产生偏差,有表面大小在间距微小时不能变大的缺点。
参照特开平2001-93929号公报(公知文献1)和特愿2002-203868号公报(公知文献2)。
如上所述,在C4型(通过焊接的倒装芯片连接型)的倒装芯片接合中,伴随焊球间距的微细化,在基板侧设有焊球时,通过以往的焊膏的丝网印刷形成基板侧的焊球时间距的微小化存在限制。此外,通过金属与金属盐的取代反应在基板侧形成焊球时,材料费、生产成本高,也存在焊球高度的偏差问题。并且,通常,在基板表面配有阻焊层,设置有用于与半导体元件侧的焊球接合的端子,由于这样的形状引发了各种问题,一直在谋求以上问题的对策。
发明内容
本发明就是对应上述问题而生的,具体地说,其目的是提供一种布线板及其制造方法,该布线板可以直接与半导体元件的焊球进行倒装芯片连接,并且可靠地与半导体元件的焊球进行倒装芯片连接。
本发明为布线板的制造方法,为具有由1层以上布线层构成的布线部,和在布线部的一侧突出设置的第1端子部,以及在布线部的另一侧设置的第2端子部的布线板的制造方法,其特征在于,包括以下工序:在由多层金属层构成的复合材料的表面形成具有第1端子部用开口的防护层的防护层形成工序;从防护层的第1端子部用开口只蚀刻复合材料的第1金属层而形成孔部的蚀刻工序;从蚀刻的第1端子部用开口以埋住孔部的方式通过电镀形成第1端子部的第1次电镀工序;剥离防护层后在第1端子部设置树脂材料层形成布线层的布线层形成工序;在布线层上设置具有第2端子部用开口的阻焊层的阻焊层形成工序;在阻焊层的第2端子部用开口实施电镀形成第2端子部的第2次电镀工序;和蚀刻除去复合材料的残留部分的蚀刻除去工序。
本发明为布线板的制造方法,其特征在于,复合材料通过层压第1Cu层、Ni层或Ti层,和第2Cu层而构成。
本发明为布线板的制造方法,其特征在于,第1次电镀工序包括实施以下步骤:依次镀Au、镀Cu,或依次镀Au、镀Ni,或依次镀Au、镀Ni、镀Cu,或依次镀Pd、镀Cu,或依次镀Pd、镀Ni,或依次镀Pd、镀Ni、镀Cu,或依次镀Pd系合金、镀Cu,或依次镀Pd系合金、镀Ni,或依次镀Pd系合金、镀Ni、镀Cu、或镀Sn,或依次镀Sn、镀Cu、或镀Sn系合金,或依次镀Sn系合金、镀Cu。
本发明为布线板的制造方法,其特征在于,在具有由1层布线层构成的布线部,和在布线部的一侧突出而设置的第1端子部,以及在布线部的另一侧设置的第2端子部的布线板的制造方法中,包括以下工序:在由第1Cu层、Ni层和第2Cu层构成的复合材料的表面形成具有第1端子部用开口的防护层的防护层形成工序;以埋住防护层的第1端子部用开口的方式通过电镀形成第1端子部用电镀形成部的第1次电镀工序;剥离防护层后在电镀形成部设置树脂层形成布线层的布线层形成工序;在布线层上设置具有第2端子部用开口的阻焊层的阻焊层形成工序;在阻焊层的第2端子部用开口处实施电镀形成第2端子部的第2次电镀工序;以复合材料的Ni层作为蚀刻阻止层蚀刻除去第2Cu层的工序;以在Ni层上只覆盖第1端子部区域的方式,形成追加防护层,以该追加防护层作为耐蚀刻防护层,蚀刻Ni层、第1Cu层使其贯通,形成由电镀形成部、第1Cu层和Ni层组成的第1端子部的蚀刻工序;除去补充抗蚀剂后,在电镀形成部、第1Cu层和Ni层上进一步形成非电解Au电镀层,或依次形成非电解Ni电镀层、非电解Au电镀层的非电解镀工序。
本发明为布线板的制造方法,其特征在于,复合材料由包层材料(clad material)构成。
本发明为布线板的制造方法,其特征在于,在布线层形成工序中,利用半添加方法(semi additive method)形成布线层。
本发明为布线板的制造方法,其特征在于,布线层形成工序包括以下工序:(A)层压由绝缘树脂构成的树脂材料层的层压工序;(B)将在上述层压工序中被层压的树脂层用激光开孔洞形成用的孔的孔形成工序;(C)在包含所形成开孔部的表面的树脂材料层表面实施非电解Cu电镀,在所形成的Cu层上电路形成部对开口以形成防护层后,在从防护层开口露出的Cu层上,以该Cu层作为导电层实施电镀Cu,然后,剥离上述防护层,蚀刻除去露出的通过非电解镀形成的Cu层,在形成通孔的同时形成电路部的电路部形成工序。
本发明为布线板的制造方法,其特征在于,在布线层形成工序中,使用全添加方法(full additive)和移除(subtractive)方法,或使用全添加方法和半添加方法两者形成布线层。
此处,移除方法是指选择蚀刻铜箔等布线形成用导电性薄板形成布线部的方式,全添加方法是指只以选择电镀布成布线部的方式,半添加方法是指蚀刻除去电镀形成的导电层形成布线部的方式。此外,电镀形成通电用薄布导电后,以此作为通电层进行选择性电镀形成厚的布线部,进一步通过平面蚀刻除去通电用薄导电层的方式也称为半添加方法。
本发明为布线板,其特征在于,具有由1层以上平面布线层构成的布线部,和在布线部的一侧设置的多个第1端子部,和在布线部的另一侧设置的多个第2端子部,布线层在面向第1端子部侧有树脂材料层,在布线部的第1端子部一侧未设置阻焊层,使树脂材料层露出,各第1端子部在其前端有平面部,各第1端子部的平面部均在一个平面上,在整个各第1端子部的平面部上形成由电镀层或非电解镀层构成的表面电镀层。
本发明为布线板,其特征在于,第1端子部的电镀层从表面一侧依次形成镀Au层、镀Cu层,或依次形成镀Au层、镀Ni层,或依次形成镀Au层、镀Ni层、镀Cu层,或依次形成镀Pd层、镀Cu层,或依次形成镀Pd层、镀Ni层,或依次形成镀Pd层、镀Ni层、镀Cu层,或依次形成镀Pd系合金层、镀Cu层,或依次形成镀Pd系合金层、镀Ni层,或依次形成镀Pd系合金层、镀Ni层、镀Cu层、或镀Sn层,或依次形成镀Sn层、镀Cu层、或镀Sn系合金层,或依次形成镀Sn系合金层、镀Cu层。
本发明为布线板,其特征在于,第1端子的非电解镀层为非电解Au镀层,或从表面侧依次为非电解Ni镀层,非电解Au镀层。
通过本发明的布线板的制造方法,基于这样的构成,可以提供一种布线板,它具有能够与半导体元件的焊球形成直接倒装芯片连接的第1端子部,能够确实地与半导体元件的焊球进行直接倒装芯片连接。
通过本发明的布线板的制造方法,第1次电镀工序包括:依次镀Au、镀Cu、或依次镀Au、镀Ni,或依次镀Au、镀Ni、镀Cu,或依次镀Pd、镀Cu,或依次镀Pd、镀Ni,或依次镀Pd、镀Ni、镀Cu,或依次镀Pd系合金、镀Cu,或依次镀Pd系合金、镀Ni,或依次镀Pd系合金、镀Ni、镀Cu、或镀Sn,或依次镀Sn、镀Cu、或镀Sn系合金,或依次镀Sn系合金、镀Cu。制成的布线板在第1端子部表面直接与半导体元件的焊球形成倒装芯片连接。因此连接时即使第1端子部表面氧化也不会引起实用水平上的问题。
特别是在第1次电镀工序中实施依次镀Au、镀Cu、或依次镀Au、镀Ni,或依次镀Au、镀Ni、镀Cu时,更可以消解第1端子部表面氧化的问题。
此外,在本发明的布线板的制造方法中,与第1Cu层的厚度一致,全部形成焊球形成区域用孔部。此外,在Ni层或Ti层的面上,可以使第1端子部(焊球部)的表面位置一致。
即,第1端子部无偏差,其突出的表面位置均匀一致。而且,能够使第1端子部(焊球部)的突起的高度,即,制造布线板时从树脂材料层突出的高度与第1Cu层的厚度一致。
此外,以Ni层或Ti层、第2Cu层作为通电层,通过电镀能够形成第1端子部(焊球部)。
此处,蚀刻Ni层或Ti层具有蚀刻第1Cu层时的蚀刻阻止层,第1次电镀的母材和作为通电层的作用。
第2Cu层有支持材料的功能,在第1次电镀工序中成为通电层。
此外,由于使蚀刻第1Cu层时的防护层为耐镀防护层,作业性良好。
在本发明的布线板的制造方法中,在第1端子部的端子部表面实施非电解镀Au,或依次非电解镀Ni、非电解镀Au。由此制作的布线板在第1端子部的表面可以直接与半导体元件的焊球形成倒装芯片连接。此外,连接时第1端子部的表面不存在表面氧化的问题。
此外,在本发明的布线板的制造方法中,蚀刻第1Cu层、Ni层后,该蚀刻残留部作为由树脂材料层突出的部分,在其表面通过非电解镀形成镀层。因此通过规定第1Cu层厚度、Ni层厚度的总和可以调整从树脂材料层突出的高度。此外,由于第1端子部的突出的表面的位置与Ni层表面一致,可以调整第1端子部(焊球部)的突起高度,即,在制造布线板时从树脂材料层突出的高度,使其均匀一致。
此处,第2Cu层不仅有支持基材的功能,还有电镀时作为通电层的作用,作为第1端子部的一部分,基于其厚度,在制造布线板时控制从树脂材料层突出的高度。
此外,Ni层是蚀刻第2Cu层时的蚀刻阻止层,具有电镀时的通电层的作用,第2Cu层具有作为支持材料的功能。
上述中,作为具有依次层压第1Cu层、Ni层或Ti层、第2Cu层结构的复合材料,从生产性方面考虑优选包层材料,但不限定于此。
包层材料的制成,例如,可在作为第1Cu层的铜箔一面形成镀Ni层将其与作为第2Cu层的Cu箔一起加热、压合形成。
另外,在作为第1乃至第2Cu层的Cu箔的一面上,形成镀Ni层,并进一步形成作为第2乃至第1Cu层的镀Cu层,也可以形成复合材料。
此外,作为布线层形成工序,可列举出使用半添加方法或全添加方法和移除方法,或使用全添加方法和半添加方法两者的方法。
本发明的具有倒装芯片连接用焊球的布线板,通过这样的构成,具有能够与半导体元件的焊球形成直接倒装芯片连接的第1端子部,并能够确实地与半导体元件的焊球形成直接倒装芯片连接。
在第1端子部侧未设置有阻焊层,使树脂材料层露出,不会出现以往的由配有阻焊层的布线板的端子形状引起的各种问题。
此外,作为第1端子部的电镀层,可列举出,从表面一侧依次形成镀Au层、镀Cu层,或依次形成镀Au层、镀Ni层,或依次形成镀Au层、镀Ni层、镀Cu层,或依次形成镀Pd层、镀Cu层,或依次形成镀Pd层、镀Ni层,或依次形成镀Pd层、镀Ni层、镀Cu层,或依次形成镀Pd系合金层、镀Cu层,或依次形成镀Pd系合金层、镀Ni层,或依次形成镀Pd系合金层、镀Ni层、镀Cu层、或镀Sn层,或依次形成镀Sn层、镀Cu层、或镀Sn系合金层,或依次形成镀Sn系合金层、镀Cu层,作为非电解镀层,因其为非电解Au镀层、或依次的非电解Ni镀层,非电解Au镀层,即使第1端子部表面氧化也不会引起实用水平的问题。
特别是,在最表面设置Au层时,可以确实地除去第1端子部的表面氧化。
附图说明
图1(a)~(g)为本发明的布线板的制造方法的第1实施方式的一部分工序剖面图。
图2(a)~(d)是接着图1(a)~(g)的一部分工序剖面图。
图3(a)~(d)是接着图2(a)~(d)的一部分工序剖面图。
图4(a)~(h)为本发明的布线板的制造方法的第2实施方式的一部分工序剖面图。
图5(a)~(d)是接图4(a)~(h)的一部分工序剖面图。
图6是使用具有本发明的倒装芯片连接用焊球的布线板的封装的剖面图。
图7是用于说明在配置有布线板的阻焊层一侧设置倒装连接部时的方式和结合状态的剖面图。
具体实施方式
在附图基础上说明本发明的实施方式。
图1(a)~(g)为本发明的布线板的制造方法的第1实施方式的一部分工序剖面图。图2(a)~(d)是接图1(a)~(g)的一部分工序剖面图。图3(a)~(d)是接图2(a)~(d)的一部分工序剖面图。图4(a)~(h)为本发明的布线板的制造方法的第2实施方式的一部分工序剖面图。图5(a)~(d)是接图4(a)~(h)的一部分工序剖面图。其中,图3(d)是本发明的具有倒装芯片连接用焊球的布线板的第1实施方式的剖面图,图5(d)是本发明的具有倒装芯片连接用焊球的布线板的第2实施方式的剖面图,图6是使用具有本发明的倒装芯片连接用焊球的布线板的封装的剖面图。图7是用于说明在配置有布线板的阻焊层一侧设置倒装连接部时的结合状态的剖面图。
图1~图7中,符号110表示(板状的)复合材料,符号111表示第1Cu层,符号111A表示孔部,符号112表示Ni层,符号113表示第2Cu层,符号120表示防护层,符号121表示防护层开口,符号131表示镀Au层,符号132表示镀Ni层,符号133表示镀Cu层,符号140表示树脂材料层,符号141表示孔部(通孔形成用孔),符号145表示树脂材料层,符号150、151表示非电解Cu镀层(也单指Cu层),符号160表示防护层,符号170表示Cu层,符号171表示通孔部,符号175表示Cu层,符号176表示通孔部,符号180表示阻焊层,符号181表示开口,符号191表示镀Ni层,符号192表示镀金层,符号210表示(板状的)复合材料,符号211表示第1Cu层,符号212表示Ni层,符号213表示第2Cu层,符号220表示防护层,符号221表示防护层开口,符号230表示电镀层(也称电镀形成部),符号240表示树脂材料层,符号241表示孔部(通孔形成用孔),符号245表示树脂材料层,符号250、255表示非电解镀层,符号260表示防护层,符号270表示Cu层,符号271表示通孔部,符号275表示Cu层,符号276表示通孔部,符号280表示阻焊层,符号281表示开口,符号291表示镀Ni层,符号292表示镀金层,符号310表示(有倒装芯片连接用焊球)布线板,符号311表示布线层层压形成部(也称布线部),符号312表示倒装芯片连接用端子(也称第1端子部),符号312S表示突出的平面部,符号313表示与母板(mother board)连接用端子(第2端子部),符号315表示焊球,符号320表示半导体元件,符号325表示焊球,符号330表示底层填料(under fil1),符号710表示半导体元件,符号715表示焊球,符号720表示布线板(也称内插器),符号721表示端子部,符号725表示焊球,符号730表示接合部。
首先,基于图1~图3说明本发明的布线板的制造方法的第1实施方式。
布线板如图3(d)所示,具有由2层的布线层170、175组成的布线部,在布线层170、175的一侧突出而设置的第1端子部131、132、133,和在布线层170、175的另一侧设置的第2端子部191、192。
布线部的各布线层170、175在第1端子部131、132、133侧有树脂材料层140、145,而且第1端子部131、132、133构成了用于与半导体元件的焊球形成直接倒装芯片连接的突起状的倒装芯片连接用焊球。第2端子部191、192为在覆盖布线部170、175的阻焊层180的开口181处以填埋开口的方式形成。
各布线层170、175的树脂材料层140、145侧朝向第1端子部131、132、133侧。
在第1端子部131、132、133侧未设置阻焊层,使树脂材料层140露出,第1端子部131、132、133在其突起状的前端设有平面部131,而且,各端子部131、132、133的平面部131整齐地在一个平面上。这种构成组成的布线板作为封装用的内插器使用。
下面阐述布线板的制造方法。首先,准备依次层压第1Cu层111、Ni层112、第2Cu层113而成的板状复合材料110(图1(a))。接着在第1Cu层111的表面以指定形状形成防护层120(图1(b)),从防护层的开口121起只蚀刻露出的第1Cu层111,使其贯通于指定区域,形成第1端子部形成区域用的孔部111A。
作为复合材料110,从生产性角度考虑优选包层材料,但并不限定于此。
通常,作为第1Cu层111、Ni层112、第2Cu层113的厚度,分别采用50~125μm、1μm、18μm~30μm。
作为包层材料,在作为第1Cu层111或第2Cu层113的铜箔的一面形成镀Ni层112,将其分别与作为第2Cu层113、第1Cu层111的铜箔一起加热后压合形成。
此外,在作为第1至第2Cu层的111、113的铜箔的一面上,形成镀Ni层112,进一步在镀Ni层112上形成作为第2乃至第1Cu层的镀Cu层111、113,也可以形成复合材料110。
使用的防护层120在后续的镀工序中耐镀。
作为防护层120的材质,通常使用丙烯酸系的物质。
此外,作为第1Cu层111的蚀刻液,为使Ni层112成为蚀刻剂阻止层,采用不蚀刻Ni层的碱性蚀刻。
然后,以防护层120作为耐镀防护层,在蚀刻工序中以填埋形成的孔部111A的方式通过电镀形成作为倒装芯片连接用焊球的第1端子部131、132、133。(图1(d))
在本例中,依次实施镀Au、镀Ni、镀Cu,依次形成镀Au层131、镀Ni层132、镀Cu层113,并填埋孔部11A。
使镀Au层131、镀Ni层132、镀Cu层113的各部分并在一起的物质为第1端子部131、132、133。
代替这种镀,也可依次实施镀Au、镀Cu,或依次实施镀Au、镀Ni。
接着,从复合材料110处剥离防护层120(图1(e))后,在复合材料110的第1端子部131、132、133的形成侧上,以连接至该第1端子部的方式,通过树脂材料层140,以半添加方法形成设置有布线的第1层的布线层170。
首先,在复合材料110的第1端子部形成侧上层压由绝缘性树脂构成的树脂材料层140(图1(f)),将层压的树脂材料层140用激光开一个通孔形成用孔部141。
作为树脂材料层140,优选例如使用在芳香族聚酰胺纤维或玻璃纤维中含浸环氧系树脂的物质,但并不限定于此。
作为树脂材料层140的层压方法,例如可采用首先在铜箔的一面上形成树脂材料层140,通过该树脂材料层140将其在在复合材料上层压后,除去铜箔的层压方法。
作为形成孔部141的激光,使用CO2激光或UV-YAG激光。
接着,包含形成的孔部141的表面,在树脂材料层140表面镀非电解镀Cu(图2(a))。然后在形成的非电解镀Cu镀层150上开口电路形成部,形成防护层160(图2(b)),然后,在从防护层160的开口中露出的Cu层150上以该Cu层150为导电层,实施电镀Cu170(图2(c))。接着,剥离上述防护层160,通过露出的非电解镀蚀刻除去形成的Cu层150,形成电路部。(图2(d))
由此,形成了第1层布线层。
然后,同样地,在第1层布线层170上形成第2层布线层175。(图3(a))
接着,在第2层布线层175上,设置使第2端子部191、192的形成区域露出的开口181,以覆盖全部布线层175的方式形成阻焊层180。(图3(b))
接着,在阻焊层180的开口181处实施电镀,形成第2端子部191、192。(图3(c))
在该电镀工序中,以Ni层111、第2Cu层113作为导电层进行依次电镀Ni、电镀Au。
形成的镀Ni层191、Cu层192的厚度总和与阻焊层180的厚度相当。
接着蚀刻除去复合材料110的残留部。(图3(d))
此时的顺序按照第2Cu层113的蚀刻、Ni层112的蚀刻、第1Cu层111的蚀刻的顺序来进行。
在上述蚀刻除去工序中,例如,第2Cu层113、第1Cu层111的蚀刻使用碱系溶液作为蚀刻液,Ni层112的蚀刻使用过氧水、硫酸系溶液作为蚀刻液。
由此,制成目标布线板(图3(d))。
接着,基于图4、图5说明本发明的布线板的制造方法的第2实施方式。
布线板具有由2层的布线层270、275组成的布线部,和在布线层270、275的一侧突出而设置的第1端子部230、211、212、295,和在布线层270、275的另一侧设置的第2端子部291、292。(图5(d))
布线部的各布线层270、275在第1端子部230、211、212、295侧有树脂材料层240、245,而且第1端子部230、211、212、295构成了用于与半导体元件的焊球形成直接倒装芯片连接的突起状的倒装芯片连接用焊球。
第2端子部291、292在覆盖布线部270、275的阻焊层280的开口281处以填埋开口的方式形成。
各布线层270、275的树脂材料层240、245侧朝向第1端子部侧的230、211、212、295侧。在第1端子部211、212、295侧未设置阻焊层,使树脂材料层240露出。第1端子部211、212、295在其突起状的前端设有平面部295,而且,各第1端子部211、212、295的平面部295整齐地在一个平面上。
这种构成组成的布线板作为封装用的内插器使用。
下面阐述布线板的制造方法。首先,准备依次层压第1Cu层211、Ni层212、第2Cu层213而成的板状复合材料210(图4(a))。接着在第1Cu层211的表面以指定形状形成防护层220(图4(b)),以防护层220作为耐镀防护层,在从防护层的开221露出的第1Cu层211上,以填埋开口221的方式,通过电镀,形成作为第1端子部一部分的电镀部(电镀形成部)230。(图4(c))
电镀部230通常为镀Cu。
然后,在剥离防护层220(图4(d))后,在电镀部230侧上,以连接至作为上述第1端子部一部分的电镀部230的方式,分别通过树脂材料层240形成设置的第1层布线层270,及通过树脂材料层245形成设置的第2层布线层275(图4(e)~图5(a))。
接着,设置使第2端子部291、292的形成区域露出的开口281,以覆盖全部布线层275的方式形成阻焊层280。(图5(b))
接着,在阻焊层280的开口281处实施电镀,形成由镀Ni层291和镀Au层292构成的第2端子部。
接着,以Ni层212作为抗蚀刻阻止层,蚀刻除去第2Cu层213,并在Ni层212上以仅覆盖第1端子部区域的方式形成追加防护层212a。然后以追加防护层212a为耐蚀刻防护层,蚀刻Ni层212、第1Cu层211使之贯通,合并电镀形成部230、第1Cu层211的残留部、Ni层212的残部形成第2端子部,除去追加防护层212a。(图5(c))
接着,在露出的Ni层212的表面实施非电解Au镀,形成非电解镀Au层295(图5(d))。
由此制成目标布线板。
而且,各部材也可使用与第1例相同的物质,这里省去说明。
接下来阐述本发明的变形例。代替层压Cu层111、Ni层112、第2Cu层113而成的复合材料110(图1(a)),也可使用层压第1Cu层、Ti层、第2Cu层而成的板状复合材料。
此外,在图1至图3和图4至图5中,布线层的数量是1层,或也可是3层以上。
此外,布线层的形成方法并不限定于半添加方法。
也可列举出使用全添加方法和移除方法,或使用全添加方法和半添加方法两者的方法。
作为本发明的具有倒装芯片连接用焊球的布线板的实施方式,可列举出基于图3(d)所示布线板的制造方法的第1实施方式制成的方式、基于图5(d)所示布线板的制造方法的第2实施方式制成的方式,但并不限定于此。
图3(d)、图5(d)所示的均为在设有2层布线层的布线板的一侧形成用于与半导体元件的焊球形成直接倒装芯片连接的、突起状倒装芯片连接用焊球作为第1端子部,在另一侧,在覆盖布线部的阻焊层的开口以填埋开口的方式电镀形成第2端子部。在树脂材料层上形成线路的各布线层,其树脂材料层侧面向第1端子部侧,其线路面向第2端子部侧。在第1端子部侧未设置阻焊层而使各树脂材料层露出,第1端子部在其突起前端设置有平面部。各端子部的平面部均在一个平面上,在包含其侧面部的露出的表面全体上,形成由电镀层或非电解镀层构成的表面镀层。
另外,有关各部的材质等,可用上述制造方法的说明来代替,这里省略说明。
本发明的图3(d)所示的布线板及图5(d)所示的布线板的内插器的封装用基板310,例如,如图6所示,其第1端子部312与半导体元件310的焊球325形成直接倒装芯片连接。
此时,第1端子部312的突出的平面部312S统一在一个平面上,因此可以均匀地接合。
此外,第1端子部312的表面部是金属,化学性稳定,不会引起氧化,也无须通过焊剂处理而得。
基于本发明的布线板具有如上所述的能够与半导体元件的焊球形成直接倒装芯片连接的镀焊球或表面经镀形成的焊球。该基板线路可使与半导体元件的焊球直接倒装芯片连接的可靠性良好。
详细地说,据此,无须使用高价材料和工序形成的焊球,通过相对廉价的方法,可以形成应对更加微细化的芯片的焊球。
此外,特别是在图1乃至图3所示的布线板的制造方法中,代替非电解镀Ni、非电解镀Au,可以通过接合可靠性高的电镀形成焊球。
此外,与利用印刷方法形成的焊球相比,可减小焊球高度的偏差,因此,与半导体元件的接合也良好,实际装配时的成品率也提高了。
此外,应用无Pb焊接时,基板无须加热,对基板的损坏降低,成品率提高。
Claims (11)
1.布线板的制造方法,为具有由1层以上布线层构成的布线部、在布线部的一侧突出而设置的第1端子部、和在布线部的另一侧设置的第2端子部的布线板的制造方法,其特征在于,包括以下工序:
在由多层金属层构成的复合材料的表面形成具有第1端子部用开口的防护层的防护层形成工序,
从防护层的第1端子部用开口只蚀刻复合材料的第1金属层而形成孔部的蚀刻工序,
从防护层的第1端子部用开口以填埋孔部的方式通过电镀形成第1端子部的第1次电解电镀工序,
剥离防护层后在第1端子部设置树脂材料层形成布线层的布线层形成工序,
在布线层上设置具有第2端子部用开口的阻焊层的阻焊层形成工序,
在阻焊层的第2端子部用开口实施电镀形成第2端子部的第2次电镀工序,及
蚀刻除去复合材料的残留部的蚀刻除去工序。
2.权利要求1所述的布线板的制造方法,其特征在于,复合材料层压第1 Cu层、Ni层或Ti层、和第2 Cu层而构成。
3.权利要求1所述的布线板的制造方法,其特征在于,第1次电镀工序包括实施以下步骤:依次镀Au、镀Cu,或依次镀Au、镀Ni,或依次镀Au、镀Ni、镀Cu,或依次镀Pd、镀Cu,或依次镀Pd、镀Ni,或依次镀Pd、镀Ni、镀Cu,或依次镀Pd系合金、镀Cu,或依次镀Pd系合金、镀Ni,或依次镀Pd系合金、镀Ni、镀Cu、或镀Sn,或依次镀Sn、镀Cu、或镀Sn系合金,或依次镀Sn系合金、镀Cu。
4.布线板的制造方法,为具有由1层以上布线层构成的布线部、在布线部的一侧突出而设置的第1端子部、和在布线部的另一侧设置的第2端子部的布线板的制造方法,其特征在于,包括以下工序:
在由第1 Cu层、Ni层,和第2 Cu层构成的复合材料的表面形成具有第1端子部用开口的防护层的防护层形成工序,
以填埋防护层的第1端子部用开口的方式通过电镀形成第1端子部用电镀形成部的第1次电镀工序,
剥离防护层后在电镀形成部设置树脂层形成布线层的布线层形成工序,
在布线层上设置具有第2端子部用开口的阻焊层的阻焊层形成工序,
在阻焊层的第2端子部用开口实施电镀形成第2端子部的第2次电镀工序,
以复合材料的Ni层作为蚀刻阻止层的蚀刻除去第2 Cu层的工序,
以在Ni层上只覆盖第1端子部区域的方式,形成追加防护层,以该追加防护层作为耐蚀刻防护层,蚀刻Ni层、第1 Cu层使其贯通,形成由电镀形成部、第1 Cu层和Ni层组成的第1端子部的蚀刻工序及,
除去追加防护层后,在电镀形成部、第1 Cu层和Ni层上进一步实施非电解镀Au层,或依次实施非电解镀Ni层和非电解镀Au层的非电解镀工序。
5.权利要求1或4所述的布线板的制造方法,其特征在于,复合材料由包层材料构成。
6.权利要求1或4所述的布线板的制造方法,其特征在于,在布线层形成工序中,利用半添加方法形成布线层。
7.权利要求6所述的布线板的制造方法,其特征在于,布线层形成工序包括以下工序:
(A)层压由绝缘树脂构成的树脂材料层的层压工序;
(B)在上述层压工序中,将被层压的树脂层用激光开一个通孔形成用的孔的孔形成工序;
(C)包含形成的孔部的表面,在树脂材料层表面实施非电解镀Cu,在形成的Cu层上开口电路形成部以形成防护层后,在从防护层开口露出的Cu层上,以该Cu层作为导电层实施电镀Cu,然后,剥离上述防护层,蚀刻除去露出的通过非电解镀形成的Cu层,在形成通孔的同时形成电路部的电路部形成工序。
8.权利要求1或4所述的布线板的制造方法,其特征在于,在布线层形成工序中,使用全添加方法和移除方法,或使用全添加方法和半添加方法两者形成布线层。
9.布线板,其特征在于,具有:
由1层以上布线层构成的布线部,
和在布线部的一侧设置的多个第1端子部,
和在布线部的另一侧设置的多个第2端子部,
布线层有面向第1端子部一侧的树脂材料层,在布线部的第1端子部一侧未设置阻焊层,使树脂材料层露出,
各第1端子部在其前端有平面部,各第1端子部的平面部均在一个平面上,在整个各第1端子部的平面部上形成由电镀层或非电解镀层构成的表面镀层。
10.权利要求9所述的布线板,其特征在于,第1端子部的电镀层从表面侧依次形成镀Au层、镀Cu层,或依次形成镀Au层、镀Ni层,或依次形成镀Au层、镀Ni层、镀Cu层,或依次形成镀Pd层、镀Cu层,或依次形成镀Pd层、镀Ni层,或依次形成镀Pd层、镀Ni层、镀Cu层,或依次形成镀Pd系合金层、镀Cu层,或依次形成镀Pd系合金层、镀Ni层,或依次形成镀Pd系合金层、镀Ni层、镀Cu层、或镀Sn层,或依次形成镀Sn层、镀Cu层、或镀Sn系合金层,或依次形成镀Sn系合金层、镀Cu层。
11.权利要求9所述的布线板,其特征在于,第1端子的非电解镀层为非电解镀Au层,或从表面侧依次为非电解镀Ni层、非电解镀Au层。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101835347A (zh) * | 2009-03-12 | 2010-09-15 | 三星电子株式会社 | 印刷电路板装配体及其制造方法 |
US7911038B2 (en) | 2006-06-30 | 2011-03-22 | Renesas Electronics Corporation | Wiring board, semiconductor device using wiring board and their manufacturing methods |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101251660B1 (ko) * | 2006-09-20 | 2013-04-05 | 엘지이노텍 주식회사 | 인쇄회로기판과 인쇄회로기판을 이용한 피씨비 카드,그리고 인쇄회로기판의 제조방법 및 pcb 카드의제조방법 |
KR101251659B1 (ko) * | 2006-09-20 | 2013-04-05 | 엘지이노텍 주식회사 | 인쇄회로기판과 인쇄회로기판을 이용한 피씨비 카드,그리고 인쇄회로기판의 제조방법 및 pcb 카드의제조방법 |
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US20090148594A1 (en) * | 2007-08-15 | 2009-06-11 | Tessera, Inc. | Interconnection element with plated posts formed on mandrel |
KR100979818B1 (ko) * | 2007-12-13 | 2010-09-06 | 삼성전기주식회사 | 인쇄회로기판 제조방법 |
KR101032704B1 (ko) * | 2009-04-14 | 2011-05-06 | 삼성전기주식회사 | 인쇄회로기판 제조방법 |
JP5147779B2 (ja) * | 2009-04-16 | 2013-02-20 | 新光電気工業株式会社 | 配線基板の製造方法及び半導体パッケージの製造方法 |
US8390083B2 (en) | 2009-09-04 | 2013-03-05 | Analog Devices, Inc. | System with recessed sensing or processing elements |
KR101089647B1 (ko) * | 2009-10-26 | 2011-12-06 | 삼성전기주식회사 | 단층 패키지 기판 및 그 제조방법 |
JP5433543B2 (ja) * | 2010-09-27 | 2014-03-05 | ローム株式会社 | 半導体装置 |
WO2012051340A1 (en) | 2010-10-12 | 2012-04-19 | Analog Devices, Inc. | Microphone package with embedded asic |
JP5800674B2 (ja) * | 2011-10-25 | 2015-10-28 | 日本特殊陶業株式会社 | 配線基板及びその製造方法 |
US9847462B2 (en) | 2013-10-29 | 2017-12-19 | Point Engineering Co., Ltd. | Array substrate for mounting chip and method for manufacturing the same |
US9666558B2 (en) | 2015-06-29 | 2017-05-30 | Point Engineering Co., Ltd. | Substrate for mounting a chip and chip package using the substrate |
TWI791924B (zh) * | 2018-11-15 | 2023-02-11 | 日商山榮化學股份有限公司 | 通路配線形成用基板及通路配線形成用基板之製造方法和半導體裝置安裝零件 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59208756A (ja) | 1983-05-12 | 1984-11-27 | Sony Corp | 半導体装置のパツケ−ジの製造方法 |
JP2840316B2 (ja) * | 1989-09-06 | 1998-12-24 | 新光電気工業株式会社 | 半導体装置およびその製造方法 |
US5738931A (en) * | 1994-09-16 | 1998-04-14 | Kabushiki Kaisha Toshiba | Electronic device and magnetic device |
JPH11135551A (ja) * | 1997-10-31 | 1999-05-21 | Sony Corp | 半導体装置及び半導体素子の実装方法 |
DE19822794C1 (de) * | 1998-05-20 | 2000-03-09 | Siemens Matsushita Components | Mehrfachnutzen für elektronische Bauelemente, insbesondere akustische Oberflächenwellen-Bauelemente |
JP2000183223A (ja) * | 1998-12-16 | 2000-06-30 | Dainippon Printing Co Ltd | 配線部材の製造方法と配線部材 |
JP2001185653A (ja) * | 1999-10-12 | 2001-07-06 | Fujitsu Ltd | 半導体装置及び基板の製造方法 |
JP3629178B2 (ja) * | 2000-02-21 | 2005-03-16 | Necエレクトロニクス株式会社 | フリップチップ型半導体装置及びその製造方法 |
JP3968554B2 (ja) * | 2000-05-01 | 2007-08-29 | セイコーエプソン株式会社 | バンプの形成方法及び半導体装置の製造方法 |
US6678952B2 (en) * | 2000-08-03 | 2004-01-20 | Tessera, Inc. | Method of making a microelectronic package including a component having conductive elements on a top side and a bottom side thereof |
US6889429B2 (en) * | 2001-03-26 | 2005-05-10 | Semiconductor Components Industries, L.L.C. | Method of making a lead-free integrated circuit package |
TWI312166B (en) * | 2001-09-28 | 2009-07-11 | Toppan Printing Co Ltd | Multi-layer circuit board, integrated circuit package, and manufacturing method for multi-layer circuit board |
US6687952B1 (en) * | 2002-01-07 | 2004-02-10 | Hmi Industries, Inc. | Wet vacuum cleaner attachment for vacuum cleaners |
JP4181778B2 (ja) * | 2002-02-05 | 2008-11-19 | ソニー株式会社 | 配線基板の製造方法 |
JP3565835B1 (ja) * | 2003-04-28 | 2004-09-15 | 松下電器産業株式会社 | 配線基板およびその製造方法ならびに半導体装置およびその製造方法 |
TWI250834B (en) * | 2004-11-03 | 2006-03-01 | Phoenix Prec Technology Corp | Method for fabricating electrical connections of circuit board |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7911038B2 (en) | 2006-06-30 | 2011-03-22 | Renesas Electronics Corporation | Wiring board, semiconductor device using wiring board and their manufacturing methods |
US8389414B2 (en) | 2006-06-30 | 2013-03-05 | Nec Corporation | Method of manufacturing a wiring board |
CN101835347A (zh) * | 2009-03-12 | 2010-09-15 | 三星电子株式会社 | 印刷电路板装配体及其制造方法 |
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US20080106880A1 (en) | 2008-05-08 |
US20060011382A1 (en) | 2006-01-19 |
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US7325301B2 (en) | 2008-02-05 |
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