CN1501492A - Integrated circuit structure with air gap and manufacturing method thereof - Google Patents
Integrated circuit structure with air gap and manufacturing method thereof Download PDFInfo
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- CN1501492A CN1501492A CNA200310103485A CN200310103485A CN1501492A CN 1501492 A CN1501492 A CN 1501492A CN A200310103485 A CNA200310103485 A CN A200310103485A CN 200310103485 A CN200310103485 A CN 200310103485A CN 1501492 A CN1501492 A CN 1501492A
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- 239000002184 metal Substances 0.000 claims abstract description 174
- 238000000034 method Methods 0.000 claims abstract description 77
- 238000005530 etching Methods 0.000 claims description 38
- 238000005229 chemical vapour deposition Methods 0.000 claims description 24
- 238000010276 construction Methods 0.000 claims description 16
- 239000011435 rock Substances 0.000 claims description 14
- 238000012545 processing Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 8
- 230000010415 tropism Effects 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
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- 230000015572 biosynthetic process Effects 0.000 abstract description 4
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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Abstract
An air gap structure and formation method for substantially reducing capacitance in a dual damascene based interconnect structure is disclosed. The air gap extends above, and may also additionally extend below, the damascene interconnects desired to be isolated thus minimizing fringing fields between the lines. Multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels.
Description
Technical field
The present invention provides a kind of high-effect (high performance) integrated circuit, and (integratedcircuit, IC) structure refer to a kind of integrated circuit structure with airspace (air gap) and preparation method thereof especially.The present invention is particularly useful for the logic IC of high operational effectiveness of needs and high integration or conformability IC (system combination chip (system-on-chip, SOC)) field for example.The method that the present invention forms the integrated circuit structure with airspace then provides the semiconductor manufacturing industry, and person one can reach the total solution of volume production (mass production) scale.
Background technology
Along with the progress of semiconductor fabrication, the semiconductor subassembly design size that is made on the semiconductor wafer is also dwindled constantly, and has evolved to deep-sub-micrometer from generation to generation.Yet, the result that integrated circuit density constantly improves, but cause time delay (RC delay) problem between each plain conductor day by day remarkable to the influence of the operational effectiveness of integrated circuit, especially working as processing procedure live width (line width) drops to below 0.15 micron, even during the manufacture of semiconductor below 0.13 micron, time delay is more obvious to the influence that the assembly operational effectiveness is caused.
Time delay between the metal interconnect can be expressed with the product mutually of the parasitic capacitance (C) between the resistance value (R) of plain conductor and plain conductor.The metal interconnect time delay phenomenon that reduces semiconductor chip is mainly carried out towards both direction at present: first is to use the lower metal material of resistance value as plain conductor, second is the parasitic capacitance between each plain conductor of reduction, reduces power consumption simultaneously with the transmission speed that increases the metal interconnect.
In the known practice, the method that reduces the parasitic capacitance between each plain conductor mainly is to adopt as FSG, HSQ, FLAREK
TMOr SiLK
TMDeng low-k (k＜3) material.The characteristic of these advanced low-k materials need include low-k, low surface conductance degree (surfaceconductance, surface resistivity＞10 basically
15Ω), low stress (compressive orweak tensile＞30MPa), excellent mechanical strength and chemistry and thermal stability, low water absorbable and process compatibility (process compatibility).Yet many advanced low-k materials all have serious reliability (reliability) and integrate the problem that the back produces with metal.Therefore, before new advanced low-k materials from generation to generation comes out as yet, overcome the operational effectiveness that time delay causes as process technique how and reduce problem, be worth inquiring into and improved problem just become one.
Because the desired dielectric constant of air approaches 1, therefore use the megohmite insulant of air (air) as the metal interconnect, also be one of solution that reduces parasitic capacitance between plain conductor.Though the technology that many low-k characteristics of utilizing air are applied to integrated circuit comes forth out, major part does not but have volume production and is worth.For example in No. the 4920639th, United States Patent (USP), Lan Y.K.Yee promptly discloses the method that a kind of making has the integrated circuit of airspace, its practice is to utilize photoresistance as the temporary transient dielectric layer between the metal interconnect earlier, after waiting to finish the making of metal interconnect, utilize removal of solvents part even all photoresistances again, and between the metal interconnect, form a large amount of airspaces.This practice can make the metal interconnect almost completely by built on stilts, and can't obtain enough supports, causes integrated circuit to be subjected to mechanical force easily and damages.
In addition, United States Patent (USP) discloses a kind of method that forms in the silica layer of airspace between the metal interconnect No. 6130151, its practice is to form a silica layer and a nitrogen silicon layer earlier on metal level, on the nitrogen silicon layer, define plurality of openings via a little shadow (photo lithography) processing procedure then, carry out an etch process again along aforesaid opening etching silica layer and nitrogen silicon layer or etching silica layer only in regular turn, to form the airspace in silica layer.
United States Patent (USP) then discloses a kind of method of airspace between the metal interconnect that form for No. 5949143, its practice is to form a dual-damascene metal interconnect earlier in dielectric layer, and then deposit an etch stop layer (etch stop layer) on metal interconnect and dielectric layer, but expose the dielectric layer of part, carry out an etch process at last and fully remove the dielectric layer that not etched stop layer covers, to form the airspace between and the etch stop layer online in this metal respectively.Other also all discloses the various method that forms the airspace between the metal interconnect respectively such as United States Patent (USP) case numbers 5324683,6077767,6083821 and 5407860 etc., seldom gives unnecessary details at this.
Yet above-mentioned these known techniques are too complicated except processing procedure, outside being difficult to integrate, also face some reliability issues simultaneously, and for example the metal interconnect can't obtain enough supports.The present invention then can provide a total solution, to solve the bottleneck that known techniques can't break through, can reach a volume production scale.
Summary of the invention
Main purpose of the present invention is at integrated circuit structure that a kind of high operation usefulness is provided and preparation method thereof.
Another object of the present invention is providing a kind of integrated circuit structure that has the airspace and enough support and preparation method thereof, making a large amount of airspaces between the metal interconnect, and then reaches the effect of the time delay that reduces the metal interconnect.
According to purpose of the present invention, a kind of high performance integrated circuit structure that has a large amount of airspaces simultaneously and make the interconnect metallic circuit possess enough supports is at first disclosed.This integrated circuit structure includes a ground floor metal conductive line pattern, is formed on the bottom; One second layer metal wire pattern is formed at this ground floor metal conductive line pattern top; One supporting construction is formed between this ground floor metal conductive line pattern and this second layer metal wire pattern, is used for supporting this second layer metal wire pattern, and wherein this supporting construction includes a dielectric layer through anisotropic etching; And, be formed between this second layer metal wire pattern by the formed a plurality of airspaces of a cap rock.
The present invention discloses a kind of method of making above-mentioned high performance integrated circuit simultaneously.In most preferred embodiment of the present invention, this method at first forms a bottom in a substrate, and forms a ground floor metal conductive line pattern on this bottom.Then on ground floor metal conductive line pattern and bottom, form a dielectric layer, and on this dielectric layer, form a second layer metal wire pattern.Utilize ground floor metal conductive line pattern and second layer metal wire pattern as an etch shield subsequently, this dielectric layer and this bottom of anisotropic etching part, to form plurality of grooves, make remaining dielectric layer constitute the supporting construction of second layer metal wire pattern simultaneously.Carry out a chemical vapor deposition (CVD) processing procedure at last, with deposition one cap rock on respectively this groove surfaces and second layer metal wire pattern, and capping this groove respectively, form a plurality of airspaces.
Because the photoresist layer that the present invention utilizes metal layer pattern or is used to define metal layer pattern is as etch shield, come the dielectric layer of metal layer pattern below is carried out a first-class tropism's etching and an anisotropic etching, in between the metal interconnect, forming a plurality of airspaces, and then reach the effect of the time delay that reduces the metal interconnect.In addition, utilize the formed integrated circuit structure of the inventive method to have and make the metal interconnect or get the dielectric layer framework that enough supports, can improve the reliability of integrated circuit.
Description of drawings
Fig. 1 has the airspace or the generalized section of the integrated circuit structure of air (air bridge) far apart in the preferred embodiment of the present invention;
Fig. 2 to Fig. 6 is for having the manufacture method schematic diagram of the integrated circuit of airspace in the preferred embodiment of the present invention;
Fig. 7 and Fig. 8 are the manufacturing method thereof schematic diagram of the embodiment of the invention two;
Fig. 9 and Figure 10 are the manufacturing method thereof schematic diagram of the embodiment of the invention three;
Figure 11 to Figure 14 is for making the manufacture method schematic diagram of the integrated circuit with airspace, and this airspace is to be formed in the excessive zone, space between lead.
Symbol description:
The 10-semiconductor chip
The 11-substrate
The 12-bottom
13-ground floor metal pattern
The 13a-metal plug
The 14-dielectric layer
The 15-second layer metal
The 16-photoresist layer
17-second layer metal pattern
The 17a-dummy pattern
17b-sidewall
The 18-hole
The 18a-airspace
The 19-cap rock
The 20-photoresist layer
The 22a-airspace
The 22b-airspace
The 23a-airspace
The 23b-airspace
The 24-dielectric layer
The 24a-connector
The 26-dielectric layer
The 26a-connector
The 28-dielectric layer
The M1-metal pattern layer
The M2-metal pattern layer
The M3-metal pattern layer
Embodiment
Please refer to Fig. 1, Fig. 1 is for having the generalized section of the integrated circuit structure of airspace (air gap) or air (air bridge) far apart in the preferred embodiment of the present invention.As shown in Figure 1, semiconductor chip 10 includes a substrate 11, can be a monocrystal silicon substrate or other semiconductor-based end.On the surface of substrate 11, can include the semiconductor subassembly that has completed, for example memory cell (memory cell), MOS transistor, resistance or electric capacity or the like.Because these assemblies are not emphasis of the present invention, therefore be not presented among the icon.Bottom 12 is formed on the substrate 11, and wherein bottom 12 can be constituted by single dielectric layer, or is made of multilayer dielectric layer.Three-layer metal patterned layer (M1, M2 and M3), each metal plug 24a and 26a and dielectric layer 24,26 and 28 are formed on the bottom 12, constitute one deck and stack long-pending metal interconnect framework.Herein, metal pattern layer (M1, M2 and M3) is meant the metal conductive line pattern that is defined in one deck.Definition metal conductive line pattern (M1, M2 and M3) and metal plug 24a and 26a can utilize traditional metal sputtering and etching technique, and 24,26 and 28 of dielectric layers can utilize general chemical vapour deposition (CVD) or rotary coating mode to form.
In Fig. 1, airspace 22a and 22b are formed between the metal pattern layer M2, and extend downward dielectric layer 24, even more extend downward in the bottom 12.Airspace 23a and 23b then are formed between the metal pattern layer M3, and extend downward dielectric layer 26.Wherein airspace 22a and 22b are coated by dielectric layer 26 to form, and have prominent outstanding (overhang) enclosed construction at 22b top, airspace.Airspace 23a and 23b are coated by dielectric layer 28 to form.Airspace 22a and airspace 23a present connected state, and this is that anisotropic etching digs wears the airspace 22a that was originally coated by dielectric layer 26 owing to form in the process of airspace 23a.In other embodiments of the invention, dug the airspace 22a that wears and to utilize dielectric layer 28 to be closed once more, and formed independently two airspace 22a and 23a.This can the ladder when adjusting dielectric layer 28 covers (step coverage) degree and reaches.
Embodiment one
Please refer to Fig. 2 to Fig. 6, Fig. 2 to Fig. 6 is for having the manufacture method schematic diagram of the integrated circuit structure of airspace according to the present invention.As shown in Figure 2, semiconductor chip 10 includes a substrate 11 and a bottom 12 is positioned on the substrate 11.Ground floor metal pattern 13 can be formed on the bottom 12 via sputter, little shadow and etching supervisor.Then deposition one dielectric layer 14 on ground floor metal pattern 13 and bottom 12 then via little shadow, etching, deposition and cmp processing procedures such as (CMP), is made metal plug 13a again within dielectric layer 14.Form a metal level 15 subsequently on dielectric layer 14 and metal plug 13a, and form a photoresist layer 16 through definition in metal level 15 surfaces.Photoresist layer 16 defines a second layer metal pattern on metal level 15.
Then as shown in Figure 3, utilize photoresist layer 16 metal level 15 to be carried out etching for etch shield, forming a second layer metal pattern 17, and be electrically connected with ground floor metal pattern 13 as contact plunger (via plug) by metal plug 13a in dielectric layer 14 and metal plug 13a top.Remove photoresist layer 16 subsequently.The first metal layer pattern 13 can be made of aluminum metal, aluminium copper or copper metal with second layer metal pattern 17.Metal plug 13a can be made of tungsten (W), titanium/titanium nitride (Ti/TiN).The composition of dielectric layer 14 can be silicon dioxide, fluorine silex glass (fluorinatedsilicate glass, FSG) or other utilize electricity slurry enhanced chemical vapor deposition method (plasma-enhanced chemical vapor deposition, PECVD) or high density plasma enhanced chemical vapor deposition method (high-density plasma chemical vapor deposition, HDPCVD) formed dielectric layer.
What need emphasize is that the integrated circuit structure with airspace of the present invention also can be applicable in the copper metal interconnect structure.At this moment, above-mentioned ground floor metal pattern 13, metal plug 13a and second layer metal pattern 17 also can utilize dual damascene (dual damascene) processing procedure to be formed among the dielectric layer.Double-insert process is the known technology of known this skill person, therefore repeats no more.Known this skill person should be applied in the present invention in the copper wiring easily with reference to the present invention.
As shown in Figure 4, with second layer metal pattern 17 as etch shield, carry out an anisotropic (anisotropic) etch process, remove the dielectric layer 14 that a desired depth is not covered by second layer metal pattern 17 vertically downward, to form plurality of grooves 18 within dielectric layer 14.Wherein, etched time (time-mode) can suitably adjust the depth of groove that extends in the bottom 12 by control, but this depth of groove is a principle with the electrical performance that does not influence assembly.
Then as shown in Figure 5, dielectric layer 14 in the groove 18 is carried out first-class tropism (isotropic) dry ecthing or wet etching processing procedure, to enlarge the area of groove 18 further, form a undercut profile (undercut profile) under second layer metal pattern 17.Be noted that, aforesaid these tropism's etch process are to be a step optionally, that is these tropism's etch process also can omit and not carry out, on the other hand, the main purpose of carrying out these tropism's etch process is the area that optionally enlarges groove 18, and therefore only part removes the dielectric layer 14 that is positioned under the second layer metal pattern 17.The supporting construction that is used to support second layer metal pattern 17 includes dielectric layer 14 and metal plug 13a.
As Fig. 5 and shown in Figure 6, then carry out a chemical vapor deposition (CVD) processing procedure, in surface deposition one cap rock (cap layer) 19 of groove 18 and second layer metal wire pattern 17, and cover groove 18 and form a plurality of airspace 18a.It should be noted that, when sedimentary cover 19, must allow cap rock 19 form prominent outstanding (overhang) in the corner portions located of second layer metal wire pattern 17 via the process parameter of adjusting chemical vapour deposition (CVD) as far as possible, apace groove 18 being covered, and then reduce cap rock 19 and be deposited into situation in the groove 18.
Embodiment two
See also Fig. 7 and Fig. 8, Fig. 7 and Fig. 8 are the manufacturing method thereof schematic diagram of another embodiment of the present invention.Wherein, Fig. 7 is the fabrication steps of continuity Fig. 2, through processing procedures such as overexposure, development and etchings, goes up formation one second layer metal pattern 17 in dielectric layer 14 and metal plug 13a, and does not remove the photoresist layer 16 that is used to define second layer metal pattern 17.As shown in Figure 8, the inventive method can photoresist layer 16 as etch shield, carry out figure four and anisotropic etching and the isotropic etch process shown in the figure five in regular turn, after etch metal layers 15 immediately in dielectric layer 14 etching form plurality of grooves 18, and groove 18 forms undercut profile (undercut profile) under second layer metal pattern 17.That is to say, after finishing second layer metal pattern 17, adjust the composition of etching gas immediately, with while (in-situ) etching dielectric layer 14.Just remove photoresist layer 16 at last, and carry out chemical vapor deposition (CVD) processing procedure shown in Figure 6,, cover groove 18 and form a plurality of airspace 18a in surface deposition one cap rock (cap layer) 19 of groove 18 and second layer metal wire pattern 17.
Embodiment three
According to the manufacturing method thereof of Fig. 4 that the present invention is exposed in, Fig. 5 and making airspace 18a shown in Figure 8, also may be implemented in arbitrary layer of metal pattern layer or each layer metal pattern layer of multi-metal interconnect processing procedure.See also Fig. 9, finish continuously after three-layer metal patterned layer (M1, M2 and M3) and each the metal plug 13a, utilize uppermost metal pattern layer M3 as etch shield again, and utilize metal pattern layer M2, metal pattern layer M1 as etching stopping layer, carrying out an anisotropic etching, and between the multi-metal interconnect, make a large amount of air grooves 18.In addition, as shown in figure 10, the present invention can add a barrier layer (stop layer) 12a in bottom 12, just can avoid over etching thus, and destroys the assembly under the bottom 12.
Embodiment four
For fear of taking place when excessive as space between the lead of second layer metal pattern 17 among Figure 10, to such an extent as to anyway adjust the process parameter of chemical vapor deposition process, cap rock 19 all can be deposited within the groove 18, thereby the situation of the volume minimizing of generation airspace 18a, can on bigger zone, space between plain conductor, form dummy pattern (dummy pattern).See also Figure 11 to Figure 14, Figure 11 to Figure 14 is that the excessive metal interconnect in space is made the schematic diagram of airspace between lead.At first as shown in figure 11, the space is excessive when between the lead of second layer metal pattern 17, and the present invention can suitably add dummy pattern (dummy pattern) 17a between excessive lead on the dielectric layer in the space 14.Wherein, the formation method of dummy pattern 17a can add a plurality of dummy pattern in the layout (layout) of the light shield of second layer metal pattern 17, second layer metal pattern 17 and dummy pattern 17a are formed on the dielectric layer 14 simultaneously, dwindle space between the lead of second layer metal pattern 17 whereby.Then carry out Fig. 4 more in regular turn to anisotropic etching, isotropic etching and chemical vapor deposition process shown in Figure 6, in dielectric layer 14, to form a plurality of airspace 18a, as shown in figure 12.
As shown in figure 13, when space between the lead of second layer metal pattern 17 is big, method of the present invention also can be after forming second layer metal pattern 17, deposition one thin layer (not shown) utilizes an etch process to form sidewall (spacer) 17b with the side in second layer metal pattern 17 on second layer metal pattern 17 more earlier.Wherein, the method that forms the sub-17b of sidewall is known by known this skill person, therefore repeats no more.Because the formation of the sub-17b of sidewall, thereby dwindled space between lead.Then carry out anisotropic etching, isotropic etching and the chemical vapor deposition process shown in the figure three to figure five more in regular turn, in dielectric layer 14, to form a plurality of airspace 18a.
As shown in figure 14, the space is excessive when between the lead of second layer metal pattern 17, method of the present invention also can be after having formed second layer metal pattern 17, utilize a photoresist layer 20 to be covered on the bigger second layer metal pattern 17 in space between lead again, and only expose the less second layer metal pattern 17 in space between lead, or utilize photoresist layer 20 and between lead 17 in the excessive second layer metal pattern in space form at least one dummy pattern.Then carry out Fig. 4 and anisotropic etching, isotropic etching shown in Figure 5 more in regular turn, in the dielectric layer 14 that is not covered, to form plurality of grooves 18 by photoresist layer 20.Remove photoresist layer 20 then, and carry out chemical vapor deposition process shown in Figure 6, in dielectric layer 14, to form a plurality of airspace 18a.
Compared to known method, characteristics of the present invention are directly to utilize metal conductive line pattern or usefulness As etch shield, come metal conductive line pattern below in the photoresist layer of definition metal conductive line pattern Dielectric layer carries out first-class tropism's etching and an anisotropic etching, and is multiple to form between the metal interconnect Several airspaces, and then reach the effect of the time delay that reduces the metal interconnect. At each gold All there is an interlayer dielectric layer (interlayer dielectric) to make metal inline under the genus lead Machine obtains enough supports. The formed airspace of the inventive method can be along with every one deck metal The definition of wire pattern is made simultaneously, or after finishing several layers of metal conductive line pattern with the gold of each layer Belonging to wire pattern is that etch shield is carried out etching once, to form a large amount of skies in integrated circuit The gas interval, and can make simultaneously that all can to obtain dielectric layer under each layer metal conductive line pattern enough Support.
Claims (25)
1. integrated circuit structure with airspace is characterized in that described structure includes:
One substrate has a bottom on it;
One ground floor metal conductive line pattern is formed on this bottom;
One second layer metal wire pattern is formed at this ground floor metal conductive line pattern top;
One supporting construction is formed between this ground floor metal conductive line pattern and this second layer metal wire pattern, is used for supporting this second layer metal wire pattern, and wherein this supporting construction includes a dielectric layer through isotropic etching; And
By the formed a plurality of airspaces of a cap rock, be formed between this second layer metal wire pattern.
2. integrated circuit structure according to claim 1 is characterized in that: this substrate is a silicon base.
3. integrated circuit structure according to claim 1 is characterized in that: this ground floor metal conductive line pattern and this second layer metal wire pattern all are made of copper.
4. integrated circuit structure according to claim 1 is characterized in that: this ground floor metal conductive line pattern and this second layer metal wire pattern all include aluminum metal.
5. integrated circuit structure according to claim 1 is characterized in that: this supporting construction includes the contact plunger (via plug) of this ground floor metal conductive line pattern of at least one electrical connection and this second layer metal wire pattern in addition.
6. integrated circuit structure according to claim 1, it is characterized in that: this cap rock is to utilize electricity slurry enhanced chemical vapor deposition method (plasma-enhanced CVD, PECVD) or the high density plasma enhanced chemical vapor deposition method (high density plasma CVD HDPCVD) forms.
7. integrated circuit structure according to claim 1 is characterized in that: the supporting construction of this second layer metal wire pattern has a undercut profile.
8. integrated circuit structure with airspace is characterized in that described integrated circuit structure includes:
One ground floor metal conductive line pattern is formed on the bottom;
One second layer metal wire pattern is formed at this ground floor metal conductive line pattern top;
One supporting construction is formed between this ground floor metal conductive line pattern and this second layer metal wire pattern, is used for supporting this second layer metal wire pattern; And
By the formed a plurality of airspaces of a cap rock, be formed between this second layer metal wire pattern.
9. integrated circuit structure according to claim 8 is characterized in that: this supporting construction includes the contact plunger (via plug) of this ground floor metal conductive line pattern of at least one electrical connection and this second layer metal wire pattern.
10. integrated circuit structure according to claim 8 is characterized in that: this supporting construction includes a dielectric layer through isotropic etching.
11. integrated circuit structure according to claim 8 is characterized in that: this second layer metal wire pattern includes a dummy pattern (dummy pattern), makes space between the plain conductor that dwindles this second layer metal wire pattern.
12. integrated circuit structure according to claim 8 is characterized in that: this second layer metal wire pattern includes on each sidewall that sidewall is formed at this second layer metal wire pattern.
13. integrated circuit structure according to claim 8 is characterized in that: this cap rock is to utilize electricity slurry enhanced chemical vapor deposition method (PECVD) or high density plasma enhanced chemical vapor deposition method (HDPCVD) to form.
14. the manufacture method with integrated circuit of airspace, this manufacture method includes:
One substrate is provided, has a bottom on it;
On this bottom, form a ground floor metal conductive line pattern;
On this ground floor metal conductive line pattern and this bottom, form a dielectric layer;
On this dielectric layer, form a second layer metal wire pattern;
Utilize this second layer metal wire pattern and this second layer metal wire pattern as an etch shield, this dielectric layer of anisotropic etching to form plurality of grooves, makes remaining this dielectric layer constitute the supporting construction of this second layer metal wire pattern simultaneously; And
Carry out a chemical vapor deposition (CVD) processing procedure,,, form a plurality of airspaces with this groove of capping with deposition one cap rock on this groove surfaces and this second layer metal wire pattern.
15. manufacture method according to claim 14, wherein this substrate is a silicon base.
16. manufacture method according to claim 14, wherein this ground floor metal conductive line pattern is to be embedded on this bottom.
17. manufacture method according to claim 14, wherein this second layer metal wire pattern is to be embedded on this dielectric layer.
18. manufacture method according to claim 14, wherein this ground floor metal conductive line pattern and this second layer metal wire pattern all are made of copper.
19. manufacture method according to claim 14, wherein this ground floor metal conductive line pattern and this second layer metal wire pattern are all to include aluminum metal.
20. manufacture method according to claim 14, wherein this manufacture method is after this dielectric layer of anisotropic etching and this bottom, other includes the supporting construction of this second layer metal wire pattern of isotropic etching, to form a undercut profile, enlarges the area of this groove.
21. the manufacture method with integrated circuit of airspace includes:
One substrate is provided, has a bottom on it;
On this bottom, form a dielectric layer;
On this dielectric layer, form a metal conductive line pattern; And
Utilize this metal conductive line pattern as an etch shield, this dielectric layer to one desired depth of etching to form plurality of grooves in this dielectric layer, makes remaining this dielectric layer constitute the supporting construction of this metal conductive line pattern simultaneously.
22. manufacture method according to claim 21, wherein this metal conductive line pattern is in constituting space (interline spacing) between a plurality of leads on this dielectric layer, and this plurality of grooves is to be formed between these a plurality of leads in this dielectric layer in the space.
23. manufacture method according to claim 21, wherein the method for this dielectric layer of etching is to utilize an anisotropic etching technology.
24. manufacture method according to claim 21, wherein this metal conductive line pattern is to be embedded on this dielectric layer.
25. manufacture method according to claim 21, wherein this manufacture method is after this dielectric layer of etching, and other includes the following step:
Deng the supporting construction of this metal conductive line pattern of tropism (isotropic) etching,, enlarge the area of this groove to form a undercut profile (undercut profile); And
(with deposition one cap rock (cap layer) on this groove surfaces and this metal conductive line pattern, this groove of capping simultaneously forms a plurality of airspaces for chemical vapor deposition, CVD) processing procedure to carry out a chemical vapour deposition (CVD).
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/295,080 | 2002-11-15 | ||
| US10/295,062 US6917109B2 (en) | 2002-11-15 | 2002-11-15 | Air gap structure and formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device |
| US10/295,719 US7449407B2 (en) | 2002-11-15 | 2002-11-15 | Air gap for dual damascene applications |
| US10/295,080 US7138329B2 (en) | 2002-11-15 | 2002-11-15 | Air gap for tungsten/aluminum plug applications |
| US10/295,719 | 2002-11-15 | ||
| US10/295,062 | 2002-11-15 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101458489A Division CN100514597C (en) | 2002-11-15 | 2003-11-07 | Manufacturing method for IC with air interval |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1501492A true CN1501492A (en) | 2004-06-02 |
| CN100372113C CN100372113C (en) | 2008-02-27 |
Family
ID=32719000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101034859A Expired - Lifetime CN100372113C (en) | 2002-11-15 | 2003-11-07 | Integrated circuit structure with air gap and manufacturing method thereof |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2004172620A (en) |
| CN (1) | CN100372113C (en) |
| TW (1) | TWI232496B (en) |
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| CN101299419B (en) * | 2007-04-30 | 2010-12-08 | 国际商业机器公司 | Semiconductor device and manufacture method thereof |
| CN102891100A (en) * | 2011-07-22 | 2013-01-23 | 中芯国际集成电路制造(上海)有限公司 | Shallow-trench isolation structure and formation method thereof |
| WO2013075375A1 (en) * | 2011-11-25 | 2013-05-30 | Shanghai Ic R & D Center Co., Ltd. | Copper interconnect structure and method for manufacturing the same |
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| CN106935544A (en) * | 2015-12-30 | 2017-07-07 | 台湾积体电路制造股份有限公司 | The formed method of semiconductor device |
| TWI708330B (en) * | 2018-12-27 | 2020-10-21 | 南亞科技股份有限公司 | Semiconductor structure and method of manufacturing the same |
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| US6838354B2 (en) * | 2002-12-20 | 2005-01-04 | Freescale Semiconductor, Inc. | Method for forming a passivation layer for air gap formation |
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| US8587121B2 (en) * | 2010-03-24 | 2013-11-19 | International Business Machines Corporation | Backside dummy plugs for 3D integration |
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| EP0393635B1 (en) * | 1989-04-21 | 1997-09-03 | Nec Corporation | Semiconductor device having multi-level wirings |
| GB2247986A (en) * | 1990-09-12 | 1992-03-18 | Marconi Gec Ltd | Reducing interconnection capacitance in integrated circuits |
| JP2555940B2 (en) * | 1993-07-27 | 1996-11-20 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| JPH07326670A (en) * | 1994-05-31 | 1995-12-12 | Texas Instr Inc <Ti> | Semiconductor integrated circuit device |
| JPH08148556A (en) * | 1994-11-16 | 1996-06-07 | Sony Corp | Semiconductor device and its manufacture |
| CN1204867A (en) * | 1997-06-20 | 1999-01-13 | 日本电气株式会社 | Semiconductor device, and method of manufacturing same |
| US6184121B1 (en) * | 1997-07-10 | 2001-02-06 | International Business Machines Corporation | Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same |
| JP2000058549A (en) * | 1998-08-04 | 2000-02-25 | Nec Corp | Formation of integrated circuit wiring |
| JP2000269327A (en) * | 1999-03-15 | 2000-09-29 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US6413852B1 (en) * | 2000-08-31 | 2002-07-02 | International Business Machines Corporation | Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material |
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2003
- 2003-11-07 CN CNB2003101034859A patent/CN100372113C/en not_active Expired - Lifetime
- 2003-11-11 TW TW092131566A patent/TWI232496B/en not_active IP Right Cessation
- 2003-11-14 JP JP2003385281A patent/JP2004172620A/en active Pending
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Also Published As
| Publication number | Publication date |
|---|---|
| TW200415704A (en) | 2004-08-16 |
| JP2004172620A (en) | 2004-06-17 |
| CN100372113C (en) | 2008-02-27 |
| TWI232496B (en) | 2005-05-11 |
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