CN104362172B - Semiconductor chip structure with end ring and its manufacturing method - Google Patents
Semiconductor chip structure with end ring and its manufacturing method Download PDFInfo
- Publication number
- CN104362172B CN104362172B CN201410545270.0A CN201410545270A CN104362172B CN 104362172 B CN104362172 B CN 104362172B CN 201410545270 A CN201410545270 A CN 201410545270A CN 104362172 B CN104362172 B CN 104362172B
- Authority
- CN
- China
- Prior art keywords
- groove
- end ring
- semiconductor
- well region
- main core
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 97
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 239000010410 layer Substances 0.000 claims abstract description 41
- 229920000642 polymer Polymers 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 239000011241 protective layer Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 21
- -1 polytetrafluoroethylene Polymers 0.000 claims description 8
- 229920001343 polytetrafluoroethylene Polymers 0.000 claims description 8
- 239000004810 polytetrafluoroethylene Substances 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 8
- 239000011347 resin Substances 0.000 claims description 8
- CMLFRMDBDNHMRA-UHFFFAOYSA-N 2h-1,2-benzoxazine Chemical compound C1=CC=C2C=CNOC2=C1 CMLFRMDBDNHMRA-UHFFFAOYSA-N 0.000 claims description 4
- 239000004952 Polyamide Substances 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 4
- 229920000090 poly(aryl ether) Polymers 0.000 claims description 4
- 229920002647 polyamide Polymers 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 229920000292 Polyquinoline Polymers 0.000 claims description 3
- 229920006260 polyaryletherketone Polymers 0.000 claims description 3
- VXNZUUAINFGPBY-UHFFFAOYSA-N 1-Butene Chemical compound CCC=C VXNZUUAINFGPBY-UHFFFAOYSA-N 0.000 claims 1
- 125000005605 benzo group Chemical group 0.000 claims 1
- IAQRGUVFOMOMEM-UHFFFAOYSA-N butene Natural products CC=CC IAQRGUVFOMOMEM-UHFFFAOYSA-N 0.000 claims 1
- 230000006698 induction Effects 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 230000003071 parasitic effect Effects 0.000 description 8
- 238000002955 isolation Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- SMWDFEZZVXVKRB-UHFFFAOYSA-N Quinoline Chemical compound N1=CC=CC2=CC=CC=C21 SMWDFEZZVXVKRB-UHFFFAOYSA-N 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A kind of semiconductor chip structure and its manufacturing method with end ring, the semiconductor chip structure with end ring include：Semiconductor base; the first surface of the semiconductor base has main core section and the end ring around main core section; the main core section and terminal ring surface have polymer protective layer; the main core section includes well region in semiconductor substrate, positioned at well region and the interlayer metal layer of semiconductor substrate surface and the stacked structure of dielectric layer; the end ring is to perform etching the groove to be formed to stacked structure, semiconductor substrate; the depth of the groove is more than the overall thickness of stacked structure and well region, and the groove exposes the well region side wall of the main core section.Since groove eliminates most of well region material, the surface induction electric field of master chip area edge is greatly reduced, the width that master chip area edge is not easy breakdown, of the invention end ring can be reduced into original 1/3 or more, greatly reduce the area of end ring.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor chip structures and its system with end ring
Make method.
Background technology
At present in the manufacturing process of high-voltage chip, the discrete device of high pressure can stay the end of one fixed width around master chip
Protection ring (also referred to as buffering ring) is held, for pressure resistance and reduces induction field.Design for the discrete device of middle low-voltage, terminal
Area shared by protection ring will not be very big, and parasitic device, the reliability of influence master chip that can't be too many.High pressure point
It is usually overleaf drawn from device high pressure port, and certain induction field can be generated on surface, it is strong in order to reduce surface field
Degree, it is desirable that resistance to pressure request of the very wide terminal suspending region to meet direct current with exchange.Its buffering area of the high tension apparatus of 500V
It is usually more than 120um, the ratio that cushion area accounts for whole chip area is usually very high.
The isolation of terminal protection ring, traditional handicraft is using field oxide isolation, injection isolation and Metal field plate or polycrystalline
Silicon field plate is isolated, and purpose is exactly for pressure resistance and to lower influence of the induction field to device effective coverage, but can all introduce
Parasitic components, such as introduce parasitic capacitance and influence the AC characteristic of device.
Invention content
Problems solved by the invention is to provide a kind of semiconductor chip structure and its manufacturing method with end ring, can be
The area of end ring is reduced under the premise of guarantee pressure resistance, and parasitic capacitance is smaller.
To solve the above problems, the present invention provides a kind of semiconductor chip structure with end ring, feature exists
In, including：Semiconductor base, the semiconductor base include first surface and opposite second surface, the semiconductor base
First surface there is main core section and the end ring around main core section, the main core section and terminal ring surface to have polymerization
Object protective layer, the main core section include well region in semiconductor substrate, positioned at the interlayer of well region and semiconductor substrate surface gold
Belong to the stacked structure of layer and dielectric layer, the end ring is to perform etching the groove to be formed, institute to stacked structure, semiconductor substrate
The depth for stating groove is more than the overall thickness of stacked structure and well region, and the groove exposes the well region side of the main core section
Wall.
Optionally, the main core section is discrete device or chip.
Optionally, the polymer protective layer forms complete air insulated formula groove above groove in groove.
Optionally, the dielectric constant of the material of the polymer protective layer is less than or equal to 3.
Optionally, the material of the polymer protective layer is polyamide, polyimides, polytetrafluoroethylene (PTFE), polyaryl ether, gathers
Aryl ether ketones, benzoxazine polymer, benzocyclobutane olefine resin, SiLK, poly quinoline are one such.
Optionally, the second surface of the semiconductor base has interconnection metal layer again.
Optionally, the dicing lane of chip is located in the groove.
The embodiment of the present invention additionally provides a kind of manufacturing method of the semiconductor chip structure with end ring, including：
Semiconductor base is provided, the semiconductor base includes semiconductor substrate, the well region in semiconductor substrate, position
In well region and the interlayer metal layer of semiconductor substrate surface and the stacked structure of dielectric layer, the corresponding position of the well region is main core
Section；
Stacked structure around semiconductor base main core section is performed etching, half until exposing stacked structure bottom
Conductor substrate forms groove, and the depth of the groove is more than the overall thickness of stacked structure and well region, and the groove exposes institute
State the well region side wall of main core section, end ring of the groove as main core section；
Polymer protective layer is formed in the stacked structure and terminal ring surface.
Optionally, the technique for forming the groove is the combination of dry etch process, wet-etching technology or both.
Optionally, further include forming interconnection metal layer again in the second surface of the semiconductor base.
Optionally, the dicing lane of chip is located in the groove.
Optionally, after forming the groove, before forming polymer protective layer, place is passivated in the trench interiors
Reason.
Compared with prior art, the technical program has the following advantages：
Since the present invention is after due to completing the making of silicon chip postchannel process, etching forms groove around main core section,
It is follow-up not have further process filling dielectric layer or interlayer metal layer, i.e., using air as main core section and neighboring area
Isolation.Since groove eliminates most of well region material, the surface induction electric field of master chip area edge, main core section is greatly reduced
Edge is not easy breakdown, and the width of end ring can be reduced into original 1/3 or more, greatly reduce the area of end ring.
Description of the drawings
Fig. 1~Fig. 5 is the section knot of the manufacturing process of the semiconductor chip structure with end ring of the embodiment of the present invention
Structure schematic diagram.
Specific implementation mode
Below in conjunction with the accompanying drawings, by specific embodiment, clear, complete description is carried out to technical scheme of the present invention.
Referring to FIG. 5, the cross-section structure for the semiconductor chip structure with end ring of first embodiment of the invention shows
It is intended to, including：Semiconductor base 10, the semiconductor base 10 includes first surface 11 and opposite second surface 12, described
The first surface 11 of semiconductor base 10 has main core section 13 and the end ring 14 around main core section I, the main core section
13 and 14 surface of end ring there is polymer protective layer 21, the second surface of the semiconductor base 10 to have interconnection metal layer again
22。
The semiconductor base 10 includes semiconductor substrate 15 and the stacked structure 16 positioned at 15 surface of semiconductor substrate,
In in main core section 13, well region 17 is formed in the semiconductor substrate 15, the surface of the well region 17 have stack tie
Structure 16, the stacked structure 16 are that the stacked structure of dielectric layer 18 and interlayer metal layer 19 illustrates only one layer in this Fig. 5
Dielectric layer 18 and from level to level between metal layer 19.In other embodiments, the stacked structure can also include multilayer dielectricity layer and
Multilayer interlayer metal layer intersects the multilayer lamination structure stacked, is connected by conductive plunger between multilayer interlayer metal layer.
The semiconductor substrate is that silicon substrate, germanium substrate, gallium nitride substrate etc. are one such, and the dielectric layer is oxidation
Silicon layer or low-K dielectric material layer, the main core section 13 are the discrete device or chip of high pressure or low pressure, for example, power device or
High-voltage driving circuit chip etc..
In the present embodiment, the foreign ion doping type of the well region 17 and the foreign ion of semiconductor substrate adulterate class
For type on the contrary, when well region is P type trap zone, the semiconductor substrate is N-type substrate, when well region is N-type well region, the semiconductor
Substrate is P type substrate.
The end ring 14 is to perform etching the groove 20 to be formed, the groove to stacked structure 16, semiconductor substrate 15
20 depth is more than the overall thickness of stacked structure 16 and well region 17, and the groove 20 exposes the well region of the main core section 13
17 side walls.Since the side wall of the groove 20 exposes well region side wall and semiconductor substrate positioned at well region bottom, the terminal
Ring 14 remains able to provide enough pressure voltages.Etching groove depth and width are wanted according to different process and circuit voltage
Ask, the pressure resistance of product adjusts, depth can be or deeper from 1~50um.Width is according to groove both sides (close to chip-side
With by proximal edge side) pressure drop difference make the appropriate adjustments.
The groove 20 is performed etching and to be formed to stacked structure 16, semiconductor substrate 15 after forming stacked structure 16.
After completing the making of silicon chip postchannel process, groove is directly formed around main core section, does not have further technique subsequently
Filled media layer or interlayer metal layer are isolated with neighboring area using air as main core section.Due to air with respect to silicon and
The lower relative dielectric constant of silica, it is not easy to which breakdown, the width of end ring can be reduced into original 1/3 or more, greatly
The big area for reducing end ring.
If the technique that etching forms groove is placed on front-end process, since empty groove is there is a possibility that silicon chip is being related to high temperature
Generate warpage in the front-end process of process, influence the processing of silicon chip and the reliability of chip, and subsequent technique also can be in ditch
Filling metal, silica etc., lower the effect of trench termination significantly inside slot.The terminal trenches of this technique road work in the completed
It is formed after skill, on former technique for processing silicon chip without influence, one of mask and etching technics need to be only added after the completion of silicon wafer to manufacture.
In the present embodiment, also there is polymer protective layer 21 on the main core section 13 and 14 surface of end ring, it is described
Polymer protective layer 21 is passivated protection to the first surface of semiconductor base 10, since the width of the groove 20 becomes smaller,
Can across on the groove 20 by depositing the polymer protective layer 21 formed so that the groove formed complete air every
From formula groove.If main core section is high tension apparatus, the width of groove can be wider, and polymer can be partially filled with into groove, meeting
The pressure resistance of groove can further be improved.
In the present embodiment, the dielectric constant of the material of the polymer protective layer 21 is less than or equal to 3, is low-K dielectric material
Material, such as polyamide, polyimides, polytetrafluoroethylene (PTFE), polyaryl ether, polyaryletherketone, benzoxazine polymer, benzocyclobutane
Olefine resin, SiLK, poly quinoline etc. are one such.Since the dielectric constant of air is close to 1, the air insulated formula groove is utilized
It is smaller as parasitic capacitance caused by isolation structure, do not interfere with AC characteristic.Even if polymer can be partially filled with into groove,
Since the dielectric constant of the polymer is relatively low, compared with prior art, parasitic capacitance can be also reduced.
In the present embodiment, the second surface of the semiconductor base 10 is also formed with interconnection metal layer 22 again, it is described again
Voltage leading-out ends of the interconnection metal layer 22 as the semiconductor substrate of main core section.
In other embodiments, the voltage leading-out ends of the main core section may be located on the first surface of semiconductor base
On.
In other embodiments, referring to FIG. 4, the dicing lane 30 of chip is located in the groove 20.Although chip is drawn
When film channel 30 is located in the groove 20, the width of groove can become larger, but subsequently to chip carry out scribing cutting after, utilize resin
It wraps the side wall of chip, i.e., wraps the side wall of well region, stacked structure that groove exposes using resin, core can be completely eliminated
Influence of the electric field of piece edge to chip interior.
The embodiment of the present invention additionally provides a kind of manufacturing method of the semiconductor chip structure with end ring, including：
Step S101, provides semiconductor base, and the semiconductor base includes semiconductor substrate, is located in semiconductor substrate
Well region, positioned at well region and the interlayer metal layer of semiconductor substrate surface and the stacked structure of dielectric layer, the well region is corresponding
Position is main chip region；
Step S102 forms interconnection metal layer again in the second surface of the semiconductor base；
Step S103 performs etching the stacked structure around semiconductor base main core section, and knot is stacked until exposing
The semiconductor substrate of structure bottom, forms groove, and the depth of the groove is more than the overall thickness of stacked structure and well region, and the ditch
Slot exposes the well region side wall of the main core section, end ring of the groove as main core section；
Step S104 forms polymer protective layer in the stacked structure and terminal ring surface.
Specifically, referring to FIG. 1, providing semiconductor base 10, the semiconductor base 10 includes semiconductor substrate 15, position
In in semiconductor substrate well region 17, positioned at the interlayer metal layer 19 and dielectric layer 18 on well region 17 and semiconductor substrate 15 surface
Stacked structure 16,17 corresponding position of the well region are main chip region 13.The Doped ions class of the well region and semiconductor substrate
Type is opposite.Due to the discrete device or chip that the main core section 13 is high pressure or low pressure, those skilled in the art can basis
It needs that suitable technique is selected to be formed, it is not described here in detail.
Referring to FIG. 2, the second surface 12 in the semiconductor base 10 forms interconnection metal layer 22 again, it is described to connect up again
Voltage leading-out ends of the metal layer 22 as the semiconductor substrate of main core section.In other embodiments, the electricity of the main core section
Pressure exit may be located on the first surface of semiconductor base, need not be formed in the second surface of the semiconductor base
Interconnection metal layer again.
Referring to FIG. 3, being performed etching to the stacked structure 16 around 10 main core section 13 of semiconductor base, until exposing
The semiconductor substrate 15 of 16 bottom of stacked structure, forms groove 20, and the depth of the groove 20 is more than stacked structure 16 and well region
17 overall thickness, and the groove 20 exposes 17 side wall of well region of the main core section 13, the groove 20 is as around master
The end ring 14 of chip region 13.
In the present embodiment, the etching technics is the combination of dry etch process, wet-etching technology or both.
In the present embodiment, by first carrying out wet-etching technology, then dry etch process is carried out, since the depth of the groove is very big,
Width is also larger, on the one hand can save etch period and etching cost, on the other hand can also realize satisfied sidewall profile.
In other embodiments, after completing etching technics, processing can also be passivated to the groove, ditch can be reduced
The defects count of groove sidewall and bottom.
In other embodiments, referring to FIG. 4, the dicing lane 30 of chip is located in the groove 20.Although chip is drawn
When film channel 30 is located in the groove 20, the width of groove can become larger, but subsequently to chip carry out scribing cutting after, utilize resin
It wraps the side wall of chip, i.e., wraps the side wall of well region, stacked structure that groove exposes using resin, core can be completely eliminated
Influence of the electric field of piece edge to chip interior.
Referring to FIG. 5, forming polymer protective layer in the stacked structure 16 and 14 surface of end ring.
The dielectric constant of the material of the polymer protective layer 21 be less than or equal to 3, be low-K dielectric material, such as polyamide,
Polyimides, polyaryl ether, polyaryletherketone, benzoxazine polymer, benzocyclobutane olefine resin, SiLK, gathers polytetrafluoroethylene (PTFE)
Quinoline etc. is one such.Since the dielectric constant of air is close to 1, using the air insulated formula groove as isolation structure institute
The parasitic capacitance of generation is smaller, does not interfere with AC characteristic.Even if polymer can be partially filled with into groove, due to the polymer
Dielectric constant it is relatively low, compared with prior art, can also reduce parasitic capacitance.
Although the invention has been described by way of example and in terms of the preferred embodiments, but it is not for limiting the present invention, any this field
Technical staff without departing from the spirit and scope of the present invention, may be by the methods and technical content of the disclosure above to this hair
Bright technical solution makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, and according to the present invention
Technical spirit to any simple modifications, equivalents, and modifications made by above example, belong to technical solution of the present invention
Protection domain.
Claims (11)
1. a kind of semiconductor chip structure with end ring, which is characterized in that including：Semiconductor base, it is described semiconductor-based
Bottom includes first surface and opposite second surface, and the first surface of the semiconductor base has main core section and surrounds main core
The end ring of section, the main core section include well region in semiconductor substrate, positioned at the layer of well region and semiconductor substrate surface
Between metal layer and dielectric layer stacked structure, the end ring be the ditch to be formed is performed etching to stacked structure, semiconductor substrate
Slot, the depth of the groove is more than the overall thickness of stacked structure and well region, and the groove exposes the trap of the main core section
Area's side wall；The groove is to perform etching to be formed to stacked structure, semiconductor substrate after forming stacked structure, the main core
Section and terminal ring surface have polymer protective layer, and the polymer protective layer forms complete above groove, in groove
Air insulated formula groove, the well region side wall is exposed in the air of air insulated formula groove.
2. the semiconductor chip structure with end ring as described in claim 1, which is characterized in that the main core section is point
Vertical device or chip.
3. the semiconductor chip structure with end ring as claimed in claim 2, which is characterized in that the polymer protective layer
Material dielectric constant be less than or equal to 3.
4. the semiconductor chip structure with end ring as described in claim 1, which is characterized in that the polymer protective layer
Material be polyamide, polyimides, polytetrafluoroethylene (PTFE), polyaryl ether, polyaryletherketone, benzoxazine polymer, benzo ring
Butene resins, SiLK, poly quinoline are one such.
5. the semiconductor chip structure with end ring as described in claim 1, which is characterized in that the semiconductor base
Second surface has interconnection metal layer again.
6. the semiconductor chip structure with end ring as described in claim 1, which is characterized in that the dicing lane of chip is located at
In the groove.
7. a kind of manufacturing method of the semiconductor chip structure with end ring, which is characterized in that including：It provides semiconductor-based
Bottom, the semiconductor base include semiconductor substrate, the well region in semiconductor substrate, are located at well region and semiconductor substrate table
The interlayer metal layer in face and the stacked structure of dielectric layer, the corresponding position of the well region are main chip region；
Stacked structure around semiconductor base main core section is performed etching, the semiconductor until exposing stacked structure bottom
Substrate forms groove, and the depth of the groove is more than the overall thickness of stacked structure and well region, and the groove exposes the master
The well region side wall of chip region, end ring of the groove as main core section；
Polymer protective layer is formed in the stacked structure and terminal ring surface, complete air insulated formula ditch is formed in groove
Slot, the well region side wall are exposed in the air of air insulated formula groove.
8. the manufacturing method of the semiconductor chip structure with end ring as claimed in claim 7, which is characterized in that form institute
The technique for stating groove is the combination of dry etch process, wet-etching technology or both.
9. the manufacturing method of the semiconductor chip structure with end ring as claimed in claim 7, which is characterized in that also wrap
It includes, interconnection metal layer again is formed on another surface of the semiconductor base.
10. the manufacturing method of the semiconductor chip structure with end ring as claimed in claim 7, which is characterized in that chip
Dicing lane be located in the groove.
11. the manufacturing method of the semiconductor chip structure with end ring as claimed in claim 7, which is characterized in that formed
After the groove, before forming polymer protective layer, processing is passivated in the trench interiors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410545270.0A CN104362172B (en) | 2014-10-15 | 2014-10-15 | Semiconductor chip structure with end ring and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410545270.0A CN104362172B (en) | 2014-10-15 | 2014-10-15 | Semiconductor chip structure with end ring and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104362172A CN104362172A (en) | 2015-02-18 |
| CN104362172B true CN104362172B (en) | 2018-09-11 |
Family
ID=52529416
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410545270.0A Active CN104362172B (en) | 2014-10-15 | 2014-10-15 | Semiconductor chip structure with end ring and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104362172B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110690202A (en) * | 2019-10-09 | 2020-01-14 | 长江存储科技有限责任公司 | Integrated circuit device and method of making the same |
| CN112201685B (en) * | 2020-09-08 | 2022-02-11 | 浙江大学 | Super junction device and dielectric combined terminal |
| CN113437136A (en) * | 2021-06-28 | 2021-09-24 | 深圳市时代速信科技有限公司 | Semiconductor device and preparation method thereof |
| CN114005733B (en) * | 2021-10-19 | 2022-08-09 | 深圳辰达行电子有限公司 | Method for manufacturing vehicle-gauge-level rectification chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6184121B1 (en) * | 1997-07-10 | 2001-02-06 | International Business Machines Corporation | Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same |
| CN1501492A (en) * | 2002-11-15 | 2004-06-02 | 联华电子股份有限公司 | Integrated circuit structure with air gap and manufacturing method thereof |
| CN102157431A (en) * | 2010-01-20 | 2011-08-17 | 瑞萨电子株式会社 | Semiconductor device and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6432646A (en) * | 1987-07-29 | 1989-02-02 | Hitachi Ltd | Element isolation structure and manufacture thereof |
| KR20120003169A (en) * | 2010-07-02 | 2012-01-10 | 삼성전자주식회사 | High selectivity etchant and method of fabricating semiconductor device using the same |
-
2014
- 2014-10-15 CN CN201410545270.0A patent/CN104362172B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6184121B1 (en) * | 1997-07-10 | 2001-02-06 | International Business Machines Corporation | Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same |
| CN1501492A (en) * | 2002-11-15 | 2004-06-02 | 联华电子股份有限公司 | Integrated circuit structure with air gap and manufacturing method thereof |
| CN102157431A (en) * | 2010-01-20 | 2011-08-17 | 瑞萨电子株式会社 | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104362172A (en) | 2015-02-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11532726B2 (en) | VDMOS device and manufacturing method therefor | |
| US10103253B2 (en) | Structure and method for vertical tunneling field effect transistor with leveled source and drain | |
| US20130069150A1 (en) | Semiconductor device and manufacturing method of the same | |
| CN104362172B (en) | Semiconductor chip structure with end ring and its manufacturing method | |
| CN107424962A (en) | Protection insulator for HFET devices | |
| US9048128B2 (en) | Inductor structure with magnetic material | |
| US20140252442A1 (en) | Method and Structure for Vertical Tunneling Field Effect Transistor and Planar Devices | |
| US10854743B2 (en) | VDMOS device and manufacturing method therefor | |
| US10867994B2 (en) | High density capacitors formed from thin vertical semiconductor structures such as FINFETs | |
| US10164006B1 (en) | LDMOS FinFET structures with trench isolation in the drain extension | |
| US20140203365A1 (en) | Semiconductor device | |
| CN107045980B (en) | The forming method of transistor | |
| TWI599041B (en) | Metal oxide semiconductor field effect transistor power device with bottom gate and method for the same | |
| CN103151310B (en) | Deeply-grooved power MOS (Metal Oxide Semiconductor) device and production method thereof | |
| CN105448984A (en) | FinFET and preparation method thereof | |
| CN103021867B (en) | The forming method of trench metal-oxide-semicondbarrier barrier Schottky | |
| US9490315B2 (en) | Power semiconductor device and method of fabricating the same and cutoff ring | |
| US8785997B2 (en) | Semiconductor device including a silicate glass structure and method of manufacturing a semiconductor device | |
| US20150137230A1 (en) | Laterally diffused metal oxide semiconductor and manufacturing method thereof | |
| CN105789280A (en) | High-voltage semiconductor device and manufacturing method thereof | |
| CN105529362B (en) | High voltage semiconductor device and its manufacturing method | |
| US8586432B2 (en) | Method for manufacturing vertical-channel tunneling transistor | |
| CN108305830A (en) | Semiconductor structure and forming method thereof | |
| CN112993014A (en) | Silicon carbide planar power semiconductor device and manufacturing method thereof | |
| CN105895667B (en) | A kind of semiconductor devices and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province, 310030 Patentee after: Jiehuate Microelectronics Co.,Ltd. Address before: Room 424, building 1, 1500 Wenyi West Road, Cangqian street, Yuhang District, Hangzhou City, Zhejiang Province Patentee before: JOULWATT TECHNOLOGY (HANGZHOU) Co.,Ltd. |