CN1750265A - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
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- CN1750265A CN1750265A CNA2005101029192A CN200510102919A CN1750265A CN 1750265 A CN1750265 A CN 1750265A CN A2005101029192 A CNA2005101029192 A CN A2005101029192A CN 200510102919 A CN200510102919 A CN 200510102919A CN 1750265 A CN1750265 A CN 1750265A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 238000000034 method Methods 0.000 title claims description 42
- 239000003990 capacitor Substances 0.000 claims abstract description 157
- 239000002184 metal Substances 0.000 claims abstract description 60
- 229910052751 metal Inorganic materials 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000000203 mixture Substances 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims 1
- 239000012528 membrane Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 226
- 101150054675 MIM1 gene Proteins 0.000 description 19
- 101150096414 MIM2 gene Proteins 0.000 description 15
- 230000015572 biosynthetic process Effects 0.000 description 14
- 238000001259 photo etching Methods 0.000 description 10
- 239000010949 copper Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 238000004380 ashing Methods 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N hydrogen peroxide Substances OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A semiconductor device has a MIM capacitor including a first insulating film formed on a semiconductor substrate, a lower electrode composed of a first metal film formed on the first insulating film, a capacitor insulating film formed on the lower electrode, and an upper electrode composed of a second metal film formed on the capacitor insulating film. The semiconductor device further has a lower interconnect composed of the first metal film formed on the first insulating film and an upper interconnect composed of the second metal film formed on the lower interconnect. The upper interconnect and the upper electrode are formed integrally.
Description
The cross reference of related application
Here by with reference to the instruction of intactly introducing the Japanese patent application JP 2004-266402 that was submitted on September 14th, 2004, comprise specification, accompanying drawing and claims.
Technical field
The present invention relates to the semiconductor device and the manufacture method thereof of a kind of MIM of comprising (metal-insulator-metal type) capacitor.
Background technology
In recent years, research concentrate on the single-chip of analogue device and CMOS logical device integrated on.Simultaneously, the CMOS logical device obtains miniaturization day by day year by year, so, in order to reduce at grid length is interconnection resistance in 0.1 μ m or the littler MOS transistor, studied low resistivity material copper as interconnection material, inlayed (damascene) technology simultaneously also under study for action as a kind of method that is used to make interconnection.Along with the carrying out of miniaturization, transistorized integrated level trends towards more and more higher, and the sum of the interconnection in the CMOS logical device is tending towards increasing.These trend towards the miniaturization of semiconductor device and multilayer interconnection configuration have caused following problems, promptly how to form the capacitor of a high capacitance in analogue device and can not influence and realize higher device integrated level.
An example as wherein form high capacitance capacitors in analogue device has a kind of like this semiconductor device, and it comprises the MIM capacitor that forms by mosaic technology.MIM capacitor is made up of metal bottom electrode respect to one another and electrode of metal, and is inserted with capacitor insulating film between upper/lower electrode.Compare with the conventional capacitor that uses polysilicon to be used as cell panel, because it is thinner that thin film technique allows that bottom electrode, capacitor insulating film and top electrode are formed ground, can not influence so can form capacitor and realize higher integrated level (for example referring to patent document 1: Japanese publication is announced No.2002-217373) with high capacitance.
With reference to the accompanying drawings, below will provide the description of the conventional method that is used to make the semiconductor device that comprises MIM capacitor.
Fig. 7 A to Fig. 7 E is the cross-sectional view that the processing step of making the conventional semiconductor device that comprises MIM capacitor is described.Typically as shown in Figure 7A, MIM capacitor is formed the surf zone that regional MIM and interconnection formation region R logic are depicted as Semiconductor substrate.
At first, as shown in Figure 7A, first dielectric film 1 is formed on (not shown) on the Semiconductor substrate, and this Semiconductor substrate is formed with such as transistorized semiconductor element.Then, by CVD or sputter first metal film 2 is deposited on first dielectric film 1.
Then, as shown in Fig. 7 B, second dielectric film 3 is deposited on first metal film 2 by CVD.
Then, as shown in Fig. 7 C,, will form the resist mask 4 that has opening among the region R logic in interconnection and be formed on second dielectric film 3, form regional MIM to cover MIM capacitor by photoetching.Then, use resist mask 4 by dry etching, composition second dielectric film 3.Afterwards, remove resist mask 4 by the ashing (ashing) of using oxidation plasma.
Then, as shown in Fig. 7 D, by CVD or sputtering deposit second metal film 5, to cover the whole surface of Semiconductor substrate.
Then, as shown in Fig. 7 E, by photoetching and dry etching composition second metal film 5, second dielectric film 3 and first metal film 2, forming the MIM capacitor of forming by top electrode 5a, capacitor insulating film 3a and bottom electrode 2a 6, and the interconnection of forming by the last interconnection 5b and the 2b that interconnects down 7.
Summary of the invention
Yet the conventional method that is used to make the semiconductor device that comprises MIM capacitor has run into following point.
As shown in Fig. 7 C, in the conventional method that is used for making the semiconductor device that comprises MIM capacitor, cover second dielectric film 3, so that second dielectric film 3 as the capacitor insulating film 3a of MIM capacitor is carried out composition with resist mask 4.Thereby in the ashing behind composition, because 4 evaporations of resist mask, upper surface and the side surface of capacitor insulating film 3a are exposed to oxygen plasma.Because capacitor insulating film is here by for example silicon dioxide film (SiO
2) form, so when being exposed to oxygen plasma, at the upper surface of capacitor insulating film and the SiO in the side surface
2The covalent bond fracture, thus the physics corrosion takes place.This causes the upper surface of capacitor insulating film and side surface coarse, its surface smoothness is descended, and reduced its puncture voltage, makes disadvantageous dielectric breakdown takes place.In the upper surface and side surface of capacitor insulating film, by being exposed under the situation that oxygen plasma caused dangling bonds, electronics is in unsettled chemi-excitation attitude, thereby the upper surface of capacitor insulating film and side surface are subjected to the pollution of impurity etc.This has caused the faulty operation of MIM capacitor, the reduction of output and the decline of device reliability.
In addition, in comprising the conventional semiconductor device of MIM capacitor, MIM capacitor and other elements electricity are independent, and are not formed for drawing the interconnection of top electrode.As a result, the other contact hole or the interconnection layer that are used to draw top electrode become necessary, and this has influenced the miniaturization of the semiconductor device with MIM capacitor.In addition, in order to be formed for drawing the other contact hole or the interconnection layer of top electrode, the number of steps in the production process of semiconductor device increases unfriendly.
One object of the present invention is to provide a kind of method that is used to make the semiconductor device with high reliability MIM capacitor.
Semiconductor device according to one aspect of the invention is the semiconductor device with MIM capacitor, and this MIM capacitor comprises: first dielectric film, and it is formed on the Semiconductor substrate; Bottom electrode is made up of first metal film that is formed on first dielectric film; Capacitor insulating film, it is formed on the bottom electrode; And top electrode, to form by second metal film that is formed on the capacitor insulating film, this semiconductor device comprises: interconnection down, form by first metal film that is formed on first dielectric film; With last interconnection, to form by second metal film that is formed on down in the interconnection, last interconnection and top electrode form as one.
According to the semiconductor device with MIM capacitor of one aspect of the invention, compare miniaturization further with the semiconductor device that interconnection layer is formed on the upper strata again with the contact hole that wherein will all be used for drawing the MIM capacitor top electrode.
Preferably, the semiconductor device according to one aspect of the invention also comprises: second dielectric film, and it is formed on first dielectric film and has bottom electrode groove and interconnection channel, and bottom electrode is imbedded in the bottom electrode groove and is interconnected down and imbeds in the interconnection channel.
In the semiconductor device according to one aspect of the invention, the upper surface and the side surface of bottom electrode are coated with capacitor insulating film.
Preferably, the semiconductor device according to one aspect of the invention also comprises: the 3rd dielectric film, and it is formed on bottom electrode and the top that interconnects down, to be used as capacitor insulating film; With the 4th dielectric film, it is formed on the 3rd dielectric film, wherein be formed with opening in the 4th dielectric film part that is arranged in above the bottom electrode, be arranged in the 3rd dielectric film above the bottom electrode and the appropriate section of the 4th dielectric film, be formed with the contact hole that runs through the 3rd dielectric film and the 4th dielectric film, on the part of the capacitor insulating film of forming by the 3rd dielectric film that is exposed in the opening, be formed with top electrode, and in the contact hole that is connected to interconnection down, be formed with interconnection.
In the semiconductor device according to one aspect of the invention, preferably, opening and contact hole are separated from each other by the 4th dielectric film, and preferably, top electrode and on be interconnected in the 4th dielectric film top and be connected to each other.
Be used to make method, may further comprise the steps: (a) on Semiconductor substrate, form first dielectric film according to the semiconductor device of one aspect of the invention; (b) on first dielectric film, form bottom electrode and the interconnection of forming by first metal film down; (c) on bottom electrode, form capacitor insulating film; And (d) on capacitor insulating film, form the top electrode of forming by second metal film, and in interconnection down, form form by second metal film on interconnect, last interconnection and top electrode form as one.
According to the method that is used to make according to the semiconductor device of one aspect of the invention, the upper surface and the side surface of the capacitor insulating film of protection MIM capacitor are not exposed to oxygen plasma, thereby keep the evenness of the capacitor insulating film of MI M capacitor.This feasible dielectric breakdown that reduction produced that can prevent by puncture voltage.
Preferably, be used to make according to the method for the semiconductor device of one aspect of the invention step (a) afterwards and step (b) before, further comprising the steps of: as on first dielectric film, to form second dielectric film, and form bottom electrode groove and interconnection channel then in second dielectric film, step (b) is to be used for forming in the bottom electrode groove bottom electrode and interconnection under the formation in interconnection channel.
In the method that is used for making according to the semiconductor device of one aspect of the invention, step (b) is preferably to be used for forming on first dielectric film first metal film, and composition first metal film is to form bottom electrode and interconnection down then, step (c) is preferably to be used for forming capacitor insulating film, thereby covers the upper surface and the side surface of bottom electrode with it.
In the method that is used for making according to the semiconductor device of one aspect of the invention, step (c) is preferably to be used at bottom electrode and to form down the 3rd dielectric film as capacitor insulating film above the interconnection, this method step (c) afterwards and step (d) also preferably include following steps before: (e) on the 3rd dielectric film, form the 4th dielectric film; (f) for the part of the 4th dielectric film that is positioned at the bottom electrode top, carry out dry etching, reach the degree of depth place of not exposing the 3rd dielectric film, in the 4th dielectric film, to form opening; (g) afterwards, form contact hole, this contact hole runs through and is positioned at the 3rd dielectric film of interconnection top and the appropriate section of the 4th dielectric film down in step (f); And (h) afterwards in step (g), remove the part of staying the 4th dielectric film in the opening by wet etching, step (d) is preferably to be used on Semiconductor substrate forming second metal film, and then composition second metal film so that top electrode and last interconnection form as one.
Thereby; in semiconductor device and manufacture method thereof according to one aspect of the invention; the upper surface of capacitor for voltage protection dielectric film and side surface are not exposed to oxygen plasma, thereby keep the evenness of capacitor insulating film reliably, and prevent the reduction of its puncture voltage.In addition, can prevent by being exposed to the pollution that oxygen plasma produces capacitor insulating film.In addition, semiconductor device miniaturization can be made, and the number of manufacturing technology steps can be reduced with MIM capacitor.
Description of drawings
Fig. 1 is the cross-sectional view of expression according to the major part of the semiconductor device structure of first embodiment of the invention;
Fig. 2 A to Fig. 2 E is explanation at the cross-sectional view that is used for making according to the major part of the processing step of the method for the semiconductor device of first embodiment;
Fig. 3 A to Fig. 3 C is explanation at the cross-sectional view that is used for making according to the major part of the processing step of the method for the semiconductor device of first embodiment;
Fig. 4 is the major part cross-sectional view of expression according to the semiconductor device structure of second embodiment of the invention;
Fig. 5 A to Fig. 5 E is explanation at the cross-sectional view that is used for making according to the major part of the processing step of the method for the semiconductor device of second embodiment;
Fig. 6 A to Fig. 6 C is explanation at the cross-sectional view that is used for making according to the major part of the processing step of the method for the semiconductor device of second embodiment; With
Fig. 7 A to Fig. 7 E is the cross-sectional view of explanation in the major part of the processing step of the conventional method that is used for making the semiconductor device with MIM capacitor.
Embodiment
Fig. 1 is the cross-sectional view of expression according to the semiconductor device that comprises MIM capacitor of first embodiment of the invention.As shown in fig. 1, MIM capacitor is formed regional MIM1, MIM capacitor and draw that interconnection forms regional MIM2 and interconnection forms the surf zone that region R logic is depicted as Semiconductor substrate.
MIM capacitor forms regional MIM1 to be had: first dielectric film 101, and it is formed on the Semiconductor substrate (not shown); Second dielectric film 102, it is formed on first dielectric film 101; Bottom electrode 104a is made up of first metal film of imbedding in the bottom electrode groove that is provided in second dielectric film 102 104; Capacitor insulating film 105a, it is made up of the 3rd dielectric film 105 that is formed on second dielectric film 102 that comprises bottom electrode 104a; The 4th dielectric film 106, it is formed on the 3rd dielectric film 105; With top electrode 111a, it is made up of second metal film 111 on the part of capacitor insulating film 105a, and this top electrode 111a is arranged in an opening, and this opening is provided at the 4th dielectric film 106 that is arranged in bottom electrode 104a top.Top electrode 111a, capacitor insulating film 105a and bottom electrode 104a constitute MIM capacitor 113.
MIM capacitor is drawn the regional MIM2 of interconnection formation and is had: first dielectric film 101, and it is formed on (not shown) on the Semiconductor substrate; Second dielectric film 102, it is formed on first dielectric film 101; Bottom electrode 104b is made up of the part of imbedding first metal film 104 in the following interconnection channel that is provided in second dielectric film 102; The 3rd dielectric film 105, it is formed on second dielectric film 102 that comprises the 104b that interconnects down; The 4th dielectric film 106, it is formed on the 3rd dielectric film 105; With last interconnection 111b, to form by the part of second metal film 111, interconnection 111b is embedded in the contact hole on this, and this contact hole is provided at and is arranged in the 4th dielectric film 106 and the 3rd dielectric film 105 of interconnection 104b top down.The last interconnection 111b and the 104b that interconnects down constitute MIM capacitor and draw interconnection 114.Last interconnection 111b forms as one with the top electrode 111a of MIM capacitor 113 and is electrically connected with it.
Interconnection forms region R logic to have: first dielectric film 101, and it is formed on (not shown) on the Semiconductor substrate; Second dielectric film 102, it is formed on first dielectric film 101; Interconnection 104c is made up of the part of imbedding first metal film 104 in the interconnection channel that is provided in second dielectric film 102; The 3rd dielectric film 105, it is formed on second dielectric film 102 and interconnection 104c top; With the 4th dielectric film 106, it is formed on the 3rd dielectric film 105.
First embodiment is characterised in that, on the 111b that interconnects form as one with the top electrode 111a of MIM capacitor 113, and top electrode 111a draws via the following interconnection 104b that is electrically connected with it.This compares with the situation that interconnection layer is formed on the upper strata again with the contact hole that will all be used for drawing the MIM capacitor top electrode, allows the semiconductor device miniaturization further to having MIM capacitor.
-be used to make the method for the semiconductor device of embodiment 1-
Below use description to make method according to the semiconductor device of first embodiment of the invention.Fig. 2 A to Fig. 2 E and Fig. 3 A to Fig. 3 E are the cross-sectional view of explanation manufacturing according to the processing step of the semiconductor device of first embodiment.Typically as shown in Fig. 2 A and Fig. 3 A, MIM capacitor is formed regional MIM1, MIM capacitor draw that interconnection forms regional MIM2 and interconnection forms the surf zone that region R logic is depicted as Semiconductor substrate.
At first, as shown in Fig. 2 A, first dielectric film 101 is formed on the Semiconductor substrate (not shown), is formed with such as transistorized semiconductor element on this Semiconductor substrate.Then, by CVD, second dielectric film 102 is deposited on first dielectric film 101, this second dielectric film 102 is that the fluorine-doped silica film (fsg film) of 300nm is formed by thickness for example.Subsequently, by photoetching and dry etching, MIM capacitor forms regional MIM1, MIM capacitor is drawn the appropriate section that interconnection forms second dielectric film 102 of regional MIM2 and interconnection formation region R logic, formation bottom electrode groove 103a, interconnection channel 103b and interconnection channel 103c being arranged in.
Then, as shown in Fig. 2 B, by CVD or sputter, deposition thickness is the first metal film (not shown) of 700nm for example, to be filled in bottom electrode groove 103a, interconnection channel 103b and the interconnection channel 103c that forms in second dielectric film 102.Thereafter, by CMP (chemico-mechanical polishing) method polish first metal film with the bottom electrode 104a that forms MIM capacitor, interconnect 104b and interconnection 104c down.For first metal film 104, can use for example aluminium (Al) or copper (Cu) here.
Then, as shown in Fig. 2 C, by CVD, comprising the bottom electrode 104a of MIM capacitor, interconnecting on second dielectric film 102 of 104b and interconnection 104c down, deposition thickness be that the 3rd dielectric film 105 of for example 50nm and thickness are the 4th dielectric film 106 of 200nm for example in succession.As the 3rd dielectric film 105, can use for example silicon nitride (SiN) film here.As the 4th dielectric film 106, can use silicon dioxide film (SiO here
2).
Then, as shown in Fig. 2 D,, be formed on the resist mask 107 that has opening above the bottom electrode 104a on the 4th dielectric film 106 by photoetching.Then, use resist mask 107, the 4th dielectric film 106 is etched into the degree of depth place of not exposing the 3rd dielectric film 105, thereby form opening 108 by dry etch process.For example, forming the degree of depth in the 4th dielectric film 106 is the opening 108 of 150nm, and the thickness of staying the 4th dielectric film 106a of opening 108 bottoms like this is 50nm.The purpose that the 4th dielectric film 106 is etched into the degree of depth place of not exposing the 3rd dielectric film 105 is, in wet etching step subsequently, the 3rd dielectric film 105 that MIM capacitor is formed among the regional MIM1 exposes, and prevents that drawing interconnection in MIM capacitor forms regional MIM2 and interconnection and form three dielectric film 105 of region R logic in separately and expose.
Then, as shown in Fig. 2 E, remove resist mask 107, and, under being formed on the 4th dielectric film 106, have the resist mask 109 of opening above the interconnection 104b then by photoetching.Then, use resist mask 109 etches into the position of exposing the 104b that interconnects down by dry etch process with the 4th dielectric film 106 and the 3rd dielectric film 105, draws among the regional MIM2 of interconnection formation in MIM capacitor like this and has formed contact hole 110.
Then, as shown in Fig. 3 A, remove resist mask 109, use for example ammoniacal liquor-hydrogen peroxide intermixture by wet-etching technology then, etching is stayed MIM capacitor and is formed the 4th dielectric film 106a in the opening 108 among the regional MIM1, has exposed the capacitor insulating film 105a that is made up of the 3rd dielectric film 105 like this in MIM capacitor forms opening 108 among the regional MIM1.
Then, as shown in Fig. 3 B, by CVD or sputter, deposition thickness is second metal film 111 of 900nm for example on the 4th dielectric film 106, with filling opening 108 and contact hole 110.For second metal film 111, can use aluminium (Al) or copper (Cu) here.
Then, as shown in Fig. 3 C, by photoetching, be formed on interconnection and form the resist mask 112 that has opening among the region R logic on second metal film 111, MIM capacitor forms regional MIM1 and MIM capacitor is drawn the regional MIM2 of interconnection formation to cover.Then, use resist mask 112 to pass through dry etch process, etching second metal film 111, so that MIM capacitor form among the regional MIM1 top electrode 111a and MIM capacitor draw interconnection form among the regional MIM2 on interconnection 111b form as one, formed the MIM capacitor of forming by top electrode 111a, capacitor insulating film 105a and bottom electrode 104a 113 thus, and formed by last interconnection 111b and down the MIM capacitor formed of interconnection 104b draw and interconnect 114.
Be used to make method according to the semiconductor device of first embodiment, permission forms the MIM capacitor of being made up of top electrode 111a, capacitor insulating film 105a and bottom electrode 104a 113 by carrying out wet etching and deposit second metal film 111 for staying the 4th dielectric film 106a that MIM capacitor forms in the opening 108 among the regional MIM1.This has prevented that photoresist is deposited on the capacitor insulating film 105a; and capacitor for voltage protection dielectric film 105a is not exposed to the oxygen plasma that is used for ashing, faulty operation, the reduction of output and the decline of device reliability of the dielectric breakdown that the evenness that has prevented from thus to be descended by capacitor insulating film produces and the caused MIM capacitor of pollution of capacitor insulating film.
Be used to make method, also allow to form simultaneously the top electrode 111a of MIM capacitor 113 and the 111b that interconnects that goes up that MIM capacitor is drawn interconnection 114 according to the semiconductor device of first embodiment.This has been avoided the needs of further formation contact hole and interconnection layer, and when MIM capacitor was independent of other elements formation, further forming contact hole and interconnection layer was essential for drawing MIM capacitor; And this method has also reduced the number that forms the step of the semiconductor device with MIM capacitor.
Fig. 4 is the cross-sectional view of expression according to the semiconductor device that comprises MIM capacitor of second embodiment of the invention.As shown in Figure 4, MIM capacitor is formed regional MIM1, MIM capacitor and draw that interconnection forms regional MIM2 and interconnection forms the surf zone that region R logic is depicted as the Semiconductor substrate (not shown).
MIM capacitor forms regional MIM1 to be had: first dielectric film 201, and it is formed on the Semiconductor substrate (not shown); Bottom electrode 202a, it is made up of first metal film 202 that is formed on first dielectric film 201; Capacitor insulating film 203a, it is made up of upper surface that forms covering bottom electrode 202a and second dielectric film 203 of side surface; The 3rd dielectric film 204, it is formed on second dielectric film 203; With top electrode 209a, it is made up of second metal film 209 that is formed on the capacitor insulating film 203a part, and this top electrode 209a is arranged in an opening, and this opening is provided at the 3rd dielectric film 204 that is arranged in bottom electrode 202a top.Top electrode 209a, capacitor insulating film 203a and bottom electrode 202a have constituted MIM capacitor 211.
MIM capacitor is drawn the regional MIM2 of interconnection formation and is had: first dielectric film 201, and it is formed on the Semiconductor substrate (not shown); Under the 202b that interconnects, form by first metal film 202 that is formed on first dielectric film 201; Second dielectric film 203, it forms and covers upper surface and the side surface of interconnection 202b down; The 3rd dielectric film 204, it is formed on second dielectric film 203; With last interconnection 209b, to form by the part of second metal film 209, interconnection 209b imbeds in the contact hole on this, and this contact hole is provided at and is arranged in the 3rd dielectric film 204 and second dielectric film 203 of interconnection 202b top down.The last interconnection 209b and the 202b that interconnects have down constituted MIM capacitor and have drawn interconnection 212.Last interconnection 209b forms as one with the top electrode 209a of MIM capacitor 211 and is electrically connected with it.
Interconnection forms region R logic to have: first dielectric film 201, and it is formed on the Semiconductor substrate (not shown); Interconnection 202c is made up of first metal film 202 that is formed on first dielectric film 201; Second dielectric film 203, it forms upper surface and the side surface that covers interconnection 202c; With the 3rd dielectric film 204, it is formed on second dielectric film 203.
Second embodiment is characterised in that, on the interconnect top electrode 209a of 209b and MIM capacitor 211 form as one, and top electrode 209a draws via the following interconnection 202b that is electrically connected with it.This compares with the situation that interconnection layer is formed on the upper strata again with the contact hole that will all be used for drawing the MIM capacitor top electrode, has allowed the semiconductor device miniaturization further to having MIM capacitor.
-be used to make the method for the semiconductor device of embodiment 2-
Below use description to make method according to the semiconductor device of second embodiment of the invention.Fig. 5 A to Fig. 5 E and Fig. 6 A to Fig. 6 E are the cross-sectional view of explanation manufacturing according to the processing step of the semiconductor device of second embodiment.As shown in Fig. 5 A and Fig. 5 B, MIM capacitor is formed regional MIM1, MIM capacitor draw that interconnection forms regional MIM2 and interconnection forms the surf zone that region R logic is depicted as the Semiconductor substrate (not shown).
At first, as shown in Fig. 5 A, first dielectric film 201 is formed on the Semiconductor substrate (not shown), and this Semiconductor substrate is formed with such as transistorized semiconductor element.Then, by CVD or sputter, be that first metal film 202 of 300nm is deposited on first dielectric film 201 with for example thickness.For first metal film 202, can use aluminium (Al) or copper (Cu) here.
Then, as shown in Fig. 5 B, by photoetching and dry etching, composition first metal film 202 with the bottom electrode 202a that forms MIM capacitor, interconnect 202b and interconnection 202c down.
Then, as shown in Fig. 5 C, by CVD in succession deposition thickness be that second dielectric film 203 of for example 50nm and thickness are for example the 3rd dielectric film 204 of 200nm, with the bottom electrode 202a that covers MIM capacitor, interconnect 202b and interconnection 202c down.As second dielectric film 203, can use for example silicon nitride (SiN) film here.As the 3rd dielectric film 204, can use silicon dioxide film (SiO here
2).
Then, as shown in Fig. 5 D,, be formed on the resist mask 205 that has opening above the bottom electrode 202a on the 3rd dielectric film 204 by photoetching.Then, use resist mask 205, the 3rd dielectric film 204 is etched into the degree of depth place of not exposing second dielectric film 203, thereby form opening 206 by dry etch process.For example, forming the degree of depth in the 3rd dielectric film 204 is the opening 206 of 150nm, and the thickness of staying the 3rd dielectric film 204a of opening 206 bottoms like this is 50nm.The purpose that the 3rd dielectric film 204 is etched into the degree of depth place of not exposing second dielectric film 203 is, in wet etching step subsequently, second dielectric film 203 that MIM capacitor is formed among the regional MIM1 exposes, and prevents that drawing interconnection in MIM capacitor forms regional MIM2 and interconnection and form second dielectric film 203 of region R logic in separately and expose.
Then, as shown in Fig. 5 E, remove resist mask 205, and, under being formed on the 3rd dielectric film 204, have the resist mask 207 of opening above the interconnection 202b then by photoetching.Then, use resist mask 207 all etches into the position of exposing the 202b that interconnects down by dry etch process with the 3rd dielectric film 204 and second dielectric film 203, draws among the regional MIM2 of interconnection formation in MIM capacitor like this and has formed contact hole 208.
Then, as shown in Fig. 6 A, remove resist mask 207, pass through wet-etching technology then, use ammoniacal liquor-hydrogen peroxide intermixture etching for example to stay MIM capacitor and form the 3rd dielectric film 204a in the opening 206 among the regional MIM1, in MIM capacitor forms opening 206 among the regional MIM1, exposed the capacitor insulating film 203a that forms by second dielectric film 203 like this.
Then, as shown in Fig. 6 B, by CVD or sputter, deposition thickness is second metal film 209 of 900nm for example on the 3rd dielectric film 204, with filling opening 206 and contact hole 208.For second metal film 209, can use aluminium (Al) or copper (Cu) here.
Then, as shown in Fig. 6 C, by photoetching, be formed on interconnection and form the resist mask 210 that has opening among the region R logic on second metal film 209, MIM capacitor forms regional MIM1 and MIM capacitor is drawn the regional MIM2 of interconnection formation to cover.Then, use resist mask 210 to pass through dry etch process, etching second metal film 209, so that MIM capacitor form among the regional MIM1 top electrode 209a and MIM capacitor draw interconnection form among the regional MIM2 on interconnection 209b form as one, formed the MIM capacitor of forming by top electrode 209a, capacitor insulating film 203a and bottom electrode 202a 211 thus, and formed by last interconnection 209b and down the MIM capacitor formed of interconnection 202b draw and interconnect 212.
Be used to make method according to the semiconductor device of second embodiment, permission forms the MIM capacitor of being made up of top electrode 209a, capacitor insulating film 203a and bottom electrode 202a 211 by carrying out wet etching and deposit second metal film 209 for staying the 3rd dielectric film 204a that MIM capacitor forms in the opening 206 among the regional MIM1.This has prevented that photoresist is deposited on the capacitor insulating film 203a; and capacitor for voltage protection dielectric film 203a is not exposed to the oxygen plasma that is used for ashing, faulty operation, the reduction of output and the decline of device reliability of the dielectric breakdown that the evenness that has prevented from thus to be descended by capacitor insulating film produces and the caused MIM capacitor of pollution of capacitor insulating film.
Be used to make method, also allow to form simultaneously the top electrode 209a of MIM capacitor 211 and the 209b that interconnects that goes up that MIM capacitor is drawn interconnection 212 according to the semiconductor device of second embodiment.This has been avoided the needs of further formation contact hole and interconnection layer, and when MIM capacitor was independent of other elements formation, further forming contact hole and interconnection layer was essential for drawing MIM capacitor; And this method has also reduced the number that forms the step of the semiconductor device with MIM capacitor.
According to the semiconductor device and the manufacture method thereof of one aspect of the invention, be useful for semiconductor device with MIM capacitor and manufacture method thereof.
Claims (9)
1. semiconductor device, has MIM capacitor, this capacitor comprises first dielectric film that is formed on the Semiconductor substrate, the bottom electrode of being made up of first metal film that is formed on described first dielectric film, the top electrode that is formed on the capacitor insulating film on the described bottom electrode and is made up of second metal film that is formed on the described capacitor insulating film, and described semiconductor device comprises:
Following interconnection is made up of described first metal film that is formed on described first dielectric film; With
Last interconnection is made up of described second metal film that is formed in the described interconnection down,
Described upward interconnection and described top electrode form as one.
2. semiconductor device according to claim 1 also comprises:
Second dielectric film is formed on described first dielectric film, and has bottom electrode groove and interconnection channel,
Described bottom electrode is imbedded in the described bottom electrode groove,
Described interconnection is down imbedded in the described interconnection channel.
3. semiconductor device according to claim 1, the upper surface of wherein said bottom electrode and side surface are coated with described capacitor insulating film.
4. semiconductor device according to claim 1 also comprises:
The 3rd dielectric film is formed on described bottom electrode and described interconnection down top, to be used as described capacitor insulating film; With
The 4th dielectric film is formed on described the 3rd dielectric film,
Be formed with opening in described the 4th dielectric film part that is arranged in above the described bottom electrode,
Being arranged in described the 3rd dielectric film above the described bottom electrode and the appropriate section of described the 4th dielectric film, be formed with the contact hole that runs through described the 3rd dielectric film and described the 4th dielectric film,
On the described capacitor insulation membrane portions of forming by described the 3rd dielectric film that is exposed in the described opening, be formed with described top electrode,
In the described contact hole that is connected to described down interconnection, be formed with described on interconnection.
5. semiconductor device according to claim 4, wherein
Described opening and described contact hole are separated from each other by described the 4th dielectric film,
Described top electrode and described on be interconnected in described the 4th dielectric film top and be connected to each other.
6. method that is used for producing the semiconductor devices, this method may further comprise the steps:
(a) on Semiconductor substrate, form first dielectric film;
(b) on described first dielectric film, form bottom electrode and the interconnection of forming by first metal film down;
(c) on described bottom electrode, form capacitor insulating film;
(d) on described capacitor insulating film, form the top electrode of forming by second metal film, and form in the described interconnection down form by described second metal film on interconnect,
Described upward interconnection and described top electrode form as one.
7. method according to claim 6 also is included in described step (a) afterwards and described step (b) following steps before:
On described first dielectric film, form described second dielectric film, and in described second dielectric film, form bottom electrode groove and interconnection channel then,
Described step (b) is to be used for forming described bottom electrode and to form described interconnection down in described bottom electrode groove in described interconnection channel.
8. method according to claim 6, wherein
Described step (b) is to be used on described first dielectric film forming described first metal film, and then described first metal film of composition forming described bottom electrode and described interconnection down,
Described step (c) is to be used for forming described capacitor insulating film, thereby covers the upper surface and the side surface of described bottom electrode with it.
9. method according to claim 6, wherein
Described step (c) is described the 3rd dielectric film that is used for forming above described bottom electrode and described down interconnection as described capacitor insulating film, and described method also comprises, in described step (c) afterwards and described step (d) following steps before:
(e) on described the 3rd dielectric film, form the 4th dielectric film;
(f) for the part of described the 4th dielectric film that is positioned at described bottom electrode top, carry out dry etching, reach the degree of depth place of not exposing described the 3rd dielectric film, in described the 4th dielectric film, to form opening;
(g) afterwards, form contact hole, this contact hole runs through described the 3rd dielectric film that is positioned at described interconnection down top and the appropriate section of described the 4th dielectric film in described step (f);
(h) afterwards, remove the part of staying described the 4th dielectric film in the described opening by wet etching in described step (g),
Described step (d) is to be used for forming described second metal film on described Semiconductor substrate, and described second metal film of composition forms as one described top electrode and described upward interconnection then.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004266402A JP2006086155A (en) | 2004-09-14 | 2004-09-14 | Semiconductor device and its manufacturing method |
| JP266402/2004 | 2004-09-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1750265A true CN1750265A (en) | 2006-03-22 |
| CN100463176C CN100463176C (en) | 2009-02-18 |
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ID=36032995
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101029192A Expired - Fee Related CN100463176C (en) | 2004-09-14 | 2005-09-14 | Semiconductor device and method for fabricating the same |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US20060054960A1 (en) |
| JP (1) | JP2006086155A (en) |
| KR (1) | KR20060050475A (en) |
| CN (1) | CN100463176C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104752154A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing capacitor |
| CN107799503A (en) * | 2016-08-30 | 2018-03-13 | 住友电工光电子器件创新株式会社 | Semiconductor devices with MIM capacitor |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100480641B1 (en) * | 2002-10-17 | 2005-03-31 | 삼성전자주식회사 | Metal-Insulator-Metal capacitor having high capacitance, integrated circuit chip having the same and method for manufacturing the same |
| DE102005038219B4 (en) * | 2005-08-12 | 2008-11-13 | Infineon Technologies Ag | Integrated circuit arrangement with capacitor in a track layer and method for producing the same |
| KR20230156179A (en) * | 2016-12-29 | 2023-11-13 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | Bonded structures with integrated passive component |
| JP6989207B2 (en) | 2018-05-15 | 2022-01-05 | 住友電工デバイス・イノベーション株式会社 | Capacitor manufacturing method |
| JP6981601B2 (en) | 2018-05-29 | 2021-12-15 | 住友電工デバイス・イノベーション株式会社 | Manufacturing method of semiconductor device |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3149817B2 (en) * | 1997-05-30 | 2001-03-26 | 日本電気株式会社 | Semiconductor device and method of manufacturing the same |
| US6498364B1 (en) * | 2000-01-21 | 2002-12-24 | Agere Systems Inc. | Capacitor for integration with copper damascene processes |
| US6368953B1 (en) * | 2000-05-09 | 2002-04-09 | International Business Machines Corporation | Encapsulated metal structures for semiconductor devices and MIM capacitors including the same |
| JP2002217373A (en) * | 2001-01-17 | 2002-08-02 | Mitsubishi Electric Corp | Manufacturing method of semiconductor device, and semiconductor device manufactured by using the same |
| JP2003051501A (en) * | 2001-05-30 | 2003-02-21 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing the same |
| JP5046445B2 (en) * | 2001-07-31 | 2012-10-10 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| CN1234170C (en) * | 2002-04-02 | 2005-12-28 | 华邦电子股份有限公司 | Integrated circuit device of metal-insulating body-metal capacitor and method for making the same |
| JP2004146814A (en) * | 2002-09-30 | 2004-05-20 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for producing same |
| KR100480641B1 (en) * | 2002-10-17 | 2005-03-31 | 삼성전자주식회사 | Metal-Insulator-Metal capacitor having high capacitance, integrated circuit chip having the same and method for manufacturing the same |
| US6964908B2 (en) * | 2003-08-19 | 2005-11-15 | International Business Machines Corporation | Metal-insulator-metal capacitor and method of fabricating same |
-
2004
- 2004-09-14 JP JP2004266402A patent/JP2006086155A/en not_active Ceased
-
2005
- 2005-08-10 US US11/200,115 patent/US20060054960A1/en not_active Abandoned
- 2005-08-16 KR KR1020050074740A patent/KR20060050475A/en not_active Application Discontinuation
- 2005-09-14 CN CNB2005101029192A patent/CN100463176C/en not_active Expired - Fee Related
-
2008
- 2008-02-26 US US12/071,742 patent/US20080158775A1/en not_active Abandoned
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104752154A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing capacitor |
| CN107799503A (en) * | 2016-08-30 | 2018-03-13 | 住友电工光电子器件创新株式会社 | Semiconductor devices with MIM capacitor |
| CN107799503B (en) * | 2016-08-30 | 2023-08-25 | 住友电工光电子器件创新株式会社 | Semiconductor device with MIM capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20060050475A (en) | 2006-05-19 |
| CN100463176C (en) | 2009-02-18 |
| US20080158775A1 (en) | 2008-07-03 |
| JP2006086155A (en) | 2006-03-30 |
| US20060054960A1 (en) | 2006-03-16 |
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