CN104425230A - Side wall structure and formation method thereof - Google Patents
Side wall structure and formation method thereof Download PDFInfo
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- CN104425230A CN104425230A CN201310407966.2A CN201310407966A CN104425230A CN 104425230 A CN104425230 A CN 104425230A CN 201310407966 A CN201310407966 A CN 201310407966A CN 104425230 A CN104425230 A CN 104425230A
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- Prior art keywords
- side wall
- formation method
- semiconductor substrate
- dielectric layer
- grid
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 239000010410 layer Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 9
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 8
- 239000000428 dust Substances 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000036632 reaction speed Effects 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a side wall structure and a formation method thereof. A plurality of combined side walls are formed in two sides of a gate medium layer and a gate electrode and comprise first side walls and second side walls; then the second side walls are removed, a gap is formed between each two adjacent first side walls, and the capacitance between the gate electrode and other semiconductor devices or metal connection wires can be reduced, so that the reaction speed of the semiconductor devices is enhanced and the voltage loss is reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of sidewall structure and forming method thereof.
Background technology
Along with the lasting reduction of feature sizes of semiconductor devices, the number of devices formed in same area increases, and then causes the electric capacity between semiconductor device or between grid and connecting line increasing.Under normal circumstances, semiconductor device reaction speed is mainly determined by the propagation delay (PropagationDelay) of grid time delay (Gate Delay) and signal, described propagation delay is also called RC time delay, R is the resistance of plain conductor, and C is the electric capacity that inner dielectric layer is formed.When electric capacity is increasing, the time delay of semiconductor device is longer, and namely semiconductor device reaction speed reduces, and meanwhile, electric capacity is larger also can cause the loss of semiconductor device voltage larger.
Please refer to Fig. 1, in prior art, semiconductor device structure comprises: Semiconductor substrate 10; Be formed in gate oxide 20 and the grid 30 on Semiconductor substrate 10 surface successively; Be formed at the side wall 40 of described gate oxide 20 and grid 30 both sides.
Wherein, the material of described side wall 40 is generally silicon nitride, its k value is higher, along with the density of semiconductor device is more and more higher, electric capacity between semiconductor device or between grid and connecting line is by increasing, so how to reduce electric capacity, improve the reaction speed of semiconductor device, the loss reducing voltage just becomes the technical problem that those skilled in the art are badly in need of solution.
Summary of the invention
The object of the present invention is to provide a kind of sidewall structure and forming method thereof, the electric capacity between semiconductor device or between grid and connecting line can be reduced.
To achieve these goals, the present invention proposes a kind of formation method of side wall, comprises step:
Semiconductor substrate is provided, described Semiconductor substrate is formed with gate dielectric layer and grid successively;
Form at least one combination side wall in the both sides of described gate dielectric layer and grid, combine side wall described in each and include one first side wall and one second side wall, described second side wall is between described first side wall;
Etching removes described second side wall, makes to occur space between described first side wall.
Further, in the formation method of described side wall, the number of described combination side wall is 1 ~ 10.
Further, in the formation method of described side wall, the material of described first side wall is silicon nitride.
Further, in the formation method of described side wall, the thickness range of described first side wall is 10 dust ~ 200 dusts.
Further, in the formation method of described side wall, the material of described second side wall is germanium silicon.
Further, in the formation method of described side wall, the germanium atom of described germanium silicon accounts for 10% ~ 90%.
Further, in the formation method of described side wall, the thickness range of described second side wall is 10 dust ~ 200 dusts.
Further, in the formation method of described side wall, the gas that etching removes described second side wall use is HCl, HBr, Cl
2or Br
2in one or more.
Further, in the formation method of described side wall, after etching removes described second side wall, form interlayer dielectric layer at described combination side wall and semiconductor substrate surface.
Further, in the formation method of described side wall, the material of described Semiconductor substrate is silicon.
Further, the present invention also proposes a kind of sidewall structure, and adopt any one method as described above to be formed, described sidewall structure comprises:
Semiconductor substrate; Form gate dielectric layer on the semiconductor substrate and grid successively; Be formed in multiple first side walls of described gate dielectric layer and grid both sides, between described first side wall, be formed with space.
Compared with prior art, beneficial effect of the present invention is mainly reflected in: form multiple combination side wall in the both sides of described gate dielectric layer and grid, described combination side wall comprises the first side wall and the second side wall; Then remove described second side wall, make to there is space between two adjacent the first side walls, the electric capacity between grid and other semiconductor device or metal contact wires can be reduced, thus improve the reaction speed of semiconductor device, reduce the loss of voltage.
Accompanying drawing explanation
Fig. 1 is the structural profile schematic diagram of semiconductor device in prior art;
Fig. 2 is the flow chart of formation method for side wall in one embodiment of the invention;
Fig. 3-Fig. 7 is the structural profile schematic diagram in one embodiment of the invention in side wall forming process.
Embodiment
Below in conjunction with the drawings and specific embodiments, sidewall structure that the present invention proposes and forming method thereof is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 2, in the present embodiment, propose a kind of formation method of side wall, comprise step:
S100: provide Semiconductor substrate 100, described Semiconductor substrate 100 is formed with successively gate dielectric layer 200 and grid 300, as shown in Figure 3;
Wherein, described Semiconductor substrate can be monocrystalline silicon, polysilicon or silicon-on-insulator; The material of described gate dielectric layer 200 is silicon dioxide; Described grid 300 can be polysilicon gate or metal gates.
S200: form at least one combination side wall in the both sides of described gate dielectric layer 200 and grid 300, each is organized described combination side wall and includes the first side wall 400 and the second side wall 500, and described second side wall 500 is between described first side wall 400;
Concrete, the formation method of multiple described combination side wall is as follows:
First, described first side wall 400 is formed in the both sides of described gate dielectric layer 200 and grid 300, as shown in Figure 3; The material of described first side wall 400 is silicon nitride, and its thickness range is 10 dust ~ 200 dusts, such as, be 50 dusts;
Then, described second side wall 500 is formed in the both sides of described first side wall 400, as shown in Figure 4; The material of described second side wall 500 is germanium silicon, and wherein, the germanium atom of germanium silicon accounts for 10% ~ 90%, and the thickness range of described second side wall 500 is 10 dust ~ 200 dusts, such as, be 50 dusts;
Then, described first side wall 400 is formed in the both sides of described second side wall 500, as shown in Figure 5; Same, the material of described first side wall 400 is silicon nitride, and its thickness range is 10 dust ~ 200 dusts, such as, be 50 dusts;
Then, described second side wall 500 is formed in the both sides of described first side wall 400, as shown in Figure 6; The material of described second side wall 500 is germanium silicon, and wherein, the germanium atom of germanium silicon accounts for 10% ~ 90%, and the thickness range of described second side wall 500 is 10 dust ~ 200 dusts, such as, be 50 dusts.
The number of described combination side wall is 1 ~ 10, and concrete number can be selected in technique by root.
S300: etching removes described second side wall 500, makes to occur space 600 between described first side wall 400, as shown in Figure 7;
Wherein, etching removes the gas of described second side wall 500 use is HCl, HBr, Cl
2or Br
2in one or more; After removing described second side wall 500, between described first side wall 400, occur that space can as side wall; Because difference dielectric dielectric constant k value is different, dielectric k value is less, and electric capacity is also less, and the k value of vacuum is 1, minimum in all material, and the k value of air is 1.0006 also very little.Use space can reduce the electric capacity between grid and other semiconductor device or metal contact wires significantly as side wall.
In the present embodiment, after etching removes described second side wall 500, form interlayer dielectric layer (not shown) at described combination side wall and Semiconductor substrate 100 surface.
In the present embodiment, also propose a kind of sidewall structure, adopt said method to be formed, described sidewall structure comprises:
Semiconductor substrate 100; Be formed in the gate dielectric layer 200 in described Semiconductor substrate 100 and grid 300 successively; Be formed in multiple first side walls 400 of described gate dielectric layer 200 and grid 300 both sides, between described first side wall 400, be formed with space 600.
To sum up, in sidewall structure that the embodiment of the present invention provides and forming method thereof, form multiple combination side wall in the both sides of described gate dielectric layer and grid, described combination side wall comprises the first side wall and the second side wall; Then remove described second side wall, make to there is space between two adjacent the first side walls, the electric capacity between grid and other semiconductor device or metal contact wires can be reduced, thus improve the reaction speed of semiconductor device, reduce the loss of voltage.
Above are only the preferred embodiments of the present invention, any restriction is not played to the present invention.Any person of ordinary skill in the field; in the scope not departing from technical scheme of the present invention; the technical scheme disclose the present invention and technology contents make the variations such as any type of equivalent replacement or amendment; all belong to the content not departing from technical scheme of the present invention, still belong within protection scope of the present invention.
Claims (11)
1. a formation method for side wall, comprises step:
Semiconductor substrate is provided, described Semiconductor substrate is formed with gate dielectric layer and grid successively;
Form at least one combination side wall in the both sides of described gate dielectric layer and grid, combine side wall described in each and include one first side wall and one second side wall, described second side wall is between described first side wall;
Etching removes described second side wall, makes to occur space between described first side wall.
2. the formation method of side wall as claimed in claim 1, it is characterized in that, the number of described combination side wall is 1 ~ 10.
3. the formation method of side wall as claimed in claim 1, it is characterized in that, the material of described first side wall is silicon nitride.
4. the formation method of side wall as claimed in claim 3, it is characterized in that, the thickness range of described first side wall is 10 dust ~ 200 dusts.
5. the formation method of side wall as claimed in claim 1, it is characterized in that, the material of described second side wall is germanium silicon.
6. the formation method of side wall as claimed in claim 5, it is characterized in that, the germanium atom of described germanium silicon accounts for 10% ~ 90%.
7. the formation method of side wall as claimed in claim 5, it is characterized in that, the thickness range of described second side wall is 10 dust ~ 200 dusts.
8. the formation method of side wall as claimed in claim 1, is characterized in that, the gas that etching removes described second side wall use is HCl, HBr, Cl
2or Br
2in one or more.
9. the formation method of side wall as claimed in claim 1, is characterized in that, after etching removes described second side wall, forms interlayer dielectric layer at described combination side wall and semiconductor substrate surface.
10. the formation method of side wall as claimed in claim 1, it is characterized in that, the material of described Semiconductor substrate is silicon.
11. 1 kinds of sidewall structures, adopt as any one method in claim 1 to 10 is formed, described sidewall structure comprises:
Semiconductor substrate; Form gate dielectric layer on the semiconductor substrate and grid successively; Be formed in multiple first side walls of described gate dielectric layer and grid both sides, between described first side wall, be formed with space.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310407966.2A CN104425230A (en) | 2013-09-09 | 2013-09-09 | Side wall structure and formation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310407966.2A CN104425230A (en) | 2013-09-09 | 2013-09-09 | Side wall structure and formation method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN104425230A true CN104425230A (en) | 2015-03-18 |
Family
ID=52973916
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310407966.2A Pending CN104425230A (en) | 2013-09-09 | 2013-09-09 | Side wall structure and formation method thereof |
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| Country | Link |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1501492A (en) * | 2002-11-15 | 2004-06-02 | 联华电子股份有限公司 | Integrated circuit structure with air gap and manufacturing method thereof |
| WO2006045722A1 (en) * | 2004-10-28 | 2006-05-04 | Infineon Technologies Ag | Semi-conductor element and associated production method |
| US20080128766A1 (en) * | 2005-03-31 | 2008-06-05 | International Business Machines Corporation | Mosfet structure with ultra-low k spacer |
-
2013
- 2013-09-09 CN CN201310407966.2A patent/CN104425230A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1501492A (en) * | 2002-11-15 | 2004-06-02 | 联华电子股份有限公司 | Integrated circuit structure with air gap and manufacturing method thereof |
| WO2006045722A1 (en) * | 2004-10-28 | 2006-05-04 | Infineon Technologies Ag | Semi-conductor element and associated production method |
| US20080128766A1 (en) * | 2005-03-31 | 2008-06-05 | International Business Machines Corporation | Mosfet structure with ultra-low k spacer |
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| PB01 | Publication | ||
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Application publication date: 20150318 |