JPH07326670A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH07326670A JPH07326670A JP11865994A JP11865994A JPH07326670A JP H07326670 A JPH07326670 A JP H07326670A JP 11865994 A JP11865994 A JP 11865994A JP 11865994 A JP11865994 A JP 11865994A JP H07326670 A JPH07326670 A JP H07326670A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- insulating film
- wirings
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体集積回路装置技
術に関し、特に、金属配線の間隙が狭い半導体集積回路
装置に適用して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device technique, and more particularly to a technique effectively applied to a semiconductor integrated circuit device having a narrow gap between metal wirings.
【0002】[0002]
【従来技術】例えば、従来の金属配線の状態を図10に
示す。半導体基板11は、単結晶シリコンから成り、そ
の表面には酸化シリコンの絶縁層12が形成され、その
表面に下層金属配線13がパターン形成されている。そ
して、この下層金属配線と上層金属配線17の層間絶縁
膜として機能する酸化シリコン膜14,16及びこの絶
縁膜の平坦化に寄与するSOG膜15とを有している半
導体集積回路が先行技術として考えられる。例えば、多
層配線に関する刊行物に、特開平5−218028等が
ある。2. Description of the Related Art For example, a state of a conventional metal wiring is shown in FIG. The semiconductor substrate 11 is made of single crystal silicon, an insulating layer 12 of silicon oxide is formed on the surface thereof, and a lower layer metal wiring 13 is patterned on the surface thereof. A semiconductor integrated circuit having the silicon oxide films 14 and 16 functioning as an interlayer insulating film of the lower metal wiring and the upper metal wiring 17 and the SOG film 15 contributing to the flattening of the insulating film is a prior art. Conceivable. For example, Japanese Patent Laid-Open No. 5-218028 and the like are publications relating to multilayer wiring.
【0003】[0003]
【発明が解決しようとする課題】この従来の多層配線の
構造の多くは、酸化シリコン膜14の比誘電率が約4程
度であり、回路の高集積化に伴って下層金属配線13の
間隔が1ミクロン以下となる最近の半導体装置において
は、配線間の容量が増大するため、特に、電気信号の伝
搬速度を遅延させる等、半導体集積回路装置の電気的特
性に悪影響を及ぼし始めている。In many of the conventional multilayer wiring structures, the relative permittivity of the silicon oxide film 14 is about 4, and the spacing between the lower layer metal wirings 13 is increased as the circuit becomes highly integrated. In recent semiconductor devices having a size of 1 micron or less, the capacitance between wirings increases, so that the electrical characteristics of the semiconductor integrated circuit device are beginning to be adversely affected, especially by delaying the propagation speed of electrical signals.
【0004】然るに、上記従来技術においては、層間絶
縁膜の膜厚や材料を決定する際、アルファ線や平坦性等
に考慮しているが、隣接する金属配線間の配線容量を低
減させるための対策については十分な手段が施されてい
なかった。However, in the above-mentioned prior art, when determining the film thickness and material of the interlayer insulating film, alpha rays and flatness are taken into consideration, but in order to reduce the wiring capacitance between the adjacent metal wirings. As for measures, sufficient measures were not taken.
【0005】また、電気信号の伝搬速度の遅延を避ける
ため、所定配線間の許容間隔やMOSトランジスタの閾
値電圧の許容範囲等が狭小となる結果、半導体集積回路
の製造プロセスに一定の限界が生じるに至っている。Further, in order to avoid the delay of the propagation speed of the electric signal, the allowable interval between the predetermined wirings and the allowable range of the threshold voltage of the MOS transistor are narrowed. As a result, a certain limit occurs in the manufacturing process of the semiconductor integrated circuit. Has reached.
【0006】本発明は、上記課題に着目してなされたも
のであり、その目的は、金属若しくは単結晶シリコン・
ストリップからなる配線間の配線容量を有効に低減する
ことができる技術を提供することにある。The present invention has been made in view of the above problems, and its purpose is to provide a metal or single crystal silicon.
It is an object of the present invention to provide a technique capable of effectively reducing the wiring capacitance between wirings made of strips.
【0007】本発明の他の目的は、半導体集積回路装置
の動作速度を向上させることができる技術を提供するこ
とである。本発明の他の目的は、半導体集積回路装置の
製造プロセスの制約を緩和することができる技術を提供
することにある。本発明の新規な構成及び効果は、明細
書の記載および添付図面から明らかになるであろう。Another object of the present invention is to provide a technique capable of improving the operating speed of a semiconductor integrated circuit device. Another object of the present invention is to provide a technique capable of relaxing restrictions on the manufacturing process of a semiconductor integrated circuit device. The novel structure and effect of the present invention will be apparent from the description of the specification and the accompanying drawings.
【0008】[0008]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を説明すれば、以下の
如くである。The typical ones of the inventions disclosed in the present application will be outlined below.
【0009】本発明の半導体装置は、微細化する金属配
線の間に比誘電率が約1と非常に小さい空隙を有するこ
とによって、この金属配線間の静電容量を低減させ集積
回路の電気的特性を向上させるものである。具体的に
は、半導体装置の配線工程において、微細な金属配線を
形成し、前記金属配線の間の溝の間に、CVD法または
スパッタ法を用いて隣接する金属配線間に空隙を生じる
ような条件で絶縁膜を形成する。更に、絶縁膜の比誘電
率がシリコン酸化膜の比誘電率よりも低い材料、例え
ば、ポリイミド系樹脂を選択すれば前記金属配線間の静
電容量をより低減させることも可能である。According to the semiconductor device of the present invention, the gap between the metal wirings to be miniaturized has a very small relative dielectric constant of about 1, so that the capacitance between the metal wirings can be reduced and the electrical characteristics of the integrated circuit can be reduced. It is intended to improve the characteristics. Specifically, in a wiring process of a semiconductor device, fine metal wirings are formed, and voids are formed between adjacent metal wirings by using a CVD method or a sputtering method between grooves between the metal wirings. An insulating film is formed under the conditions. Furthermore, if a material having a relative dielectric constant of the insulating film lower than that of the silicon oxide film, for example, a polyimide resin is selected, it is possible to further reduce the capacitance between the metal wirings.
【0010】[0010]
【作用】上記発明によれば、隣接する配線相互間に低誘
電率の空隙を配置させたことにより、当該配線相互間の
誘電率を有効に低減させることが可能となる。更に、該
空隙の上に形成される回路及び配線層の信頼性を低下さ
せることなく半導体装置を集積化して、歩留まりを向上
させることが可能となる。According to the above invention, by arranging the void having a low dielectric constant between the adjacent wirings, the dielectric constant between the wirings can be effectively reduced. Furthermore, it is possible to improve the yield by integrating the semiconductor device without lowering the reliability of the circuit and the wiring layer formed on the void.
【0011】この結果、電気信号が金属配線を充電若し
くは放電する際の時間を、従来に比して短縮することが
できるので、電気信号の伝搬速度を高速にすることがで
きる。As a result, the time required for the electric signal to charge or discharge the metal wiring can be shortened as compared with the conventional case, so that the propagation speed of the electric signal can be increased.
【0012】[0012]
【実施例】図1から図4は、本発明の一実施例である半
導体集積回路装置の製造プロセスを示す。本実施例の半
導体集積回路用の金属配線は、微細加工されたDRA
M、MPU、マスクROM、ゲート・アレイ等に応用す
ることができる。1 to 4 show a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention. The metal wiring for the semiconductor integrated circuit of this embodiment is a finely processed DRA.
It can be applied to M, MPU, mask ROM, gate array, etc.
【0013】まず、図1には、半導体基板の上の絶縁膜
1を形成し、その上に金属配線2をパターン形成した態
様が示されている。例えば、本実施例においては、金属
配線の間隔は、64MDRAMの場合、0.04μmで
あり、また、256mDRAMの場合、0.025μm
でパターニングすることができる。もっとも、配線密度
が厳しくなければ、低誘電体の空隙を特に設ける必要は
ない。図2には、その後、CVD法を用いて絶縁膜3を
金属配線2及び前記絶縁膜基板1の上に堆積させる態様
を示す。この際、金属配線1の上部の角に従って堆積す
るような条件で絶縁膜3を堆積させていく。図3には、
この条件で膜を堆積していくと隣接配線間の溝が絶縁膜
で充填される前に隣接金属配線上部の膜同士を接触さ
せ、空隙4を形成する状態を示す。このとき、比誘電率
が約1の空隙を形成することができ、隣接配線間の容量
を低減する手段を提供することができる。図4には、金
属配線1と金属配線2を接続するためのコンタクト穴
(図9参照。)を形成した後に、金属配線5を形成する
工程を示す。また、上記の絶縁膜3が低誘電率のもので
あれば金属配線2と金属配線5との容量も低減できる。
CVD法には、例えばモノシランと酸素を反応させて酸
化シリコンを形成する方法や通常のTEOS−CVDに
SiF4 若しくはC2 F6 を添加してフッ素をシリコン
酸化膜にドープする方法、CVD法でポリイミド系の絶
縁膜を堆積させる方法等がある。First, FIG. 1 shows a mode in which an insulating film 1 is formed on a semiconductor substrate, and a metal wiring 2 is patterned on the insulating film 1. For example, in the present embodiment, the space between the metal wirings is 0.04 μm in the case of 64 MDRAM and 0.025 μm in the case of 256 mDRAM.
Can be patterned. However, if the wiring density is not severe, it is not necessary to particularly provide a low dielectric void. FIG. 2 shows a mode in which the insulating film 3 is then deposited on the metal wiring 2 and the insulating film substrate 1 by using the CVD method. At this time, the insulating film 3 is deposited under the condition that it is deposited along the upper corner of the metal wiring 1. In Figure 3,
When the films are deposited under this condition, the films on the adjacent metal wirings are brought into contact with each other before the grooves between the adjacent wirings are filled with the insulating film, and the voids 4 are formed. At this time, a void having a relative dielectric constant of about 1 can be formed, and a means for reducing the capacitance between adjacent wirings can be provided. FIG. 4 shows a step of forming a metal wiring 5 after forming a contact hole (see FIG. 9) for connecting the metal wiring 1 and the metal wiring 2. If the insulating film 3 has a low dielectric constant, the capacitance between the metal wiring 2 and the metal wiring 5 can be reduced.
Examples of the CVD method include a method of reacting monosilane and oxygen to form silicon oxide, a method of adding SiF 4 or C 2 F 6 to ordinary TEOS-CVD to dope fluorine into a silicon oxide film, and a CVD method. There is a method of depositing a polyimide insulating film.
【0014】図5から図8には、本発明の第2の実施例
である半導体集積回路装置の工程順断面図を示す。5 to 8 are sectional views in order of the steps of a semiconductor integrated circuit device according to the second embodiment of the present invention.
【0015】まず、図5は、絶縁膜1の上に金属配線2
を形成した断面図を、図6は、スパッタ法を用いて絶縁
膜6を金属配線2及び絶縁膜1の上に堆積させた断面図
をそれぞれ示す、金属配線2の上部の角にコンフォーマ
ル(conformal)な膜が堆積するような条件で
膜を堆積することができる。図7は、この条件で膜を堆
積していくと隣接配線間の溝が絶縁膜で充填される前に
隣接金属配線上部の膜同士が接触し、空隙4を形成する
工程断面図を示す。このとき比誘電率が約1の空隙を形
成することによって隣接配線間の容量を低減することが
できる。図8は、下部金属配線2と上部金属配線5を接
続するためのコンタクト穴(図9参照)を形成した後、
金属配線5を形成した断面図を示す。また、上記の絶縁
膜3が低誘電率のものであれば金属配線2と金属配線5
と間の容量も低減できる。このとき、スパッタされる膜
には、シリコン酸化膜、フッ素をドープしたシリコン酸
化膜(SiOF)、ポリイミド、ポリテトラフルオロエ
チレン(PTFE)等を適宜選択して用いることができ
る。First, in FIG. 5, a metal wiring 2 is formed on the insulating film 1.
6 is a cross-sectional view in which the insulating film 6 is deposited on the metal wiring 2 and the insulating film 1 by a sputtering method, and FIG. The film can be deposited under conditions such that a conformal film is deposited. FIG. 7 is a process cross-sectional view in which the films on the adjacent metal wirings are in contact with each other before the trenches between the adjacent wirings are filled with the insulating film and the voids 4 are formed when the films are deposited under this condition. At this time, the capacitance between adjacent wirings can be reduced by forming a void having a relative dielectric constant of about 1. In FIG. 8, after forming contact holes (see FIG. 9) for connecting the lower metal wiring 2 and the upper metal wiring 5,
The sectional view which formed the metal wiring 5 is shown. If the insulating film 3 has a low dielectric constant, the metal wiring 2 and the metal wiring 5
The capacity between and can also be reduced. At this time, a silicon oxide film, a silicon oxide film (SiOF) doped with fluorine, polyimide, polytetrafluoroethylene (PTFE), or the like can be appropriately selected and used as the film to be sputtered.
【0016】前記絶縁膜には、上記フッ素を含有する酸
化シリコンの他、有機物を含有する酸化シリコン、テフ
ロン等の低誘電率の材料によって形成することもでき
る。図9は、本発明の別の実施例である半導体メモリの
要部断面を示す。上記実施例は下部金属配線相互の容量
を低減する態様を説明したが、本実施例は、3層金属配
線を用いたDRAMに適用したものである。即ち、上記
実施例と同様のプロセスを用いて、先ず、高融点金属で
あるタングステンからなる第1レベルのB/L20を形
成し、次にタングステンからなる第2レベルのYセレク
ト線5を形成し、最後に、アルミとチタン・ナイトライ
ドとの積層構造によるW/L2を形成することで、同一
レベルの金属配線間の容量を空隙4,4′,4″によっ
て低減しつつ、上層若しくは下層の金属配線相互の容量
を層間絶縁膜1,3,6によって低減することができ
る。もっともメモリ・セル・プレート電極等と金属配線
との容量も層間絶縁膜によって低減することができるの
は言うまでもない。特に、空隙部4には、材料に含有さ
れるアルファ線を放射する放射性物質が存在し得ないた
め、DRAMキャパシタの電荷蓄積ノード22等に対す
る悪影響も生じる虞がない点で有利である。In addition to the above-mentioned fluorine-containing silicon oxide, the insulating film may be formed of a low dielectric constant material such as silicon oxide containing an organic substance or Teflon. FIG. 9 shows a cross section of a main part of a semiconductor memory according to another embodiment of the present invention. Although the above embodiment has described the mode of reducing the capacitance between the lower metal wirings, this embodiment is applied to the DRAM using the three-layer metal wiring. That is, using the same process as in the above embodiment, first, the first level B / L 20 made of tungsten which is a refractory metal is formed, and then the second level Y select line 5 made of tungsten is formed. Finally, by forming W / L2 having a laminated structure of aluminum and titanium nitride, the capacitance between the metal wirings at the same level is reduced by the voids 4, 4 ′, 4 ″, and the upper or lower layer is formed. The capacitance between the metal wirings can be reduced by the interlayer insulating films 1, 3, and 6. It goes without saying that the capacitance between the memory cell plate electrode and the metal wiring can also be reduced by the interlayer insulating film. In particular, since no radioactive substance that emits alpha rays contained in the material can exist in the void portion 4, it has an adverse effect on the charge storage node 22 of the DRAM capacitor. It is advantageous in that there is no possibility that occur.
【0017】更に、上記空隙の高さを金属配線の厚さよ
り高くすればより配線容量の低減を図ることが可能とな
る。この場合、パターニングした各金属配線2,5,2
0の間に存在する各絶縁層6,3,1をエッチバックし
て溝を深く掘った後に、上記プロセスと同様に低誘電率
の材料を堆積させることで金属配線の厚さをより大きな
空隙を形成するのである。Furthermore, if the height of the void is made higher than the thickness of the metal wiring, the wiring capacitance can be further reduced. In this case, each patterned metal wiring 2, 5, 2
After the insulating layers 6, 3, 1 existing between 0 are etched back to dig a groove deeply, a low dielectric constant material is deposited in the same manner as in the above process to increase the thickness of the metal wiring to a larger void. Is formed.
【0018】以上の説明では、主としてDRAMの金属
配線に適用した場合について説明したが、これに限定さ
れず、例えば、SRAM、EEPROM、EPROM、
マイクロプロセッサ等の多層配線を有する半導体集積回
路装置に適用することも可能である。In the above description, the case where the present invention is mainly applied to the metal wiring of the DRAM has been described, but the present invention is not limited to this and, for example, SRAM, EEPROM, EPROM,
It can also be applied to a semiconductor integrated circuit device having multi-layer wiring such as a microprocessor.
【0019】[0019]
【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
次の通りである。すなわち、徴細化する金属配線の間に
非常に小さい比誘電率(約1)の空隙を形成することに
よって、この金属配線の間の静電容量を減少することが
できる。具体的には、CVD法またはスパッタ法によっ
て隣接配線の金属配線の上部の角にコンフォーマル(c
onformal)な膜が堆積するような条件で膜を堆
積させていくと、隣接配線間の溝が絶縁膜で充填される
前に接触し、空隙を形成することができ、半導体集積回
路装置の配線間の静電容量を減らすことが可能となる。
よって、集積回路の動作速度等の電気的特性を向上し得
るという効果を奏する。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows. That is, by forming a void having a very small relative dielectric constant (about 1) between the metal wirings to be thinned, the capacitance between the metal wirings can be reduced. Specifically, a conformal (c) is formed on the upper corner of the metal wiring of the adjacent wiring by CVD or sputtering.
If a film is deposited under such a condition that an (normal) film is deposited, a groove between adjacent wirings can be brought into contact with each other before being filled with an insulating film, and a void can be formed, and a wiring of a semiconductor integrated circuit device can be formed. It is possible to reduce the capacitance between them.
Therefore, it is possible to improve the electrical characteristics such as the operating speed of the integrated circuit.
【0020】また、CVD法またはスパッタ法で堆積さ
れる膜が低誘電率の膜であれば更に、配線間の容量を低
減することができ、また、上部の金属配線との容量も同
時に低減できる。If the film deposited by the CVD method or the sputtering method has a low dielectric constant, the capacitance between the wirings can be further reduced, and the capacitance with the upper metal wiring can be reduced at the same time. .
【図1】本発明の第1の実施例である半導体集積回路用
の金属配線の断面図である。FIG. 1 is a cross-sectional view of a metal wiring for a semiconductor integrated circuit that is a first embodiment of the present invention.
【図2】本発明の第1の実施例である配線工程の一部断
面図である。FIG. 2 is a partial cross-sectional view of a wiring process which is the first embodiment of the present invention.
【図3】本発明の第1の実施例である配線間の空隙部の
断面図である。FIG. 3 is a cross-sectional view of a void portion between wirings, which is the first embodiment of the present invention.
【図4】本発明の第1の実施例である半導体集積回路用
の上部及び下部配線の要部断面図である。FIG. 4 is a cross-sectional view of essential parts of upper and lower wirings for a semiconductor integrated circuit according to the first embodiment of the present invention.
【図5】本発明の第2の実施例である半導体集積回路用
の金属配線の断面図である。FIG. 5 is a sectional view of metal wiring for a semiconductor integrated circuit according to a second embodiment of the present invention.
【図6】本発明の第2の実施例である配線工程の一部断
面図である。FIG. 6 is a partial cross-sectional view of a wiring process which is a second embodiment of the present invention.
【図7】本発明の第2の実施例である配線間の空隙部の
断面図である。FIG. 7 is a cross-sectional view of a void portion between wirings, which is a second embodiment of the present invention.
【図8】本発明の第2の実施例である半導体集積回路用
の上部及び下部配線の要部断面図である。FIG. 8 is a cross-sectional view of essential parts of upper and lower wirings for a semiconductor integrated circuit according to a second embodiment of the present invention.
【図9】本発明の別の実施例であるダイナミック型半導
体メモリの要部の前方及び後方断面図を合成したもので
ある。FIG. 9 is a combination of front and rear sectional views of a main part of a dynamic semiconductor memory according to another embodiment of the present invention.
【図10】従来の多層配線の断面図である。FIG. 10 is a cross-sectional view of a conventional multilayer wiring.
1 絶縁膜基板 2 金属配線 3 CVD法で堆積させた絶縁膜 4 空隙部 5 金属配線 6 スパッタ法で堆積させた絶縁膜 11 単結晶シリコン 12 酸化シリコン 13 下層金属配線 14 酸化シリコン 15 SOG膜 16 酸化シリコン 17 上層金属配線 19 ソース・ドレイン 20 タングステン配線層 21 キャパシタ・プレート電極 22 電荷蓄積ノード 30 ワードライン DESCRIPTION OF SYMBOLS 1 Insulating film substrate 2 Metal wiring 3 Insulating film deposited by CVD method 4 Void portion 5 Metal wiring 6 Insulating film deposited by sputtering method 11 Single crystal silicon 12 Silicon oxide 13 Lower metal wiring 14 Silicon oxide 15 SOG film 16 Oxidation Silicon 17 Upper layer metal wiring 19 Source / drain 20 Tungsten wiring layer 21 Capacitor plate electrode 22 Charge storage node 30 Word line
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 23/12 N ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location 23/12 N
Claims (5)
路を構成する相互配線であって、複数の金属配線と、こ
の金属配線相互間の溝部に位置する低誘電率の空隙と、
この空隙及び金属配線の上に堆積させる絶縁膜とを含む
半導体集積回路装置。1. An interconnect for forming a semiconductor integrated circuit formed on a semiconductor substrate, comprising: a plurality of metal interconnects; and a low dielectric constant void located in a groove between the metal interconnects.
A semiconductor integrated circuit device including an insulating film deposited on the void and the metal wiring.
れている特許請求の範囲第1項の半導体集積回路装置。2. The semiconductor integrated circuit device according to claim 1, wherein the insulating film is deposited by a CVD method.
されている特許請求の範囲第1項の半導体集積回路装
置。3. The semiconductor integrated circuit device according to claim 1, wherein the insulating film is deposited by a sputtering method.
化膜の比誘電率よりも低い特許請求の範囲第1項の半導
体集積回路装置。4. The semiconductor integrated circuit device according to claim 1, wherein the relative dielectric constant of the insulating film is lower than the relative dielectric constant of the silicon oxide film.
リコン、有機物を含有する酸化シリコン、ポリイミド、
テフロン等の低誘電体材料から選ばれた一つ、或は、こ
れら材料を含む特許請求の範囲第1項の半導体集積回路
装置。5. The insulating film comprises silicon oxide containing fluorine, silicon oxide containing organic matter, polyimide,
2. A semiconductor integrated circuit device according to claim 1, wherein one of low-dielectric materials such as Teflon is selected, or these materials are included.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11865994A JPH07326670A (en) | 1994-05-31 | 1994-05-31 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11865994A JPH07326670A (en) | 1994-05-31 | 1994-05-31 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07326670A true JPH07326670A (en) | 1995-12-12 |
Family
ID=14742047
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11865994A Pending JPH07326670A (en) | 1994-05-31 | 1994-05-31 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07326670A (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6064118A (en) * | 1997-04-18 | 2000-05-16 | Nec Corporation | Multilevel interconnection structure having an air gap between interconnects |
US6093633A (en) * | 1996-02-29 | 2000-07-25 | Nec Corporation | Method of making a semiconductor device |
US6440839B1 (en) * | 1999-08-18 | 2002-08-27 | Advanced Micro Devices, Inc. | Selective air gap insulation |
JP2004172620A (en) * | 2002-11-15 | 2004-06-17 | United Microelectronics Corp | Integrated circuit with air gaps and its manufacturing method |
KR100487414B1 (en) * | 2000-12-23 | 2005-05-03 | 주식회사 하이닉스반도체 | Manufacturing method of semiconductor device |
US7698671B2 (en) | 2006-11-22 | 2010-04-13 | Panasonic Corporation | Method for designing semiconductor integrated circuits having air gaps. |
JP2010153904A (en) * | 2010-03-04 | 2010-07-08 | Renesas Technology Corp | Semiconductor device |
US9472453B2 (en) | 2014-03-13 | 2016-10-18 | Qualcomm Incorporated | Systems and methods of forming a reduced capacitance device |
US9543194B2 (en) | 2014-12-05 | 2017-01-10 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US9991249B2 (en) | 2016-02-11 | 2018-06-05 | Samsung Electronics Co., Ltd. | Integrated circuit and computer-implemented method of manufacturing the same |
-
1994
- 1994-05-31 JP JP11865994A patent/JPH07326670A/en active Pending
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6093633A (en) * | 1996-02-29 | 2000-07-25 | Nec Corporation | Method of making a semiconductor device |
US6064118A (en) * | 1997-04-18 | 2000-05-16 | Nec Corporation | Multilevel interconnection structure having an air gap between interconnects |
US6368939B1 (en) * | 1997-04-18 | 2002-04-09 | Nec Corporation | Multilevel interconnection structure having an air gap between interconnects |
US6440839B1 (en) * | 1999-08-18 | 2002-08-27 | Advanced Micro Devices, Inc. | Selective air gap insulation |
KR100487414B1 (en) * | 2000-12-23 | 2005-05-03 | 주식회사 하이닉스반도체 | Manufacturing method of semiconductor device |
JP2004172620A (en) * | 2002-11-15 | 2004-06-17 | United Microelectronics Corp | Integrated circuit with air gaps and its manufacturing method |
US7698671B2 (en) | 2006-11-22 | 2010-04-13 | Panasonic Corporation | Method for designing semiconductor integrated circuits having air gaps. |
JP2010153904A (en) * | 2010-03-04 | 2010-07-08 | Renesas Technology Corp | Semiconductor device |
US9472453B2 (en) | 2014-03-13 | 2016-10-18 | Qualcomm Incorporated | Systems and methods of forming a reduced capacitance device |
US9543194B2 (en) | 2014-12-05 | 2017-01-10 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US9991249B2 (en) | 2016-02-11 | 2018-06-05 | Samsung Electronics Co., Ltd. | Integrated circuit and computer-implemented method of manufacturing the same |
US10418354B2 (en) | 2016-02-11 | 2019-09-17 | Samsung Electronics Co., Ltd. | Integrated circuit and computer-implemented method of manufacturing the same |
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