CN1399736A - 用于处理器的转移指令 - Google Patents
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- LHMQDVIHBXWNII-UHFFFAOYSA-N 3-amino-4-methoxy-n-phenylbenzamide Chemical compound C1=C(N)C(OC)=CC=C1C(=O)NC1=CC=CC=C1 LHMQDVIHBXWNII-UHFFFAOYSA-N 0.000 description 1
- 108010072610 N-acetyl-gamma-glutamyl-phosphate reductase Proteins 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
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- 238000010586 diagram Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
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- 230000010365 information processing Effects 0.000 description 1
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- G—PHYSICS
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- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/321—Program or instruction counter, e.g. incrementing
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- G06F9/00—Arrangements for program control, e.g. control units
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- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
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- Engineering & Computer Science (AREA)
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- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Multi Processors (AREA)
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Abstract
描述一种如基于处理器(12)的多线程硬件处理器。处理器(12)包括计算机指令(20),它是根据任何指令值是真或假引起指令流执行中的转移的转移指令。该指令还包括一标记,它规定在完成转移操作之前执行该转移指令后的指令的数目。
Description
背景技术
本发明涉及转移指令。
并行处理是计算过程中并发事件信息处理的有效形式。并行处理要求在一台计算机中同时执行多个程序。顺序处理或串行处理将所有任务顺序地在单个工作站上完成,而管线处理使任务在专用的工作站上完成。无论在并行处理机,管线机或顺序处理机上执行的计算机程序都包括转移,其中顺序地执行一个指令流,并从该序列转移到不同的指令序列。
附图简要说明
图1是使用一个处理器的通信***的方框图。
图2是图1的详细方框图。
图3是用于图1和2的处理器中的一个微引擎的方框图。
图4是图3的微引擎管线的方框图。
图5A-5C示出转移指令的示例性格式。
图6是通用寄存器的方框图。
描述
参照图1,通信***10包括一处理器12。在一个实施例中,处理器是基于硬件的多线程处理器12。处理器12连接到如PCI总线14,存储***16和第二总线18那样的总线。对于能了解成并行子任务或功能的任务***10特别有用。具体说来,基于硬件的多线程处理器12对面向宽带而非向等待时间的任务有用。基于硬件的多线程处理器12有多个微引擎22,每个有多个硬件控制的线程,它们能同时活动并对一个任务独立地工作。
基于硬件的多线程处理器12还包括中央处理器20,它对基于硬件的多线程处理器12加载微码控制予以协助,并完成其他计算机类型的功能,如处理协议,例如,对包括处理的额外支持,其中微引擎将包送出,作如在边界条件中那样更的处理。在一个实施例中,处理器20是基于Strong ArmR(Arm是美国ARM有限公司的商标)的结构。通向处理器20具有操作***。通过操作***处理器20能调用功能在微引擎22a-22f上运行。处理器20能使用任何支持的操作***,最好是实时操作***。对作为Strong Arm结构实现的核心处理器能使用的操作***如Microsoft NTRreal-time,VXWorks,和CUS,一个在因特网上可用的自由件(freeware)操作***。
基于硬件的多线程处理器12还包括多个功能引擎22a-22f。功能微引擎(微引擎)22a-22f每个包含硬件的程序计数器和与这些程序计数器有关的状态。实际上,对应的多个线程组能在每个微引擎22a-22f上同时活动而在任何时刻只有一个实际在操作。
微引擎22a-22f每个具有处理4个硬件线程的能力。微引擎22a-22f带着共享资源操作,包括存储***16和总线接口24和28。存储***16包括同步动态随机存储器(SDRAM)控制器26a静态随机存储器(SRAM)控制器26b。SDRAM存储器16a和SDRAM控制器26a通常用于处理大量数据,如处理从网络包来的网络有效负载(Payload)。SRAM控制器26b和SRAM存储器16b用于如网络包处理,页式图象(Postscript)处理器,或作为用于如RAID盘存储的存储子***的处理器,或用于低等待时间,快速访问任务的处理器,这些任务如访问查找表,核心处理器20的存储器等。
处理器12包括总线接口28,将处理器连接到第二总线18。在一个实施例中,总线28将处理器12连接到所谓的FBUS(FIFO总线)。处理器12包括如PCI总线接口24那样的第二接口。将在PCI总路线14上的其他***部件连接的处理器12。PCI总线接口24提供到SDRAM存储器16a的高速数据通道24a。通过该通道,数据能借助直接存储器访问(DMA)传输,通过PCI总线14从SDRAM16a快速传递。
每个功能单元连接到一个或多个内部总线。内部总线是双向32位总线(即一根总线用于读,一根总线用于写)。基于硬件的多线程处理器12还构造成使得在处理器12中内部总线的带宽之和超过连接到处理器12的外部总线的带宽,处理器12包括一内部核心处理器总线32,如ASB总线(先进***总线),它将处理器核心20连接到存储控制器26a、26c和如下所述的ASB翻译器。ASB总线是与Strong Arm处理器核心一起用的所谓AMBA总线的子集。处理器12还包括一专用总线34,它将微引擎单元连接到SRAM控制器26b,ASB翻译器30和FBUS接口28。存储器总线38将存储控制器26a、26b连接至总线接口24和28以及存储***16,包括用于自引导操作等的闪存只读存储器16c。
参考图2,每个微引擎22a-22f包括判优电路,它检查标志以确定在可用的线程上操作。从任何一微引擎22a-22f来的任一线程能访问SDRAM控制器26a,SRAM控制器26b或FBUS接口28。存储控制器26a和26b每个包括多个队列,存放未完成的存储器调用请求。FBUS总线28对每个MAC设备支持的端口支持发送和接收(Transnit and Receive)标志,以及指出何时要求服务的中断标志。FBUS接口28还包括控制器28a,它完成从FBUS18来的包的头标处理。控制器28a提取包的头标,并完成在SRAM中的可编微程序的源/目标/协议的散列查找(用于地址光滑)。
核心处理器20访问共享资源。核心处理器20具有通过总线32到SDRAM控制器26a,到总线接口24,和到SRAM控制器26b的直接通信。但是,为了访问微引擎22a-22f和位于任一个微引擎22a-22f的传输寄存器,核心处理器20通过ASB翻译器30,经总线34访问微引擎22a-22f。ASB翻译器30物理上驻留在FBDS接口28中,但逻辑上是分开的。ASB翻译器30实现FBUS微引擎传输寄存器位置和核心处理器地址(即ASB总线)之间的地址翻译,使核心处理器20能访问属于微引擎22a-22c的寄存器。
虽然微引擎22能如下所述使用寄存器组交换数据,还提供一便笺式存储器27,以允许微引擎写出数据到该存储器为其他微引擎读取,便笺式存储器27连接到总线34。
处理器核心20包括以5阶段管理实施在单个周期内完成一个或二个操作数的单个循环移位的RISU核心50,并提供乘法支持及32位滚动移位支持。此RISC核心50是标准的Strong ArmR结构,但为性能的原因以5阶段管线实现。
处理器核心20还包括16千字节指令高速缓存52,8千字节数据高缓存54和预取流缓冲器56。核心处理器20与存储器写及取指令并行地完成算术运算。核心处理器20通过ARM定义的ASB总线与其他功能单元接口,ASB总线是32位双向总线32。
参考图3,示例性的微引擎22f包括一个含有存储微程序的RAM的控制存储70。微程序可由核心处理器20加载。微引擎22f还包括控制器逻辑72。控制器逻辑包括指令解码器73和程序计数器(PC)单元72a-72d。这4个程序计数器72a-72d保持在硬件中。微引擎22f还包括上下文事件交换逻辑(ContextEvent Swithing Logic)74。上下文事件逻辑74从每个共享资源,如SRAM26a,SDRAM26b或控制器核心20,控制和状态寄存器等,接收消息(如SEQ-#-EVENT_RESPONSE;FBI-EVENT-RESPONSE;SRAM-EVENT-RESPONSE;SDRAM-EVENT-RESPONSE;和ASB-EVENT-RESPONSE)。这些消息提供有关被请求的功能是否已完成的,。信箱线程请求的功能是否已完成并已发完成信号,线程需要等待完成信号,且如果该线程能够操作,则将其放入右用线程表中(未示出)。微引擎22f能是有最多可用线程,如4个。
除了对执行的线程是局部的事件信号外,微引擎22利用全局的发信号状态。执行的线程能用发信号状态将一个信号状态广播到所有的微引擎22。接收请求可用(Refust Available)信号,在微引擎中的任何或所有线程能根据这些信号状态转移。这里信号状态能被用于确定一个资源的可用性,或资源是否准备服务。
上下文事件逻辑74具有对4个线程的判优。在一个实施例中,判优是一个循环机制。也能用其他技术,包括优先级排队或加数的公平排队。微引擎22f还包括执行框(EBOX)数据通道76,它包括算术逻辑单元76a和通用寄存器组76b。算术逻辑单元76a完成算术逻辑功能及功能。算术逻辑单元包括由下面描述的指令使用的条件码的位。寄存器组76b是有相当大数目的通用寄存器,它们如下述那样分窗,使得可相对及绝对编址。微引擎22f还包括写传输寄存器堆线78和读传输寄存器堆线80。这些寄存器也分窗,使得它们相对和绝对可编址。写传输寄存器堆线78是写到资源的数据的放置处。类似地,读寄存器堆线80用于双共享资源来的返回数据。数据到达之后或同时,从相应的共享资源,如SRAM控制器26a,SDRAM控制器26b或核心处理器,来的事伯被送到上下文事件判优器74,它随之提醒线程,该数据已就绪或已被发出。传输寄存78和80均通过数据通道连接到执行框(EBOX)76。
参考图4,微引擎通道保持5阶段微一管线82。此管线包括查找微指令字82a,形成寄存器文件地址82b,从寄存器文件82c读操作数,ALU。移位或比较操作82d,和结果写回到寄存储82e。借助一个写回数据旁路进入ALU/移位单元,并借助假设寄存器作为寄存器文件(而非RAM)实现,微引擎能实现同时的文件读和写,这是全隐去了写操作。
在微引擎22a-22f中支持的指令组支持条件转移。当转移的决定是由以前的微控制指令设置的条件码的结果时,出现最坏情况的条件转移等待时间(不包括跳),等待时间示于下面表1中:
表1
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
----------------------+----+----+----+----+----+----+----+----+
微存储查找 | n1 | cb | n2 | XX | b1 | b2 | b3 | b4 |
寄存器地址生成 | | n1 | cb | XX | XX | b1 | b2 | b3 |
寄存器文件查找 | | | n1 | cb | XX | XX | b1 | b2 |
ALU/shifter/cc | | | | n1 | cb | XX | XX | b1 |
写回 | | | m2 | | n1 | cb | XX | XX |
其中nx是预转移微字(n1置位条件码)
cb是条件转移
bx是转移后的微码
XX是放弃的微码
如表1所示,直到周期4的n1条件码被设置,并作出转移决定(在此情况导致在周期5查找转移路径),微引擎22f招致个,周期的转移等待时间,因为在转移路径开始用b1充满管线以前在管线中必须放弃操作n2和n3(紧跟转移后的2个微字)。如果转移未发生,不放弃微字,执行正常继续。微引擎有若干机制来减少或消除实际的转移等待时间。
微引擎支持可选送的延迟(deferred)转移。可选的延迟是在执行转移之后而在转移生效之前,微引擎或2个微字(即转移生效在时间上“延迟”了)。,如果在转移微字之后找到有用的工作充满浪费的周期,则转移的等待时间能被隐去。在表2中示出1同期延迟转移,其中在cb之后而在b1之前允许n2:
表2
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
----------------------+----+----+----+----+----+----+----+----+
微存储查找 | n1 | cb | n2 | XX | b1 | b2 | b3 | b4 |
寄存器地址生成 | | n1 | cb | n2 | XX | b1 | b2 | b3 |
寄存器文件查找 | | | n1 | cb | n2 |XX| b1 | b2 |
ALU/shifter/cc | | | | n1 | cb | n2 | XX | b1 |
写回 | | | | | n1 | cb | n2 | XX |
在表3中示出2周期延迟转移,其中在发生到b1的转移前允许完成n2和n3。注意,只有条件码在转移前的微字上设置时才允许2周期转移延迟。
表3
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
--------------------+----+----+----+----+----+----+----+----+
微存储查找 | n1 | cb | n2 | n3 | b1 | b2 | b3 |b4 | b5 |
寄存器地址生成 | | n1 | cb | n2 | n3 | b1 | b2 | b3 | b4 |
寄存器文件查找 | | | n1 | cb | n2 | n3 | b1 | b2 | b3 |
ALU/shifter/cc | | | | n1 | cb | n2 | n3 | b1 | b2 |
写回 | | | | | n1 | cb | n2 | n3 | b1 |
微引敬也支持条件码计算。如果据此作出转移决定的条件码在转移前设置2个或更多的微字,则表4所示,因为决定在早一个周期作出,消除了1个周期的转移等待时间。
表4
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8|
--------------------+----+----+----+----+----+----+----+----+
微存储查找 | n1 | n2 | cb | XX | b1 | b2 | b3 | b4 |
寄存器地址生成 | | n1 | n2 | cb | XX | b1 | b2 | b3 |
寄存器文件查找 | | |n1 | n2 | cb | XX | b1 | b2 |
ALU/shifter/cc | | | | n1 | n2 | cb | XX | b1 |
写回 | | | | | n1 | n2 | cb | XX |
在此例中,n1设置条件码而n2不设置条件码。因此,转移决定能在周期4(而不是周期5)作出,消除了1周期的转移等待时间。在表5的例子中,1周期转移延迟和早设置条件码结合起来,完全隐去了转移等待时间。即,
在1周期延迟转移前2个周期设置条件码(cc)
表5
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
---------------------+----+----+----+----+----+----+----+----+
微存储查找 | n1 | n2 | cb | n3 | b1 | b2 | b3 | b4 |
寄存器地址生成 | | n1 | n2 | cb | n3 | b1 | b2 | b3 |
寄存器文件查找 | | | n1 | n2 | cb | n3 | b1 | b2 |
ALU/shifter/cc | | | | n1 | n2 | cb | n3 |b1 |
写回 | | | | | n1 | n2 | cb | n3 |
在条件码不能提前设置的情况(即在转移前的微字中设置),微引擎支持转移推测,试图减少余下的1个周期的转移等待时间。借助“推测”路径或顺序路径,微引擎在确切知道路径前一个周期预取推测的路径。如果推测正确,如表6所示,消除了1周期的转移等待时间。
表6
推测转移发生/转移是发生
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
----------------------+----+----+----+----+----+----+----+----+
微存储查找 | n1 | cb | n1 |b1 | b2 | b3 | b4 | b5 |
寄存器地址生成 | | n1 | cb | XX | b1 |b2 | b3 | b4 |
寄存器文件查找 | | | n1 | cb | XX | b1 | b2 | b3 |
ALU/shifter/cc | | | | n1 | cb | XX | b1 | b2 |
写回 | | | | | n1 | cb | XX | b1 |
如果微码推测转移发生不正确,如表7所示,微引擎仍然只浪费1个周期。
表7
推测转移发生/转移未发生
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
--------------------+----+----+----+----+----+----+----+----+
微存储查找 | n1 | cb | n1 | XX | n2 | n3 | n4 | n5 |
寄存器地址生成 | | n1 | cb | n1 | XX | n2 | n3 | n4 |
寄存器文件查找 | | | n1 | cb | n1 | XX | n2 | n3 |
ALU/shifter/cc | | | | n1 | cb |n1 | XX | n2 |
写回 | | | | | n1 | cb | n1 | XX |
但是当微码推测转移未发生时,等待时间的损失不同地分布。对推测转移未发生/转移未发生的情况,如表8所示没有浪费的周期。
表8
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
----------------------+----+----+----+----+----+----+----+----+
微存储查找 | n1 | cb | n1 | n2 | n3 | n4 | n5 | n6 |
寄存器地址生成 | | n1 | cb | n1 | n2 | n3 | n4 | n5 |
寄存器文件查找 | | | n1 | cb | n1 | n2 | n1 | b4|
ALU/shifter/cc | | | | n1 | cb | n1 | n2 | n3 |
写回 | | | | | n1 | cb | n1 | n2 |
然而,对推测转移未发生/转移是发生的情况,如表9所示有2个周期浪费。
表9
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
----------------------+----+----+----+----+----+----+----+----+
微存储查找 | n1 | cb | n1 | XX | b1 | b2 | b3 | b4 |
寄存器地址生成 | | n1 | cb | XX | XX | b1 | b2 | b3 |
寄存器文件查找 | | | n1 | cb | XX | XX | b1 | b2 |
ALU/shifter/cc | | | | n1 | cb | XX | XX | b1 |
写回 | | | | | n1 | cb | XX | XX |
微引擎结合转移推测和1周期转移延迟来进一步改善结果。对于推测转移发生并带1周期延迟;转移/转移是发生的情况如图10所示。
表10
| 1 | 2 | 3 | 4 | 5|6 | 7 | 8 |
--------------------+----+----+----+----+----+----+----+----+
微存储查找 | n1 | cb | n2 | b1 | b2 | b3 | b4 | b5 |
寄存器地址生成 | | n1 | cb | n2 | b1 | b2 | b3 | b4 |
寄存器文件查找 | | | n1 | cb | n2 | b1 | b2 | b3 |
ALU/shifter/cc | | | | n1 | cb | n2 | b1 | b2 |
写回 | | | | | n1 | cb | n2 | b1 |
在上述情况由于n2并由于正确推测了转移方向,隐去了2周期的转移等待时间。
如果微码推测不正确,如表11所示仍然有1周期的转移等待时间(推测转移发生带1周期延迟转移/转移未发生)。
表11
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
--------------------+----+----+----+----+----+----+----+----+
微存储查找 | n1 | cb | n2 | XX | n3 | n4 | n5 | n6 | n7 |
寄存器地址生成 | | n1 | cb | n2 | XX | n3 | n4 | n5 | n6 |
寄存器文件查找 | | | n1 | cb | n2 | XX | n3 | n4 | n5 |
ALU/shifter/cc | | | | n1 | cb | n2 | XX | n3 | n4 |
写回 | | | | | n1 | cb | n2 | XX | n3 |
如果微码正确地推测转移未发生,则管线顺序地流入正常未受扰动情况。如果微码不正确地推测转移未发生,如表12引所示微引擎经受1周期没有结果的执行。
表12
推测转移未发生/转移是发生
| 1 | 2 | 3 | 4|5 | 6 | 7 | 8 | 9 |
--------------------+----+----+----+----+----+----+----+----+
微存储查找 | n1 | cb | n2 | XX | b1 | b2 | b3 | b4 | b5 |
寄存器地址生成 | | n1 | cb | n2 | XX | b1 | b2 | b3 | b4 |
寄存器文件查找 | | | n1 | cb | n2 | XX | b1 | b2 | b3 |
ALU/shifter/cc | | | | n1 | cb | n2 | XX | b1 | b2 |
写回 | | | | | n1 | cb | n2 | XX | b1 |
其中nx是预转移微字(n1设置条件码)
cb是条件转移
bx是转移后微字
XX是放弃的微码
在跳转指令的情况,招致3个额外周期的等待时间,因为在路跳转在ALU阶段的周期结束以前转移地址未知(表13)
表13
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
--------------------+----+----+----+----+----+----+----+----+
微存储查找 | n1 | jp | XX | XX |XX | j1 | j2 | j3 | j4 |
寄存器地址生成 | | n1 | jp | XX | XX | XX | j1 | j2 | j3 |
寄存器文件查找 | | | n1 | jp | XX | XX | XX | j1 | j2 |
ALU/shifter/cc | | | | n1 |jp | XX | XX | XX | j1 |
写回 | | | | | n1 |jp | XX | XX | XX |
按照在转移前的微字上设置的ALU条件码操作的条件转移码选择0,1或2或3周期的转移长方式。条件码在按期操作的条件转移能选择0或1周期转移延迟方式以前,设置2个或更多的微字。所有期货转移(包括上下文重新判优)能选择0或1周期的转移延迟方式。结构能设计成使得在以前的转移,跳转或上下文判优微字的转移延迟窗之中的一个上下文判优微字为非法操作。即,在某些实施例中,在管线中转移变换期间不允许发生上下文切换,因为保存老的上下文PC是过分的复杂。结构也能设计成使得在以前的转移,跳转或上下文判优微字的转移延迟窗之中的一个上下文判优微字为非法操作,以避免复杂的和可能未能预见的转移行为,
参考图5A,示出转移指定的一般格式。
转移指令
BR BR<O,BR=O BR<O。BR i=O BR=COUT,BR>O Br!=COUT,BR>O
一组转移指令是无条件转移B根据ALU条件码转移到指定标号的指令。示例性的ALU条件码是符号,零,和进位(Carryout-cout)。
格式:br[label#],optional-token(label-标号)
br=o[label#],optional-token可先标记
br!=o[label#],optional-token
br>[label#],optional-token
br>o[label#],optional-token
br<o[label#],optional-token
br<=o[label#],optional-token
br=Cout[label#],optional-token
br!=Cout[label#],optional-token
参数labet#是对应于指令地址的符号标号。转移指令的分类可有列optional-token可选标记:延迟1条指令,延迟2条指令,和延迟3条指令,这些optional-token使得处理器要完成转移操作之前执行条,2条或3条指令,设置条件码的ALU操作在转移指令前可以出现若干指令。延迟2和延迟3不与下述的转移推测一起使用。
第四个optional-token是推测转移(guess-branch)标记,它引起处理器预取对“转移发生”条件的指令,而作下一条顺序指令。在转移指令前立即发生设置条件码的ALU操作。
BR-BCLR;BR-BSET
当指定位被置位或清除时第二组转移指令是转移到指定标号。这些指令在处理器的状态寄存器中设置条件码。指令格式是
br-bclr[reg,bit-positior,label#],
optional-token;br-bset[reg,bit-positior,label#],
optional-token
操作数字段RegA保存操作数的与上下文相关的传输寄存器或通用寄存器。Bit-positionA是指定在一长字中位的位置的数。Bito是最低位。有效的bit-positson的值是0到31。Label#是对应目标指令的地址的符号标号。
转移指令组也具有,optional-token;如上所述为延迟1指令,延迟2指令及延迟3指令转移推测。
例:br-bcln[reg,bit-position,label#],如果位被清除,延迟〔1〕转移。
BR=BYTE;Br!=BYTE
第三组转移指令是那样的指令,如果长字中的指定字节匹配byte-compare-Valne(字节—比较—值),引起处理器转移到指定标号处的指令。By=byte指令对“转移发生”条件预取指令而不预取下一条顺序指令。Br!=byte指令预取下一条顺序指令。这些指令设置条件码。
格式:
br=byte[reg,byte-spec,byte,compare-value,label#],opetional-token
br!=byte[reg,byte-spec,byte,compare-value,label#],opetional-token
Reg是存放操作数的与上下文相关的传输寄存器或通用寄存器。Byte-specNumber是指定与byte-compart-value比较的在寄存器中一字节的数。有效的byte spec值是0到3,0值对照最右边的字节。byte-compart-value是用于比较的参数。在此实施中,有效的byte-compart-value是0到255。Label#是对应于指令地址的符号。
此组转移指令也有optional-token;延迟1指令,延迟2指令,延迟3指令,和转移推测。延迟2和3只对Br!=BYTE使用。
例:br!=byte[reg,byte-spec,byte-compart-value,labe#],defer[3]
此微字指令提供将寄存器操作数的对齐字节与一即时指定字节值比较的技术,其中byte-spec表示比较的对齐字节(0是最右字节,3是最左字节)。ALU条件码通过从指定的寄存器字节减去指定的字节值而设置。如果值匹配,发生指定的转移。有3个周期转移等待时间与此指令有关,因此为了用有用的工作充满等待时间,允许0,1,2,3的转移延迟。该寄存器是A或B存储区的寄存器。
CTX-ARB
参考图5B,上下文交换指令CTX-ARB交换出在指定微引擎中当前运行的上下文到存储器,让其化上下文在那个微引擎中执行。当指定的信号激活时,上下文交换指令CTX-ARB还唤醒被交换出的上下文。上下文交换指令的格式是
ctx-arb[parameter],optional-token
“parameter—参数”字段能具有若干值之一。如果该参考数指定为“sramSwap”,上下文交换指令交换出当前的上下文并当接收到线程的SRAM信号时唤醒它。如果该参数指定为“sram swap”上下文交换指令交换出当前的上下文并当接收到线程的SDRAM信号时唤醒它。该参数也能指定为“FBI”它交换出当前的上下文并当接收到线程的FBI信号时唤醒它。FBI信号指出已完成FBICSR,Scratchpad,TFIFO,或RFIFO操作。
参数也能指定为“seg-num1-charge/seg-num2-change”,它交换出当前的上下文并当顺序数的值改变时唤醒它。参数也能指定为“inter-thread”,它交换出当前的上下文并当收到线程的内线程(Cinterthread)信号时唤醒它,或指定为“Voluntary”,如果另外线程准备运行时交换出当前的上下文,原则不交换。如果线程交换出,在某个后续上下文判优点它自动地再能运行。参数能是“anto-push”,它交换出当前上下文并当SRAM传输读寄存器数据被FBUS接口自动压入时唤醒它,参数或是“stert-receive”,它交换出当前上下文,并当在receive FIFO中的新的包数据对此线程可用处理时唤醒它。
该参数也能是“kill”它防止当前的上下文或线程,在对该线程的适当的使能位在CTX-ENABLES寄存器中被置位以前再次执行,参数能是“pci”,它交换出当前上下文并当PCI单元DMA传输已完成的信号时唤醒它。
上下文交换指令CTX-ARB能具有下述optiohal-token,延迟1规定在此调回后上下文被交换前执行一条指令。
BR=CTX,BR!=CTX
参考图5C,示出上下文转移指令BR=CTX,Br!=CTX。上下文转移指令引起处理器,如微引擎22f,根据当前执行的上下文是否为指定的上下文数而转移指令是从转移掩码字段在等于“8”或“9”时确定。上下文转移指定能具有下述格式,
格式:br=ctx[ctx,label#],optional-token
br!=ctx[ctx,label#],optional-token
Label#是对应于指令地址的符号标号。Ctx一上下文数是一个上下文(线程)的数。在此例中,有效的Ctx值是0,1,2,3。
此指令有optional-token“defer one”(“延迟1”)指令,它导致处理器在完成转移操作前执行该指令后的指令。
BR-INP-STATE
再参考图5A,另外转移指令类在指定的状态名的状态被设置成1时或0并指出当前的处理状态。这对所有微引擎都可用。在图6中示出使用br-mask字段的格式被用于规定转移。对转移掩码=15,使用扩展的字段指定如下所列的各种信号和状态信号。
格式:br-inp-state[state-name,label#],optional-token
Label#是对应于指令地址的符号标号。State-name是状态名,如果rec-reg-avail被设置,它指出RCV-REQ FIFO具有空间可用于另外的接收请求。如果Push-protect被设置,它指出FBI单元当前正在写到SRAM传喻寄存器。此指令也具有optional-token“延迟1”,它在完成转移操作前执行此指令后的指令。
BR-!SIGNAL
另一类转移指令使得如果指定信号未认定时引起处理器转移。如果信号认定,指令清除此信号并不发生转移。在最后一个长字被写到传统寄存器的两个周期之后,SRAM和SDRAM信号被送给微引擎。在信号后一个周期,倒数第二长字被写入。当该信号被提交时,所有其他长字是有效的。程序员用此指令适当地选择读传输寄存器的时间,保证读出适当的数据。
格式:br-signal[stignal-name,label#],optional-token
Label#是对应于指令地址的符号标号。Signal-name能是sram,sdram,fbi,ihter-thread,auto-push,start-receive,seg-num1,seg-num2。
此转移指令组具有下列optional-token:defer one(延迟1)指令,defertwo(延迟令2)指令,和defer three(延迟令3)指令。这些optional token引起处理器在此指令后而在完成转移操作之前执行1,2或3条指令。设置条件码的ALU操作在转移指令前可以存在若干指令,defer two和deferthree不能与转移推测一起使用。
第4个optional token是guess-branch(推测—转移)预取。推测转移预取标记预对“转移发生”的指令而不是下一条顺序指令。此标记与延迟1指令一起用以改善性能。
例:xfer-order $ xfero $ xfer1$xfer2$xfer3
sram[read,$xfer0,op1,0,2],sig-done
wai t#:
br_!signal[sram,wait#],guess_branch
nop;delay 1 cycle before reading $xfer0
alu[gpr0,0,b,$xfer0];val id data is written to gpr0
alu[gpr1,0,b,$xfer1];valid data is written to gpr0
self#:
br[self#]
参考图6,存在的两个寄存器空间是局部可访问寄存器,和由所有微引擎可访问的全部可访问寄存器。通用寄存器(GPR)作为两个分别的存储区实施(A存储区和B存储区),它们的地址逐字交替,使A存储区寄存器具有lsb=0,而B存储区寄存器具有lsb=1(lsb是最低位)。每个存储区能对其存储区中的两个不同字完成同时的读和写。
整个存储区A和B,寄存器组76b能组织成32个寄存器的4个窗76b0-76b3,它们对每个线程相对可编址。同时,thread(线程)-0在77a(寄存器0)处找到其寄存器0,thread-1在77b(寄存器32)处找到其寄存器0,thread-2在77c(寄存器64)处找到其寄存器0,thread-3在77d(寄存器96)处找到其寄存器0。支持相对编址,使得多个线程能使用完全相同的控制存储及位置却访问不同的寄存器窗并完成不同的功能。使用寄存器窗编址和存储区编址虽然在微引擎22f中只使用双口RAM却提供必要的读带宽。
这些分窗的寄存器从上下文切换到上下文切换不需要保存数据,所以消除了上下文交换文件或堆线的正常压入和弹出操作。这里的上下文交换对于从一个上下文改变到另一个具有。周期开销。相对寄存器编址将寄存器存储区,在遍及整个通用寄存器组的宽度分成窗。相对编址允许相对于一个窗的起始点访问任何一个窗。在此结构中也支持绝对编址,其中通过提供寄存器的准确地址,由任何一个线程能访问任何一中的个绝对寄存器。
通用寄存器78的编址根据微字的格式能以2种方式出现。两种方式是绝对相对方式。在绝对方式中,寄存器地址的编址直接以7位源字段(a6-a0或b6-b0)指定,如图14所示:
表14
7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+
AGPR: | a6 | 0 | a5 | a4 | a3 | a2 | a1 | a0 | a6=0
B GPR: | b6 | 1 | b5 | b4 | b3 | b2 | b1 | b0 | b6=0
SRAM/ASB:| a6 | a5| a4 | 0 | a3 | a2 | a1 | a0 | a6=1,a5=0,a4=0 SDRAM:
| a6 | a5 | a4 | 0 | a3 | a2 | a1 | a0| a6=1,a5=0,a4=1
寄存器地址直接以8位目标字段(d7-d0)指定,见表15。
表15
7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+
A GPR: | d7 | d6 | d5 | d4 | d3 | d2 | d1 | d0 | d7=0,d6=0
B GPR: | d7 | d6 | d5 | d4 | d3 | d2 | d1 | d0 | d7=0,d6=1
SRAM/ASB:| d7 | d6 | d5 | d4 | d3 |d2 | d1 | d0 | d7=1,d6=0,d5=0
SDRAM: | d7 | d6 | d5 | d4 | d3 | d2 | d1 | d0 | d7=1,d6=0,d5=1
如果<a6:a5>=1,1,<b6:b5>=1,1,或<d7:d6>=1,1,则较低位被解释为与上下文相关的地址字段(如下所述)。当在A、B绝对字段中指定非相对的A或B源地址,只有SRAM/SDRAM设备具有有效的地址空间;但是因为此限止不施加到目标字段,写SRAM/SDRAM仍然使用全地址空间。
在相对方式中,编址一指定的地址是在上下文空间偏移量,如由5位源字段(a4-a0或b4-b0)确定,表16:
表16
7 6 5 4 3 2 1 0
+…+…+…+…+…+…+…+…+
A GPR: | a4 | 0 | 上下文 | a3 | a2 | a1 | a0 | a4=0
B GPR: | b4 | 1 | 上下文 | b3 | b2 | b1 | b0 | b4=0
SRAM/ASB:| ab4 | 0 | ab3 | 上下文 | b2 | b1 | ab0 | ab4=1,ab3=0
SDRAM: | ab4 | 0 | ab3 | 上下文 | b2 | b1 | ab0 | ab4=1,ab3=1
或由6位目标字段(d5-d0)确定,表17
表17
7 6 5 4 3 2 1 0
+…+…+…+…+…+…+…+…+
A GPR: | d5|d4 |上下文| d3 | d2 | d1 | d0 | d5=0,d4=0
B GPR: | d5 | d4 | 上下文 | d3 | d2 | d1 | d0 | d5=0,d4=1
SRAM/ASB: | d5 | d4 | d3 | 上下文 | d2 | d1 | d0 | d5=1,d4=0,d3=0
SDRAM: | d5 | d4 | d3 | 上下文 | d2 | d1 | d0 | d5=1,d4=0,d3=1
如果<d5:d4>=1,1,则目标地址不选址一个有效寄存器,因而不写日月标操作板。
其他实施倒在下面权利要求的范围之内。
Claims (21)
1、一种计算机指令,其特征在于,包括
转移指令,所述转移指令根据任何一指定值是真或假引起指令流执行的转移并且包括一个标记,所述标记规定在所述指令后并在完成转移操作前执行指令流中指令的数目。
2、如权利要求1所述的指令,其特征在于,
所述转移指令包括规定转移推测操作的第二标记。
3、如权利要求1所述的指令,其特征在于,
所述可选的标记包括defer-i,它引起处理器在完成转移操作前执行转移指令后的第ith条指令。
4、如权利要求1的所述指令,其特征在于,
所述可选的标记能规定在完成转移操作前,执行在所述转移指令后的1,2或3条指令。
5、如权利要求1的所述指令,其特征在于,
所述指令具有如下格式:
br[label#],optional-token
其中br是转移操作,label#是转移到的地址的符号表示,optional-token规定在br转移指令指定的转移操作完成前执行的指令数目。
6、如权利要求1所述的指令,其特征在于,
由程序员或汇编程序指定一条所述可选的标记,以便可变周期能延迟转移。
7、如权利要求1所述的指令,其特征在于,
指定可选标记中的一个,以便帮助汇编程序产生更有效的码。
8、如权利要求1所述的指令,其特征在于,
所述的转移指令是无条件转移或根据ALU条件码转移到指定标号处的指令。
9、如权利要求1所述的指令,其特征在于,
当指定位被置位或清除时,所述指令是到指定标号的转移指令。
10、如权利要求1所述的指令,其特征在于,
如果一长字中的指定字节匹配或不匹配字节-比较-值,则所述的转移指令是引起处理器转移到指定标号的指令的转移指令。
11、如权利要求1所述的指令,其特征在于,
所述的转移指令是引起处理器根据当前的上下文是否为所述转移指令中的指定上下文,转移到指定标号的转移指令。
12、如权利要求1所述的指令,其特征在于,
如果指令状态名的状态是一选定值,则所述的转移指令是引起处理器转移的转移指令。
13、如权利要求1所述的指令,其特征在于,
如果一指定信号不被认定,则所述的转移指令是引起处理器转移的转移指令。
14、如权利要求1所述的指令,其特征在于,
所述的转移指令还包括一附加标记,即推测-转移标记,它使得处理器预取“转移发生”情况的指令,而不是下一条顺序的指令。
15、一种计算机程序,其特征在于,包括
使得处理器执行计算机指令完成一功能的多条指令,所述程序具有在包括不同的延迟转移标记的不同程序部分中的第二多个转移指令,其中转移标记规定在完成由第二多个转移指定的转移操作之前执行的指令数目。
16、如权利要求15所述的程序,其特征在于,
至少一条转移指令还包括另外的标记,即推测转移标记,它使得处理器预取“转移发生”情况的指令,而不是下一条顺序的指令。
17、一种操作处理器的方法,其特征在于,包括
执行转移指令,它根据任一指定值是真或假引起指令流的转移,以及
根据计算指定完成转移操作以前执行的指令数的标记,延迟执行所述转移指令的转移操作。
18、如权利要求17所述的方法,其特征在于,还包括
计算指定转移推测操作第二标记,它使得处理器预取“转移发生”情况的指令,而不是下一条顺序的指令。
19、如权利要求17所述的方法,其特征在于,
由程序员选择所述的可选标记。
20、如权利要求17所述的方法,其特征在于,
由程序员或汇编程序指定所述的可选标记,以便可变周期能延迟转移。
21、如权利要求17所述的方法,其特征在于,
指定一个可选标记,以便帮助汇编程序产生更有效的程序码。
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