CN100474236C - 多线程并行处理器及其维持线程执行的方法 - Google Patents
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Abstract
本发明描述一个并行的基于硬件的多线程处理器。该处理器包括一个协调***功能的通用处理器和支持多个硬件线程或上下文(THREAD_3,…THREAD_0)的多个微引擎。该处理器保持执行线程(THREAD_3,…THREAD_0)。该执行线程(THREAD_3,…THREAD_0)访问组织成多个可相对编址的寄存器窗的寄存器组,它们对每个线程(THREAD_3,…THREAD_0)可相对编址。
Description
背景技术
本发明涉及计算机处理器。
在计算过程中并行处理是并发事件信息处理的有效方式。与顺序处理相反,并行处理要求在计算机中同时执行许多程序。在并行处理器的范围内,并行化意味着在同一时刻做多于一件事情。不象在单个站上顺序地完成所有任务的串行范例,也不象在专门的站完成诸任务的管线(流水线)机器,对于并行处理提供多个站,每个能完成所有任务。即,通常所有的或多个站同时地并独立地对一个问题的相同或共同的部分工作。某些问题适合于应用并行处理解决。
附图概述
图1是使用基于硬件的多线程处理器的通信***的方框图。
图2是图1的基于硬件的多线程处理器的详细的方框图。
图3是在图1和图2的基于硬件的多线程处理器中使用的微引擎功能单元的方框图。
图4是在图3的微引擎中管线的方框图。
图5是示出通用寄存器地址安排的方框图。
描述
参考图1,通信***10包括一个并行的、基于硬件的多线程处理器12。基于硬件的多线程处理器12连结到如PCI总线14之类的总线、存储器***16和第二总线18。对于能够分解成并行子任务或功能的任务,***10特别有用。具体说来,基于硬件的多线程处理器12对于面向带宽而非面向等待时间的任务是有用的。基于硬件的多线程处理器12具有多个微引擎22,每个带有多个能同时激活并独立对一个任务工作的硬件控制的线程。
基于硬件的多线程处理器12还包括一个中央处理器20,它帮助加载用于基于硬件的多线程处理器12的其他资源的微码控制,并完成其他通用计算机类型的功能,如处理协议,异常,在诸如边界条件中微引擎将包停下以作更详细处理的情况下对包处理的额外支持。在一个实施例中,处理器20是基于Strong (Arm是英国ARM有限公司的商标)的结构。通用微处理器20具有操作***。通过此操作***,处理器20能调用功能对微引擎22a—22f操作。处理器20能使用任何支持的操作***,最好是实时操作***。对于作为StrongArm结构实现的核心处理器,可以使用如实时,VXWorks和□CUS那样可在因特网上得到的免费软件操作***。
基于硬件的多线程处理器12还包括多个功能微引擎22a—22f。功能微引擎(微引擎)22a-22f中每一个包含多个硬件的程序计数器和与这些计数器相关的状态。实际上,对应多个线程组能在每个微引擎22a—22f上同时激活,虽然在任何时刻只有一个实际上在操作。
在一个实施例中,示出6个微引擎22a—22f。每个微引擎22a—22f具有处理4个硬件线程的能力。6个微引擎22a—22f在共享资源下操作,包括存储器***16和总线接口24和28。存储器***16包括一个同步动态随机存取存储器(SDRAM)控制器26a和静态随机存取存储器(SRAM)控制器26b。SDRAM存储器16a和SDRAM控制器26a通常用于处理大量数据,如处理从网络包来的网络有效负载。SRAM控制器26b和SRAM存储器16b用在对低等待时间,快速访问任务的网络实施中,如对核心处理器20的访问查找表,访问存储器等。
6个微引擎22a—22g根据数据的特征访问SDRAM 16a或SRAM16b。低等待时间,低带宽数据存在SRAM并从中取出,而等待时间不重要的较高带宽的数据存入SDRAM,并从中取出。微引擎22a—22f能执行对SDRAM控制器26a或SRAM控制器16b的存储器引用指令。
硬件多线程的优点能通过SRAM或SDRAM存储器的访问解释。作为例子,来自微引擎的Thread_0(线程_0)所请求的SRAM访问引起SRAM控制器26b启动对SRAM存储器16b的访问。SRAM控制器控制对SRAM总线的判优,访问SRAM16b,从SRAM 16b取出数据,并将数据返回到请求的微引擎22a—22b。在SRAM访问过程中,如果微引擎,如22a,只能操作单个线程,该微引擎在数据从SRAM返回以前休眠。通过在每个微引擎22a—22f中应用硬件上下文(context)交换,使得其他带着唯一程序计数器的其他上下文能在同一微引擎中执行。因此在第一线程,如Thread_0,等待读数据返回时,另一线程,如Thread_1能工作。在执行中Thread_1可访问SDRAM存储器16a。当Thread_1对SDRAM单元操作,且Thread_0对SRAM单元操作的同时,一个新的线程,如Thread_2,现在能在微引擎22a中操作。Thread_2能操作一定时间,直到它需要访问存储器,或完成某些如作出对总线接口访问那样另外的长等待时间操作。因此,处理器12能同时具有总线操作、SRAM操作和SDRAM操作,所有均由一个微引擎22a操作或完成,并且能具有一个以上可用线程以在数据通道中处理更多的工作。
硬件上下文交换也同步任务的完成。例如,两个线程可以选中同一个共享资源,如SRAM。这些分别的功能单元的每一个,如FBUS接口28、SRAM控制器26a和SDRAM控制器26b,在它们完成从一个微引擎线程上下文来的请求任务时,回报一个标志,通知一个操作的完成。当微引擎接收到此标志时,该微引擎能确定打开哪个线程。
对基于硬件的多线程处理器12的一个应用例子是作为网络处理器。作为网络处理器,基于硬件的多线程处理器12接口到如媒体访问控制设备那样网络设备,如10/100 BaseT Octal MAC 13a或Gigabit Ethernet(千兆以太网)设备13b。通常,作为网络处理器,基于硬件的多线程处理器12能接口到接收/发送大量数据的任意类型的通信设备或接口设备。在网络应用中工作的通信***10能从设备13a,13b接收多个网络包,并以并行方式处理那些包。用基于硬件的多线程处理器12能分别地处理每个网络包。
使用处理器12的另一个例子是用于后脚本(postscript)处理器的打印机引擎作为对存储子***,即RAID盘存储器的处理器。另一个使用是匹配引擎。在例如安全行业中,电子商务的兴起需要使用电子匹配引擎匹配买方和卖方之间的订单。这些和其他并行类型的任务能在***10上完成。
处理器12包括连结处理器到第2总线18的总线接口28。在一个实施例中,总线接口28将处理器12连结到所谓FBUS 18(FIFO总线)。FBUS接口28负责控制并连结处理器12到FBUS18。FBUS18是64位宽的FIFO总线,用于连结到媒体访问控制器(MAC)设备。
处理器12包括一个第二接口,如PCI总线接口24,它将驻留在PCI14总线上的其他***部件连接到处理器12。PCI总线接口24提供高速数据通道24a到存储器16,如SDRAM存储器16a。经过该通道,数据能借助直接存储器访问(DMA)传输,从SDRAM16a穿过PCI总线14快速移动。基于硬件的多线程处理器12支持图像传输。基于硬件的多线程处理器12能使用多个DMA通道,所以如果DMA传输的一个目标忙,另一个DMA通道能接管PCI总线以将信息提交到另一个目标,以保持高的处理器12的效率。此外,PCI总线接口24支持目标操作和主操作。目标操作是这样一种操作,其中在总线14上的从属设备通过读和写访问SDRAM,而读和写是从属于目标操作来服务的。在主要操作中,处理器核心20直接发送数据到PCI接口24或从中接收数据。
每个功能单元连结一个或多个内部总线。如下所述,内部总线是双32位总线(即一个总线用于读,一个总线用于写)。基于硬件的多线程处理器12,还构造成使得处理器12中内部总线的带宽之和超过连结到处理器12的外部总线的带宽。处理器12包括一个内部核心处理器总线32,如ASB总线(先进***总线),它将处理器核心20连结到存储控制器26a,26c,并连结到如下所述的ASB翻译器30。ASB总线是与Strong Arm处理器核心一起使用的AMBA总线的子集。处理器12还包括一个专用总线34,将微引擎单元连结到SRAM控制器26b、ASB翻译器30和FBUS接口28。存储器总线38将存储控制器26a,26b连接到总线接口24和28以及包括用于自引导等操作的闪存ROM 16c的存储器***16。
参考图2,每个微引擎22a—22f包括一个判优器,它检查标志以确定操作可用的线程。从任何一个微引擎22a—22f来的任何一个线程能访问SDRAM控制器26a,SRAM控制器26b,或FBUS接口28。存储控制器26a,26b中每一个包括多个队列,以存储未完成的存储器引用请求。此队列或者保持存储器引用的次序,或者安排存储器引用以优化存储器带宽。例如,如果Thread_0不依赖于Thread_1或与其没有关系,线程1和0没有理由不能不按顺序地完成它们对SRAM单元的存储器引用。微引擎22a—22f对存储控制器26a和26b发出存储器引用请求。微引擎22a—22f将足够的存储器引用操作充满存储器子***26a和26b,使得存储器子***26a和26b成为处理器12操作的瓶颈。
如果存储器子***16用本质上独立的存储器请求充满,处理器12能够完成存储器引用排序。存储器调用排序改善了可得到的存储器带宽。如下所述,存储器调用排序减少了访问SRAM发生的停顿时间或泡沫。随着对SRAM的存储器引用,将信号线的电流方向在读和写之间切换产生一个泡沫或停顿时间,等待在SRAM16b与SRAM控制器26b连结导线上的电流稳定下来。
即,驱动总线电流的驱动器在改变状态以前需要稳定下来。重复的读周期后面跟一个写能降低峰值带宽。存储器引用排序允许处理器12组织对存储器的引用,使得一长串读能跟一长串的写。这能用于使在管线中停顿时间最小,从而更有效地达到接近最大可用的带宽。引用排列帮助维持并行的硬件上下文线程。在SDRAM中,引用排序允许在一个存储区与另一存储区之间隐藏预充电。具体说来,如果存储***16b组织成奇数存储区和偶数存储区,当处理器在奇数存储区上操作的同时,存储控制器能开始预充电偶数存储区。如果存储器引用在奇数和偶数存储区之间交替,预充电是可能的。通过将存储器引用排序为对相反存储区的交替访问,处理器12改善了SDRAM的带宽。此外,也可使用其他的优化。例如,将可以合并的操作在存储器访问前合并的合并优化;通过检查地址,存储器的已打开的页面不再重新打开的打开页面优化;如下所述的链接;和刷新机构都可以使用。
FBUS接口28支持用于每个MAC设备支持的端口的发送和接收标志,以及指示何时需要服务的中断标志。FBUS接口28还包括一个控制器28a,它完成从FBUS18进入的包的报头处理。控制器28a提取包的报头并完成在SRAM中的一个微程序可编程的源/目标/协议的散列查找(用于地址平滑)。如果散列不能成功地解决,该包的首部被送到处理器核心20作另外的处理。FBUS接口28支持下列内部数据事务:
FBUS单元 (共享总线SRAM) 到/从微引擎。
FBUS单元 (经过专用总线) 从SDRAM单元写。
FBUS单元 (经过Mbus) 读至SDRAM。
FBUS18是标准的工业总线并包括一个数据总线(如64位宽)和用于地址和读/写控制的边带控制。FBUS接口28提供使用一系列输入和输出FIFO 29a—29b输入大量数据的能力。从FIFO 29a—29b,微引擎22a—22f从一个接收FIFO取出数据、或命令SDRAM控制器26a将数据从其送到FBUS接口28,在接收FIFO中数据从总线18的设备来。借助直接存储器访问,数据能经过存储控制器26a送到SDRAM存储器16a。类似地,微引擎能将数据从SDRAM 26a移到接口28,经过FBUS接口28,移出FBUS18。
数据功能在各微引擎中分配。到SRAM26a,SDRAM26b和FBUS的连接性是通过命令请求。命令请求可以是存储器请求或FBUS总线请求。例如,一个命令请求可将数据从位于微引擎22a中的寄存器移到共享资源,如SDRAM位置,SRAM位置,闪存储器或某些MAC地址。命令发送到每个功能单元及共享资源。但是,共享资源不需要保持数据的本地缓存。而是,共享资源访问位于微引擎内部的分布数据。这使得微引擎22a—22f有对数据的本地访问,而不是仲裁总线访问和总线风险竞争。以这个特征,有0周期的停顿用于等待在微引擎22a—22f内部的数据。
连结如存储控制器26a和26b这类共享资源的数据总线,如ASB总线30、SRAM总线34和SDRAM总线38,具有足够的带宽,使得没有内部瓶颈。因此,为了避免瓶颈,处理器12有带宽要求,给每个功能单元提供至少两倍的内部总线的最大带宽。作为一个例子,SDRAM能以83MHz运行64位宽的总线。SRAM数据总线能具有分别的读和写总线,如能是以166MHz运行的32位宽读总线和以166MHz运行的32位宽写总线。本质上,那是以166MHz运行的64位,它实际是SDRAM带宽的两倍。
核心处理器20也能访问共享资源。核心处理器20具有通过总线32对SDRAM控制器26a、总线接口24和SRAM控制器26b的直接通信。然后,为了访问微引擎22a—22f以及位于任何一个微引擎22a—22f的传输寄存器,核心处理器20经过总线34上的ASB翻译器30访问微引擎22a—22f。ASB翻译器30能物理地驻留在FBUS接口28中,但逻辑上是分开的。ASB翻译器30完成FBUS微引擎传输寄存器位置和核心处理器地址(即ASB总线)之间的地址翻译,所以核心处理器20能访问属于微引擎22a—22c的寄存器。
虽然微引擎22能使用寄存器组如下所述地交换数据,还可提供便笺存储器(暂时存储器)27,以允许微引擎将数据写到存储器以外,用于其他微引擎读取。便笺存储器27连结到总线34。
处理器核心20包括以5阶段管线实现的、在单个周期完成一个操作数或二个操作数的单循环移位的RISC核心50,提供乘法支持和32位滚动移位支持。此RISC核心50是标准的Strong 结构,但为了性能的原因用5阶段管线实现。处理器核心20还包括16千字节的指令高速缓存器52和8千字节的数据高速缓存器54以及预取流缓存器56。核心处理器20与存储写和指令的读取并行地完成算术操作。核心处理器20经过ARM确定的ASB总线与其他功能单元接口。ASB总线是32位双向总线32。
微引擎:
参考图3,示出微引擎22a—22f的一个例子,如22f。微引擎包括一个控制存储70,在一个实施例中,它包括一个RAM,这里是1024个32位字。RAM存储微程序。微程序可由核心处理器20加载。微引擎22f还包括控制器逻辑72。控制器逻辑包括一个指令解码器73和程序计数器(PC)单元72a—72d。4个微程序计数器72a—72d保持在硬件中。微引擎22f还包括上下文事件切换逻辑74。上下文事件逻辑74从如SRAM26a、SDRAM26b或处理器核心20及控制和状态寄存器等那样的共享资源中的每一个接收消息(如SEQ_#_EVENT_RESPONSE;FBI_EVENT_RESPONSE;SRAM_EVENT_RESPONSE;SDRAM_EVENT_RESPONSE和ASB_EVENT_RESPONSE)。这些消息提供有关所请求的功能是否已完成的信息。根据由线程请求的功能是否已经完成并产生完成信号,该线程需要等待该完成信号,且如果该线程能操作,则该线程被放置于可用的线程列表(未图示)上。微引擎22f能具有最多例如4个可用的线程。
除了对执行线程是本地的事件信号以外,微引擎22使用全局的信令状态。一个执行线程能用信令号状态对所有微引擎22广播一个信号状态。接收请求有效信号,在微引擎中的任何和所有线程能根据这些信令状态转移。能使用这些信令状态确定一个资源的可用性或一个资源是否已准备好服务。
上下文事件逻辑74具有对4个线程的判优。在一个实施例中,判优是一个循环算法机制。可以使用其他技术,包括优先级排队或加权公平排队。微引擎22f还包括一个执行箱(框)(EBOX)数据通道76,它包括一个算术逻辑单元76a和通用寄存器组76b。算术逻辑单元76a完成算术和逻辑功能以及移位功能。寄存器组76b具有相当大数目的通用寄存器。如在图6中将描述,在本实施例中第一存储区Bank A中有64个通用寄存器,且在第二存储区Bank B中也有64个。如将描述的,寄存器组分成窗,使得它们可被相对地和绝对地编址。
微引擎22f还包括一个写传输寄存器堆栈78和一个读传输堆栈80。这些寄存器也分窗,使得它们可相对地和绝对地编址。写传输寄存器堆栈78是写到资源去的数据位于的地方。类似的,读寄存器堆栈80是用于从共享资源返回的数据。在数据到达之后或同时,从如SRAM控制器26a、SDRAM控制器26b或核芯处理器20那样各共享资源来的一个事件信号提供给上下文事件判优器74,后者将提醒线程,数据已可用或已发出。传输寄存器存储区78和80通过数据通道连结到执行箱(EBOX)76。在一个实施例中,读传输寄存器有64个寄存器且写传输寄存器有64个寄存器。
参考图4,微引擎数据通道保持5级微管线82。此微管线包括查找微指令字82a;形成寄存器文件地址82b;从寄存器文件读出操作数82c;ALU,移位或比较操作82d;将结果写回到寄存器82e。通过提供写回数据旁路到ALU/移位单元,并通过假设寄存器作为寄存器文件(而非RAM)实现,微引擎能完成同时的寄存器文件读和写,这完全隐藏了写操作。
SDRAM接口26a将一个信号返回到请求读的微引擎,指出在读请求时是否发生奇偶校验错误。当微引擎使用任何返回数据时,该微引擎的微码负责检查SDRAM读的奇偶校验标志。在检查标志时,如果它被置位,根据它转移的动作将其清除。只有当SDRAM能够检查且SDRAM受奇偶校验保护的时候才发送奇偶校验校志。微引擎和PCI单元是得知奇偶校验错误的仅有的请求者。因此,如果处理器核心20或FIFO请求奇偶校验保持,微引擎在请求中预以协助。
参考图5,存在两个寄存器地址空间,本地可访问的寄存器,和全局可访问的寄存器,后者可由所有微引擎访问。通用寄存器(GPR)作为两个分别的存储区(A存储区和B存储区)实现,它们的地址逐字交叉,使得A存储区寄存器有lsb=0,B存储区寄存器有lsb=1(lsb是最低有效位)。每个存储区能实现对该存储区中两个不同字的同时读和写。
在存储区A和B内,寄存器组76也被组织成4个32个寄存器的窗76b0-76b3,它们可每个线程相对编址。因此,thread_0在77a找到它的寄存器0(寄存器0),thread_1在77b找到它的寄存器_0(寄存器32),thread_2在77c找到它的寄存器_0(寄存器64),而thread_3在77d找到它的寄存器0(寄存器96)。支持相对编址,使得多线程能使用完全相同的控制存储和位置,而访问不同的寄存器窗并完成不同的功能。使用寄存器窗编址和存储区编址,只要在微引擎22f中采用双口RAM就提供了需要的读带宽。
这些分窗的寄存器从上下文切换到上下文切换不需要保存数据,因而消除了上下文交换文件或堆栈的正常压入或弹出。这里的上下文切换对于从一个上下文改变为另一个具有0周期的开销。相对寄存器编址将寄存器存储区按通用寄存器组的地址宽度分成窗。相对编址允许对于窗起始点访问任何窗。在此结构中也支持绝对编址,通过提供寄存器的精确地址,任何一个绝对寄存器能被任何一个线程访问。
通用寄存器78的编址以两种方式出现,取决于微字的格式。两种方式是绝对方式和相对方式。在绝对方式中,寄存器地址的编址直接在7位源字段(a6-a0或b6-b0)中指定:
7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+
A GPR:|a6|0|a5|a4|a3|a2|a1|a0| a6=0
B GPR:|b6|1|b5|b4|b3|b2|b1|b0| b6=0
SRAM/ASB:|a6|a5|a4|0|a3|a2|a1|a0|a6=1,a5=0,a4=0
SDRAM:|a6|a5|a4|0|a3|a2|a1|a0|a6=1,a5=0,a4=1
寄存器地址直接在8位目标字段(d7-d0)中指定:
7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+
A GPR:|a6|0|a5|a4|a3|a2|a1|a0| a6=0
B GPR:|b6|1|b5|b4|b3|b2|b1|b0| b6=0
SRAM/ASB:|a6|a5|a4|0|a3|a2|a1|a0| a6=1,a5=0,a4=0
SDRAM:|a6|a5|a4|0|a3|a2|a1|a0|a6=1,a5=0,a4=1
如果<a6:a5>=1,1,<b6:b5>=1,1或<d7:d6>=1,1,则较低位解释为上下文相关的地址字段(下面描述)。当在A,B绝对字段中指定一非相对的A或B的源地址,只有SRAM/ASB和SDRAM地址空间的低一半能编址。实际上,读绝对SDRAM/SDRAM设备具有有效的地址空间;但是因为此限制不应用于目标字段,写SRAM/SDRAM仍然使用全部地址空间。
在相对方式中,指定地址的编址是在上下文空间中如5位源字段(a4-a0,或b4—b0)所定义的偏移量:
7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+
A GPR:|a4|0|上下文|a3|a2|a1|a0|a4=0
B GPR:|b4|1|上下文|b3|b2|b1|b0|b4=0
SRAM/ASB:|ab4|0|ab3|上下文|b2|b1|ab0|ab4=1,ab3=0
SDRAM:|ab4|0|ab3|上下文|b2|b1|ab0|ab4=1,ab3=1或6位目标字段(d5-d0)所定义的:
7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+
A GPR:|d5|d4|上下文|d3|d2|d1|d0| d5=0,d4=0
B GPR:|d5|d4|上下文|d3|d2|d1|d0| d5=0,d4=1
SRAM/ASB:|d5|d4|d3|上下文|d2|d1|d0| d5=1,d4=0,d3=0
SDRAM:|d5|d4|d3|上下文|d2|d1|d0| d5=1,d4=0,d3=1
如果<d5:d4>=1,1,则目标地址不选址有效的寄存器,因此没有目标操作数要写回。
其他实施例在附后的权利要求的范围内。
Claims (18)
1.一种在并行多线程处理器中维持线程执行的方法,其特征在于,所述方法包括下述步骤:
通过在所述多线程处理器中的执行线程来访问寄存器组,所述寄存器组被组织成每个线程可相对编址的多个可相对编址寄存器窗,从而,多个线程能使用完全相同的控制存储和位置但访问不同的寄存器分窗存储区,并执行不同功能。
2.如权利要求1所述的方法,其特征在于,相对寄存器编址在所述寄存器组的地址宽度上将寄存器存储区分成各个窗。
3.如权利要求1所述的方法,其特征在于,相对编址允许访问相对于一个寄存器窗的起点的任何分窗寄存器。
4.如权利要求1所述的方法,其特征在于,还包括:
按照在处理器中执行的线程数,将所述寄存器组组织成各个窗。
5.如权利要求1所述的方法,其特征在于,使用双端口随机访问存储器实现所述寄存器窗。
6.如权利要求1所述的方法,其特征在于,相对编址允许访问相对于寄存器窗起点的任何寄存器窗。
7.如权利要求1所述的方法,其特征在于,所述寄存器组是可绝对编址的,其中任何一个绝对可编址的寄存器能通过提供寄存器的确切地址被任何线程访问。
8.如权利要求7所述的方法,其特征在于,寄存器的绝对地址在指令的源字段或目标字段中直接指定。
9.如权利要求1所述的方法,其特征在于,相对地址在指令中被指定为上下文执行空间中的地址偏移量,由源字段或目标字段操作数确定。
10.一种基于硬件的多线程处理器,其特征在于包括:
处理器单元,它包括:
控制逻辑,包括上下文事件切换逻辑,所述上下文切换逻辑对访问用于多个可执行线程的微引擎进行判优;
算术逻辑单元,用于处理用于执行线程的数据;和
寄存器组,所述寄存器组被组织成每个可执行线程相对可编址的多个相对可编址寄存器窗,从而,多个线程能使用完全相同的控制存储和位置但访问不同的寄存器分窗存储区,并执行不同功能。
11.如权利要求10所述的处理器,其特征在于,所述控制逻辑还包括:
指令解码器;和
用于跟踪执行线程的程序计数器单元。
12.如权利要求11所述的处理器,其特征在于,所述程序计数器单元保持在硬件中。
13.如权利要求10所述的处理器,其特征在于,相对编址允许访问相对一个寄存器窗的起点的任何寄存器。
14.如权利要求10所述的处理器,其特征在于,所述寄存器组的窗的数目取决于在所述处理器中执行的线程数。
15.如权利要求11所述的处理器,其特征在于,使用双端口随机访问存储器提供分窗寄存器。
16.如权利要求10所述的处理器,其特征在于,所述处理单元是微程序编程的处理器单元。
17.一种用于管理在多线程处理器中执行多个线程的设备,其特征在于,所述设备包括:
通过在多线程处理器中的执行线程来访问寄存器组的逻辑,所述寄存器组被组织成每个线程可相对编址的多个相对可编址寄存器窗,从而,多个线程能使用完全相同的控制存储和位置但访问不同的寄存器分窗存储区,并执行不同功能。
18.如权利要求17所述的设备,其特征在于,所述寄存器组还是绝对可编址的,其中任何一个绝对可编址的寄存器能通过提供该寄存器的确切地址被任何线程访问。
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2000
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