CN1259692C - 应变半导体覆绝缘层型基底的制造方法 - Google Patents
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Abstract
本发明提出一种应变半导体覆绝缘层型基底的结构及其制造方法。首先提供一标的晶圆和一施体晶圆,施体晶圆包括一主体半导体基底和位于其上的一应变半导体层,其中主体半导体基底的晶格常数不同于半导体层的自然晶格常数。接着将施体晶圆黏着标的晶圆的表面后,将应变半导体层自施体晶圆分离,使应变硅层黏结至标的晶圆。
Description
技术领域
本发明是有关于一种半导体制程,且特别是有关于一种应变半导体硅覆绝缘层型基底,例如是应变硅覆绝缘层型基底(strained-silicon-on-insulator substrate;简称SSOI substrate)的结构的制造方法。
背景技术
随着闸极组件尺寸的缩小化,要使金氧半场效晶体管(MOSFET)组件能在低操作电压下,具有高驱动电流和高速的效能是相当困难的。因此,许多人在努力寻求改善金氧半场效晶体管组件的效能的方法。
利用应变引发的能带结构变型来增加载子的迁移率,以增加场效晶体管的驱动电流,可改善场效晶体管组件的效能,且此种方法已被应用于各种组件中,当硅MOSFET组件的信道处于双轴拉伸应变的情况时,可增加电子及电洞的迁移率。电子和电洞的迁移率的增加,则可以分别改善N信道和P信道MOSFET的驱动电流。
如图1A所示,传统的应变硅层116的制造,是在主体硅基底114上借助厚缓冲层或复合层结构,而于松弛的硅锗层112上磊晶成长出一应变硅层116。首先,会在先在硅基底114上形成一层厚度为微米等级的厚硅锗梯度缓冲层110。通常制备厚硅锗梯度缓冲层110需要数十分钟至数小时的时间,且制程成本相当昂贵。接着,在厚硅锗梯度缓冲层110上形成一层松弛的硅锗层112,其自然晶格常数大于硅。由于其晶格常数不同,因此松弛的结晶硅与松弛的结晶硅锗的晶格会无法相配,如图1B所示。如图1C所示,当在松弛的硅锗层112上磊晶成长薄硅层116时,薄硅层116的晶格会被迫对准松弛的硅锗层112的晶格,使得薄硅层116会处于双轴拉伸的情况。晶体管118是形成在硅层116中,其中晶体管118包括源极120、汲极122和闸极124。形成在应变硅层116中的晶体管,其电性效能会得到改善。
然而,这样的基底结构很难与传统的CMOS制程相整合,且会有以下的缺点。第一,成长厚梯度硅锗缓冲层是相当昂贵且费时的制程。第二,厚梯度硅锗缓冲层会与其下方的基底之间晶格错排,而产生分散且是三度空间的缺陷网。在硅锗缓冲层中的差排会增殖至晶圆表面,其差排密度高达1E4至1E5cm-2。如此高的差排密度会严重影响此基底结构在集成电路上的应用。
第三,表面粗糙度会是严重的问题,且会造成主动组件的迁移率降低。此外,传统的CMOS制程会使用高温制程,特别是在形成隔离结构(例如浅沟槽隔离结构或场氧化结构)的期间。这样的高温制程会造成缺陷密度的增加。
近来,T.A.Langdo等人在2002 IEEE国际SOI会议中发表″Preparation of novel SiGe-free strained Si on insulator substrates″,该等人提出在硅基底上成长复合梯度硅锗层,接着成长松弛的硅锗层和拉伸应变的硅层,以形成施体晶圆(donor wafer)。接着将氢植入施体晶圆内以产生一开裂面,并将此施体晶圆键结至氧化的硅标的晶圆。第一次回火会影响沿开裂面的***,第二次回火会增加键结强度,以形成应变硅覆绝缘层型基底。
然而此制程有以下缺点。第一,应变硅层的表面粗糙度约为5埃均方根,会影响组件的特性和施体晶圆和标的晶圆之间的键结强度。第二,应变硅层仍会遭遇到高缺陷密度的问题,因为其是覆盖于一梯度硅锗缓冲层上,而其中具有大量向上增殖的穿透性差排。因此,在应变硅层中的任何缺陷亦会转移至最后的SSOI晶圆中。
发明内容
本发明的目的在于提供一种具有低缺陷密度和较佳表面粗糙度的应变半导体覆绝缘层型基底的制造方法。
一种应变半导体覆绝缘层型基底的制造方法,包括:
提供一主体半导体基底,该主体半导体基底具有一晶格常数不同于硅的晶格常数;
在该主体半导体基底上形成一应变硅层,以形成一施体晶圆,该施体晶圆具有一上表面;
植入一离子至该施体晶圆的该主体半导体基底内,以形成一植入层;
提供一标的晶圆,该标的晶圆包括一基底和位于该基底上的一绝缘层,该绝缘层包括一高应力层,该标的晶圆具有一上表面;
将该施体晶圆的该上表面键结至该标的晶圆的该上表面;
进行一分离制程,以将该应变硅层自该施体晶圆分离,该应变硅层黏结至该标的晶圆;以及
加强该应变硅层和该标的晶圆之间的键结,其中该应变硅层具有拉伸应变时,该高应力层为一压缩应力层,该压缩应力膜是高硅含量氮化硅膜,而该应变硅层中具有压缩应变时,该高应力层为一拉伸应力层,该压缩应力层是高氮含量的氮化硅膜。
附图说明
图1A是显示传统的具有松弛的薄膜层的基底结构;
图1B是绘示硅锗层和硅层在松弛状态下的晶格状态;
图1C是绘示松弛硅锗层表面的硅层的双轴拉伸的示意图;
图2A是绘示本发明的一种应变硅覆绝缘层型基底的结构,其中埋入式绝缘层为单层结构;
图2B是绘示本发明的另一种应变硅覆绝缘层型基底的结构,其中埋入式绝缘层为迭层结构;
图3是绘示本发明的SSOI晶圆的制造流程图;
图4A至图4G是为一种形成SSOI基底的方法的示意图;
图5A和图5B是为另一种形成SSOI基底的方法的示意图;
图6A至图6E是为另一种制造SSOI基底的方法的示意图;
图7是绘示在本发明的SSOI基底上形成晶体管的示意图。
符号说明:
硅锗梯度缓冲层:110
松弛的硅锗层:112
主体硅基底:114
应变硅层:116、210
晶体管:118、750、752
源极:120、758
汲极:122、760
闸极:124、754
SSOI基底:200
埋入式绝缘层:212
绝缘层:212a、212c
高应力层:212b
基底:214
通道区:756
施体晶圆:400、500
主体板模基底:430
离子:432
基底表面:434
植入层:436
板模基底的一部分:440
热氧化层:208
应变记忆层:540
具体实施方式
SSOI晶圆的结构:
图2A是绘示本发明的一种应变硅覆绝缘层型基底200的结构,其包括覆盖于埋入式绝缘层212上的应变硅层210。埋入式绝缘层212可以是任何单层结构的绝缘材质,例如氧化硅、氮化硅、氧化铝等;或是迭层结构的绝缘材质,例如氮化硅/氧化硅、氧化硅/氮化硅/氧化硅等。图2B是绘示埋入式绝缘层212为迭层结构的示意图。
在一较佳实施例中,埋入式绝缘层212可以由一高应力层所组成。此由高应力层所构成的埋入式绝缘层212可用以维持或加强应变硅层210在SSOI晶圆中的应变。因此,高应力层亦做为应变记忆层。借由在埋入式绝缘层212中使用高应力层或应变记忆层,可以维持或增强紧邻其上方的应变硅层210的应变。
上述的高应力层中的应力较佳的是大于300Mpa。此高应力层或应变记忆层的材质例如是具有高应力的含氮层,包括氮化硅(Si3N4)、氮氧化硅(SiOxNy)、氨氧化硅(SiOxNy:Hz)、或其组合。当此高应力层或应变记忆层形成于硅基底上时,硅基底的表面会遭受到应力,使其硅晶格的晶格常数会改变,意即,硅表面会处于应变状态。因此,可以借由在下方提供高应力层或应变记忆层,如图2A的212,并紧临应变硅层210,而得以维持或甚至增强在SSOI基底200中的应变硅层210中的应变。
此高应力层或应变记忆层亦可以为夹置于两绝缘层中的迭层结构,如图2B所示,埋入式绝缘层212的结构为绝缘层212a、高应力层212b和绝缘层212c。在此情况下,绝缘层212a和212c两者可均为氧化物,例如氧化硅,当然亦可以使用其它的绝缘材质。
此高应力层或应变记忆层亦可以为一面与应变硅层210直接接触,另一面则和其底材间夹置一绝缘层。在此情况下,埋入式绝缘层212是由高应力层212b和绝缘层212c两迭层所构成。
埋入式绝缘层212是设置于一底材上,在此称基底214。此基底214的材质较佳的是硅,亦可是含轻掺杂,虽然掺杂不是必要的。其它例如锗、石英、蓝宝石(sapphire)和玻璃均可以做为基底214的材质。
以应变硅层210中的应变本质为拉伸应变为例。意即,应变硅层210在同平面方向的晶格常数是大于在松弛状态的硅的晶格常数。为了保持在应变硅层210中的拉伸应变,埋入式绝缘层212较佳的是包括具有高应力的压缩应力膜。压缩应力膜例如是借由电浆增强型化学气相沉积法(PECVD)沉积的高硅含量氮化硅膜,例如使用二氯硅烷(dichlorosilane)对氨气有高的流量比的沉积条件。
以应变硅层210中的应变本质为压缩应变为例。意即,应变硅层210在同平面方向的晶格常数小于在松弛状态的硅的晶格常数。为了保持在应变硅层210中的压缩应变,埋入式绝缘层212较佳的是包括具有高应力的拉伸应力膜。拉伸应力膜例如是借由电浆增强型化学气相沉积法(PECVD)沉积的高氮含量的氮化硅膜。在拉伸应力膜中的应力例如是20GPa。
以下表一是整理上述两种不同应变下的应变硅层210的特性。
表一拉伸应变和压缩应变的应变硅层的特性
拉伸应变的应变硅层 | 压缩应变的应变硅层 | |
应变硅层的硅晶格常数 | 小于松弛硅的晶格常数 | 大于松弛硅的晶格常数 |
其下方的应力层的性质 | 具压缩应力 | 具拉伸应力 |
图7是绘示在本发明的SSOI基底上形成晶体管的示意图。图中,CMOS晶体管750和752可以形成在应变硅层210中。其中,包括NMOS晶体管750的应变硅层210的一部分会轻掺杂p型掺质(例如硼),包括PMOS晶体管752的应变硅层210的一部分会轻掺杂n型掺质(例如砷和/或磷)。每一个晶体管包括闸极754和通道区756,源极758和汲极760是被通道区756分开。其它的组件亦可以形成在应变硅层上。
SSOI晶圆的制造方法:
图3是绘示本发明的SSOI晶圆的制造流程图。
首先,提供两晶圆,用以分别形成施体晶圆(donor wafer)和标的晶圆(target wafer)。
施体晶圆:
如方块310所示,施体晶圆(亦称板模基底,template substrate)是形成自晶格常数不同于硅的主体基底(例如半导体基底)。在方块312中,薄应变硅层是磊晶成长在晶格常数不同于硅的主体基底上,以形成施体晶圆。值得注意的是,本发明所形成施体晶圆并不需要梯度缓冲层。
标的晶圆:
如方块314所示,借由在基底上形成绝缘层以提供一标的晶圆(target wafer)。举例而言,在单层绝缘层的情况下,此绝缘层可以是借由在硅基底上热成长而形成的氧化硅。在具有高应力或应变记忆层的堆栈的绝缘层的情况下,可以借由在硅基底上热成长一层氧化硅,并接着使用PECVD制程沉积高应力氮化硅层。此氮化硅层还可以暴露在氧化环境下,以在氮化硅层的顶部部分形成一薄层的氮氧化硅层。此高应力层或应变记忆层较佳的是具有大于300Mpa的应力。
晶圆组装和分离:
在施体晶圆上的应变硅层可以借由晶圆键结和分离制程(waferbonding and separation process)转移至标的晶圆上,如方块316所示。举例而言,此晶圆键结和分离制程可以是SmartcutTM制程、或NanocleaveTM制程,两者均是出自于Silicon Genesis Corporation。详细的晶圆键结和分离制程可以参考美国专利第5,013,681、5,374,564、5,863,830、6,355,541、6,368,938和6,486,008号,此分离制程如方块318所示。
如果应变硅层具有拉伸应变,则施体晶圆的主体基底的晶格常数应大于硅的晶格常数,例如主体硅锗晶圆(SiGe wafer)。如果应变硅层具有压缩应变,则主体基底的晶格常数应具小于硅的晶格常数,例如主体硅锗碳晶圆(SiGeC wafer)。为了使SiGeC的晶格常数小于硅,在主体Si1-x-yGexCy中锗的组成x和碳的组成y要符合y>0.1x的条件。
当本发明以松弛的主体半导体基底制备SSOI基底时,表面缺陷密度和表面粗糙度的问题会相当少。举例而言,与在硅基底上成长厚梯度SiGe缓冲层的传统技术相较,本发明相当容易在松弛的主体SiGe晶圆上得到低缺陷密度和好的表面粗糙度。在上述的传统的方法中,在SiGe和其底层硅基底之间的晶格错排以及在不超过其临界厚度下所成长的SiGe缓冲层,会导致不可避免的错排片段(misfit segments)(如图1A标号A处)、穿透性差排(threading dislocations)(如图1A标号B处)和高表面粗糙度。在梯度SiGe缓冲层的线差排的位置和密度是不易控制的。
相反地,与最先进的硅基底相较,主体半导体基底具有低缺陷密度和表面粗糙度。在施体晶圆方面,应变硅层是磊晶成长于主体半导体基底,因此,可以避免上述缺陷和表面粗糙度的问题,以达到低缺陷密度和良好的表面粗糙度。此外,在施体晶圆上,应变硅层可以磊晶成长在任何具有单晶表面的主体基底上。
在晶圆分离之后,进行回火制程,以强化应变硅层和标的晶圆之间的键结,以形成应变硅覆绝缘层型晶圆。最后的键结步骤如方块320所示。与最先进的主体硅基底相较,在SSOI晶圆的应变硅层具有小于每平方公分1缺陷的缺陷密度,且小于2埃的均方根表面粗糙度。
以下将举三个例子进一步详细说明本发明的技术。
〔例1〕
图4A至图4G是为一种形成图2中的基底的方法的示意图。
标的晶圆:
首先请参照图4A,标的晶圆200包括一基底214(例如硅基底)和一绝缘层212(例如氧化物、氮化物或其组合)。在一较佳实施例中,此绝缘层212还可以包括上述的高应力层或应变记忆层。此应变记忆层较佳的是一应力超过300MPa的高应力膜,且较佳的是具有应力超过300MPa的氮化硅膜。图4A的标的晶圆200的绝缘层212例如是借由热氧化制程将基底214表面氧化,并接着沉积一高应力膜(例如氮化硅)于其上而成。此绝缘层212的厚度约介于100至5,000埃之间。
施体晶圆:
图4B和图4C是绘示形成施体晶圆400的示意图。首先,提供主体板模基底430,其中板模基底的材质是在其松弛的状态,且具有不同于硅的晶格常数。在此板模基底430上成长一磊晶的应变硅层210。此应变硅层210的厚约介于20至1,000埃之间。应变硅层210的厚度较佳的是小于其临界厚度,大于此临界厚度则会变得不稳定,且可能会松弛化。
在施体晶圆400中应变硅层210中应变(ε)的大小约小于4%,较佳的是约小于2%。自然应变可以是压缩或拉伸,其是根据使用的板模基底而定。如果板模基底430是由晶格常数大于硅的材质所组成,例如Si0.8Ge0.2,则在应变硅层210中的应变本质会为拉伸。如果板模基底430是由晶格常数小于硅的材质所组,例如Si0.98C0.02,则应变硅层210的应变会本质为压缩。
接着请参照图4C,将离子432(例如氢或择自由氦、氖、氩和氪所组成的族群的惰性气体)植入于施体晶圆400中。植入的离子的波峰是在基底表面434下方深度为xd处。植入的离子会产生植入层436。在较佳的实施例中,植入的离子为氢离子,植入的剂量大约为1015cm-2。植入的能量是依据所需的深度而定,且范围约为1至500keV。离子可以借由不同的技术来进行植入,例如粒子束线离子植入(beam line ionimplantation)、电浆浸入离子植入(plasma immersion ionimplantation;PIII)、或离子浴(ion shower)。因为氢离子较易穿越板模基底430至选定深度而不会造成材质的伤害,故为较佳的选择。
晶圆组装:
接下的步骤为标的晶圆200的上表面(即应变硅层210的表面)的键结制程,如图4D和图4E所示。此键结制程可以是β键结制程(betabonding process),其为一种将施体晶圆400和标的晶圆200结合在一起的制程。此β键结是来自于静电力(electrostatic force)或凡得瓦力(van der Waals force)。此标的晶圆200是做为机械支撑之用,用以将应变硅层210自施体晶圆400转移至标的晶圆200。此外,板模基底430的一部分440亦可以随应变硅层210转移至标的晶圆200。此转移的板模基材440可以被选择性地移除。在进行β键结之前,预进行键结的标的晶圆200和施体晶圆400的表面是进行清洗,以自其表面移除任何残留的液体或粒子。
此键结制程形成如图4E所示的晶圆组。根据本发明一较佳实施例,晶圆上的应变硅层210是夹置于两应力提供层(stressors)之间,或是于两应力诱导媒介层(stress-inducing agents)之间。其中,一应力提供层是为板模基底430,其会因应变硅层210和板模基底430之间晶格的错排(mismatch),而诱导应变硅层210中的应变;另一应力提供层是为在埋入式绝缘层212中的高应力层或应变记忆层,其是与应变硅层210邻接。因此,与其它形成SSOI基底的技术相较,本发明的应变硅层210中的应变可以被维持或加强。
晶圆分离:
接着将图4E中的晶圆组使用晶圆分离制程自植入层436处分离。举例而言,晶圆分离制程可以经由热处理而达成。当晶圆组的温度上升至某一程度,例如大约500℃左右,产生自植入层436内的微气泡会膨胀,促使压力上升。当微气泡的压力超过某一值时,施体晶圆400会沿着***面分离。进行此可控制的***制程的方法,例如是Silicon GenesisCorporation的SmartCutTM制程。结晶的重排和微气泡的接合,会产生足够动力的巨气泡,使薄膜自施体晶圆端分离。
分离出的其中一晶圆是为可重复使用的板模基底400。另一晶圆是为SSOI基底200,其表面(即应变硅层210表面)具有板模基底的一部分440,如第4F图所示。可以将在应变硅层210上的板模基底的一部分440蚀刻移除。
最后键结:
之后,进行应变硅层210和标的晶圆200之间的最后键结,以产生预定的SSOI基底。此最后键结的步骤通常为进行高温回火,而回火的温度通常为700℃以上。最后键结的步骤会在应变硅层210和标的晶圆200之间建立强键结。当晶圆在足够高温足够的时间下回火时,会在接合处形成共价键(covalent bonds)。在回火期间,应变硅层210表面会成长一层热氧化层208,如图4G所示。此热氧化层208可以被移除,例如借由在稀释的氢氟酸下湿蚀刻。在一较佳实施例中,在如图4G所示的SSOI晶圆200上的应变硅层210的应变,是为如图4C所示的施体晶圆400上的应变硅层210的至少90%。
〔例2〕
其它之前所述之用在结合施体晶圆和标的晶圆的晶圆键结和晶圆分离技术,亦可以用来形成如图2所示的SSOI基底。图5A和图5B是为另一种形成图2中的SSOI基底的方法的示意图。在此例子中,标的晶圆200与图4A的相同,意即,其包括基底214和设置于其上的绝缘层212。同样地,绝缘层212可以是氧化硅,基底214可以是硅基底。
施体晶圆500可以包括板模基底430、磊晶成长于其上的应变硅层210、以及形成在应变硅层210上的应变记忆层540。此位于应变硅层212上的应变记忆层540,可以借由化学气相沉积制程(CVD process)沉积而形成。接着,将图5A和图5B所示的标的晶圆200和施体晶圆500的顶部表面互相键结,意即,将位于施体晶圆500上的应变记忆层540键结至标的晶圆200上的绝缘层212。
上述的埋入式绝缘层212可以是由许多介电层所构成的堆栈结构。例如,高应力氮化硅层/氧化硅层的堆栈结构。亦可以是应力大于300MPa的高应力氮化硅层设置于应力小于300MPa的低应力氮化硅层上的堆栈结构。
有关使用晶圆键结和分离方法来制造SSOI基底的方法,如之前描述的其技术是为借由植入法用来诱导裂开面的产生。在这情况下,晶圆分离是借由热处理来达成。此外,施体晶圆500亦可以依据其它机制来诱发开裂制程以分离晶圆。举例而言,晶圆分离制程可以是原子层开裂制程(atomic layer cleaving process)或极微开裂制程(nanocleaveprocess),可参考Michael I.Current等人于2001 IEEE国际SOI会议,发表的″Atomic layer cleaving with SiGe strain layers forfabrication of Siand Ge-rich SOI device layers″。此极微开裂转移制程是利用应变层开裂面而发生膜层分离。
〔例3〕
图6A至图6E是为另一种制造SSOI基底的方法的示意图。
标的晶圆:
首先,提供如图6A所示的标的晶圆200,其包括基底214和位于其上的绝缘层212。承上所述,此绝缘层212可以包括高应力层或应变记忆层。其中,此高应力层或应变记忆层的压力大于300MPa。
施体晶圆:
提供如图6B所示施体晶圆400。施体晶圆400包括松弛的板模基底430和位于其上的应变硅层210。应变硅层210的厚度较佳的是小于1000埃,且应变范围约为0.01%至4%。此板模基底430可以是如前所述的主体SiGe基底或是Si1-x-yGexCy基底。在应变硅层210和松弛板模基底430之间有一界面,大应变梯度会沿此界面而存在。此应变硅层210可以利化学气相沉积法磊晶成长而成。
晶圆组装:
接着,施体晶圆400的上表面键结至标的晶圆200的上表面。晶圆键结制程如图6C所示,得到的晶圆组如图6D所示。
晶圆分离:
接着,借由使用类似极微开裂制程,会在或靠近应变硅层210和板模基底430之间的界面发生切割或开裂。此开裂面会开始于接近应变硅层210和板模基底430之间的界面。
如果开裂面在板模基材处,有一些板模基底430的材质会覆盖在SSOI基底200的应变硅层210上,此部分可以借由蚀刻制程来加以移除。如果开裂面在应变硅层210处,则回收的板模基底430上方会有一薄层的应变硅材。如果板模基底430要再重复利用,则可以将其表面的硅层移除。
最后键结:
在晶圆分离制程之后,在应变硅层210和标的晶圆200之间进行最后键结,以产生预定的抗凹陷SOI基底。其通常需要高温回火制程,而回火温度约为700℃以上。因而形成如图6E所示的应变硅覆绝缘层的结构。晶圆400是为模板基底,且可以回收和重复使用。
值得注意的是,可以使用施体晶圆和标的晶圆的其它组合,并借由上述的晶圆键结和晶圆分离方法,来制造SSOI基底。举例而言,施体晶圆可以是氧化硅层上覆盖应变硅层,或者是氮化硅/氧化硅迭层上覆盖应变硅层。
亦值得注意的是,应变半导体层亦可以是硅以外的材质。举例而言,本发明可以用来形成锗、砷化镓、或其它半导体材质的应变层。此外,施体晶圆还可包括具有多层结构形成在表面上的晶圆。例如,施体晶圆可以是表面具有SiGeC或SiC层的硅基底。
Claims (22)
1.一种应变半导体覆绝缘层型基底的制造方法,包括:
提供一主体半导体基底,该主体半导体基底具有一晶格常数不同于硅的晶格常数;
在该主体半导体基底上形成一应变硅层,以形成一施体晶圆,该施体晶圆具有一上表面;
植入一离子至该施体晶圆的该主体半导体基底内,以形成一植入层;
提供一标的晶圆,该标的晶圆包括一基底和位于该基底上的一绝缘层,该绝缘层包括一高应力层,该标的晶圆具有一上表面;
将该施体晶圆的该上表面键结至该标的晶圆的该上表面;
进行一分离制程,以将该应变硅层自该施体晶圆分离,该应变硅层黏结至该标的晶圆;以及
加强该应变硅层和该标的晶圆之间的键结,其中该应变硅层具有拉伸应变时,该高应力层为一压缩应力层,该压缩应力膜是高硅含量氮化硅膜,而该应变硅层中具有压缩应变时,该高应力层为一拉伸应力层,该压缩应力层是高氮含量的氮化硅膜。
2.根据权利要求1所述的应变半导体覆绝缘层型基底的制造方法,其中该高应力层具有大于300Mpa的应力。
3.根据权利要求1所述的应变半导体覆绝缘层型基底的制造方法,其中该主体半导体基底的该晶格常数大于硅的晶格常数。
4.根据权利要求3所述的应变半导体覆绝缘层型基底的制造方法,其中该主体半导体基底为一主体硅锗基底。
5.根据权利要求1所述的应变半导体覆绝缘层型基底的制造方法,其中该含氮层是为氮化硅、氮氧化硅、氨氧化硅、或其组合。
6.根据权利要求1所述的应变半导体覆绝缘层型基底的制造方法,其中该含氮层是为Si3N4。
7.根据权利要求1所述的应变半导体覆绝缘层型基底的制造方法,其中该应变硅层是处于一拉伸应变。
8.根据权利要求7所述的应变半导体覆绝缘层型基底的制造方法,其中该拉伸应变的大小介于0.01%和4%之间。
9.根据权利要求1所述的应变半导体覆绝缘层型基底的制造方法,其中该主体半导体基底的该晶格常数小于硅的晶格常数。
10.根据权利要求9所述的应变半导体覆绝缘层型基底的制造方法,其中该主体半导体基底是为一主体硅锗碳基底。
11.根据权利要求1所述的应变半导体覆绝缘层型基底的制造方法,其中该应变硅层是处于一压缩应变。
12.根据权利要求11所述的应变半导体覆绝缘层型基底的制造方法,其中该压缩应变的大小介于0.01%和4%之间。
13.根据权利要求1所述的应变半导体覆绝缘层型基底的制造方法,其中植入至该施体晶圆中的该离子是择自由氢、氦、氖、氩、氪和其组合所组成的族群中。
14.根据权利要求1所述的应变半导体覆绝缘层型基底的制造方法,其中该绝缘层为氧化硅。
15.根据权利要求1所述的应变半导体覆绝缘层型基底的制造方法,其中该绝缘层的厚度介于100和5000埃之间。
16.根据权利要求1所述的应变半导体覆绝缘层型基底的制造方法,其中该标的晶圆包括一硅基底。
17.根据权利要求1所述的应变半导体覆绝缘层型基底的制造方法,其中该施体晶圆更包括一介电层设于该应变硅层上。
18.根据权利要求17所述的应变半导体覆绝缘层型基底的制造方法,其中该介电层的材质是择自由氧化硅、氮化硅、氮氧化硅、氧化铝和其组合所组成的族群中。
19.根据权利要求18所述的应变半导体覆绝缘层型基底的制造方法,其中该介电层具有大于300Mpa的应力。
20.根据权利要求1所述的应变半导体覆绝缘层型基底的制造方法,其中该键结制程包括一β键结制程。
21.根据权利要求1所述的应变半导体覆绝缘层型基底的制造方法,其中该分离制程包括一可控制的开裂制程。
22.根据权利要求1所述的应变半导体覆绝缘层型基底的制造方法,其中加强该应变硅层和该标的晶圆之间的键结的制程包括:回火该应变硅层和该标的晶圆。
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-
2003
- 2003-03-05 US US10/379,873 patent/US6911379B2/en not_active Expired - Lifetime
- 2003-07-21 TW TW092119783A patent/TWI225283B/zh not_active IP Right Cessation
- 2003-08-21 CN CNB031539548A patent/CN1259692C/zh not_active Expired - Lifetime
- 2003-08-21 CN CNB2005101156272A patent/CN100378918C/zh not_active Expired - Lifetime
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2004
- 2004-02-10 SG SG200400560A patent/SG125932A1/en unknown
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US20040173790A1 (en) | 2004-09-09 |
CN1527357A (zh) | 2004-09-08 |
TW200418131A (en) | 2004-09-16 |
CN1790619A (zh) | 2006-06-21 |
US6911379B2 (en) | 2005-06-28 |
TWI225283B (en) | 2004-12-11 |
CN100378918C (zh) | 2008-04-02 |
SG125932A1 (en) | 2006-10-30 |
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