CN1245764C - 铁电存储晶体管及其形成方法 - Google Patents

铁电存储晶体管及其形成方法 Download PDF

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CN1245764C
CN1245764C CNB031106161A CN03110616A CN1245764C CN 1245764 C CN1245764 C CN 1245764C CN B031106161 A CNB031106161 A CN B031106161A CN 03110616 A CN03110616 A CN 03110616A CN 1245764 C CN1245764 C CN 1245764C
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许胜籐
张风燕
李廷凯
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Sharp Corp
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Abstract

本发明提供一种非易失性铁电存储器件，这种存储器件消除了与漏电流相关的晶体管存储保持性能变劣的问题。本发明的铁电存储晶体管包括：具有源区、栅区和漏区的衬底；位于栅区的栅极叠层，该栅极叠层包括：包含第一高k杯和第二高k杯在内的高k绝缘体元件、封闭在所述高k绝缘体元件内的铁电元件，以及位于所述高k绝缘体元件上部的上电极；位于所述衬底和栅极叠层上方的钝化氧化物层；以及喷涂金属，用于为源区、漏区、和栅极叠层形成相应的触点。

Description

铁电存储晶体管及其形成方法
技术领域
本发明涉及长存储保持时间单个晶体管铁电RAM的制造，具体地说，涉及一种具有铁电元件的铁电RAM，所述铁电元件被封装在高k电介质中。
背景技术
现有技术单个晶体管金属铁电氧化物半导体(MFOS)栅极叠层包括一个上电极、一个铁电层和一个氧化物层。在对这样一种器件进行编程之后，电子或空穴可以从上电极流入铁电层，并在铁电层中被俘获。被俘获电荷的极性与极化电荷的极性相反。这些被俘获的电荷补偿了极化电荷，使存储窗口减小。结果，晶体管存储保持性能变劣。
发明内容
本发明的目的在于提供一种非易失性铁电存储器件，它消除了与泄漏有关的晶体管存储保持性能的变劣。
本发明的另一目的在于提供一种铁电存储单元，所述单元包括封装在高k电介质中的铁电元件。
本发明的铁电存储晶体管包括：具有源区、栅区和漏区的衬底；位于所述栅区的栅极叠层，该栅极叠层包括：包含第一高k杯和第二高k杯在内的高k绝缘体元件、被封闭在所述高k绝缘体元件内的铁电元件、和位于所述高k绝缘体元件上部的上电极；位于所述衬底和栅极叠层上方的钝化氧化物层；以及喷涂金属，用于为源区、漏区和栅极叠层形成相应的触点。以此可以实现上述目的。
可由选自一组材料HfO2、ZrO2、和HfZrOx中的一种材料形成所述高k绝缘体元件。
所述高k绝缘体元件的厚度约在2nm到10nm之间。
可由选自一组材料PGO、PZT、BTO、SBTO、和SBTN中的一种材料形成所述铁电元件。
所述铁电元件的厚度约在100nm到600nm之间。
可由选自一组材料铜、铝、铱、和铂中的一种材料构成所述上电极。
本发明形成铁电存储晶体管的方法包括如下步骤：a)制备衬底，包括形成源区、栅区、漏区和氧化物器件隔离区；b)在衬底上淀积将要去除的(sacrificial)氧化物层；c)在准备去除的氧化物层上淀积栅极定位层(placeholder layer)；d)遮挡位于栅区上的栅极定位层和将要去除的氧化物层，并在源区、漏区、氧化物器件隔离区上除去所述栅极定位层和准备去除的氧化物层；e)在由步骤a)到d)所得结构上方淀积氧化物层，该氧化物层的厚度约为栅极定位层厚度的两倍；f)将由步骤a)到e)使所得的结构变得平滑至栅极定位层的水平；g)在栅区中除去栅极定位层和准备去除的氧化物层，形成栅极定位层结构；h)在由步骤a)-g)所得的结构上淀积高k绝缘体层，形成第一高k杯；i)用铁电材料填充第一高k杯，形成铁电元件；j)使铁电元件变得平滑到氧化物层的上部水平；k)在由步骤a)到j)所得的结构上淀积另一个高k绝缘体层，以在铁电元件上方形成第二高k杯；l)在第二高k杯上淀积上电极，形成栅极和栅极叠层；m)在由步骤a)到l)所得的结构上淀积一层钝化氧化物；n)蚀刻所述钝化氧化物，形成至源区、漏区和栅极叠层的对应触点通路；以及o)将由步骤a)到n)所得的结构金属化。以此实现上述的目的。
所述淀积高k绝缘层和淀积第一高k杯的步骤g)包括可由一组材料HfO2、ZrO2和HfZrOx中选出一种高k绝缘体材料。
所述淀积高k绝缘层和淀积第一高k杯的步骤g)包括淀积一层高k材料，其厚度约在2nm到10nm之间。
所述用铁电材料填充第一高k杯的步骤h)可以包括从一组材料PGO、PZT、BTO、SBTO和SBTN中选出一种铁电材料。
所述用铁电材料填充第一高k杯的步骤h)可以包括用铁电材料填充第一高k杯，铁电材料的厚度约在100nm到600nm之间。
在第二高k杯上方淀积上电极，以形成栅极和栅极叠层的步骤k)可以包括：可由一组材料铜、铝、铱、和铂中选出一种上电极材料。
淀积栅极定位层的步骤c)可以包括淀积一层从一组材料，包括氮化硅和多晶硅中选出的材料层。
给出本发明的这一概述和目的是为了迅速理解本发明的本质。通过结合附图参照本发明的优选实施例的下述详细描述，可以获得本发明的更加深入的理解。
附图说明
图1是现有技术晶体管10的示意图；
图2描述在图1的铁电电容器被编程为低阈值电压状态，并且栅极处于地电位之后的存储保持期间内的电荷和电场分布；
图3a是说明电荷俘获的示意图；
图3b是说明电荷俘获的另一示意图；
图4是本发明铁电存储晶体管50的示意图；
图5描述的是本发明铁电存储晶体管的状态；
图6-10描述本发明铁电存储晶体管制造方法中的连续步骤。
具体实施方式
相关申请
本申请涉及Hsu等人在2001年3月28日提出的系列号为NO.09/820039的“MFOS存储晶体管及其制造方法”。
图1是现有技术晶体管10的示意图。例如，现有技术晶体管10是典型的当前技术水平的晶体管，比如金属铁电氧化物半导体(MFOS)晶体管、金属铁电绝缘体半导体(MFIS)晶体管等。
晶体管10包括具有源区14、漏区16、和栅区18的衬底12，以及在栅区18上的栅极叠层20。
栅极叠层20包括高k绝缘体22、铁电元件24和上电极26。现有技术中的高k绝缘体22位于铁电元件24的下面及其侧面的周围。由钝化氧化物层28覆盖这一结构，其中形成通路，分别为源区14、栅极叠层20、和漏区16提供金属触点30、32和34。
栅极叠层20包括在硅衬底上的金属铁电薄膜绝缘体(MFIS)。高k绝缘体22的介电常数较高而漏电流较小，并可以从诸如HfO2、ZrO2和HfZrOx之类的材料中选出。铁电元件24从包括下列材料的材料组中选出：铅锗氧化物(Pb5Ge3O11)(PGO)、Pb(Zr，Ti)O3(PZT)、SrBi2Ta2O9(BTO)、SrBa2Ta2O9(SBTO)和SrBi2(Ta1-xNbx)2O9(SBTN)，并且上电极可由铜、铝、铱或铂构成。这样的结构称为铁电电容器。
图2描述在图1铁电电容器被编程为低阈电压状态并且栅极处于地电位之后的存储保持期间内电荷和电场的分布。箭头36代表高k绝缘体22的电压VOX，箭头38代表铁电(FE)元件24的电压VFE，而标号40代表栅极叠层20的顶部的电压V0。所述高k绝缘体22两端有电压，以及所述铁电元件24两端也有电压。高k绝缘体22两端的电压与铁电元件24两端的电压大小相等但极性相反。铁电元件24两端电压称为去极化电压。
VFE＝VOX＝VOO           (1)
VOO＝QR/(COX+CFE)      (2)
其中的QR是铁电元件24上的电荷，COX是高k绝缘体22的电容，CFE是铁电元件24的电容。
虽然空穴或电子都不可能从高k绝缘体22流入铁电元件(铁电薄膜)24，但在上电极26中有大量电子和空穴。以下将描述来自上电极26的空穴陷入铁电元件24中的现象。
图3a是说明电荷俘获的示意图。如图3a所示，空穴可以从上电极26移入铁电元件24。这种现象称为金属铁电金属(MFM)电容器的漏电流。空穴不能流过高k绝缘体22，这是因为在高k绝缘体22和铁电元件24的界面处有势垒，而且高k绝缘体22中的电场极性与铁电元件24中的电场极性相反的缘故。
图3b是说明电荷俘获的另一示意图。有如参照附图3a的描述的那样，空穴不能从铁电元件24流到高k绝缘体22中，如图3b所示，这些空穴仍然陷入铁电材料中，其中VFE和VOX这两者都等于0。在铁电元件24中俘获的空穴补偿了铁电元件24中的极化电子。这就减小了存储晶体管的存储窗口，并且使器件的存储特性变劣。在将存储晶体管编程为它的高阈电压状态时，电荷和电压的极性都发生改变，但电子的流动和俘获机制仍如以上所述。
图4是本发明铁电存储晶体管50的示意图。在本发明的铁电存储晶体管50中，为了消除参照附图1-3所描述的与存储保持时间有关的漏电流，在铁电薄膜和上电极之间采用一个附加的绝缘体。
晶体管50包括具有源区54、漏区56、和栅区58的衬底52，以及栅极叠层60。栅极叠层60包括高k绝缘体62，高k绝缘体62封闭铁电元件64和上电极66。衬底52有氧化物隔离区(氧化物元件隔离区)90。
高k绝缘体62包括第一高k杯(或者简称为下部)62L，它位于铁电元件64和硅衬底52之间，并且包围铁电元件64的侧面；以及第二高k杯(或简称上部)62U，它位于铁电元件64和上电极66之间。于是，铁电元件64被封闭在高k绝缘体62(第一高k杯62L和第二高k杯62U)之内。由硅氧化物层96和钝化氧化物层68覆盖这一结构，其中形成通路，用于分别为源区54、栅极叠层60和漏区56提供金属触点70、72、和74。栅极叠层60包括硅衬底上的金属铁电薄膜绝缘体(MFIS)。
高k绝缘体62的介电常数较高而漏电流小，并可以从诸如HfO2、ZrO2和HfZrOx之类的材料中选出。铁电元件64从包括下列材料的一组材料中选出：铅锗氧化物(Pb5Ge3O11)(PGO)、Pb(Zr，Ti)O3(PZT)、SrBi2Ta2O9(BTO)、SrBa2Ta2O9(SBTO)和SrBi2(Ta1-xNbx)2O9(SBTN)，并且可由包括一组材料铜、铝、铱、或铂中的一种形成上电极。
图5描述本发明铁电存储晶体管的状态。图5说明在将铁电存储晶体管编程为它的低阈值电压之后，并且在栅极电压返回地电位之后的电场极性和电荷分布。铁电元件64两端的电压78(VFE)等于第一高k杯62L两端的电压(箭头76，VOX1)和第二高k杯62U两端的电压(箭头80，VOX2)之和。铁电元件64中电场的极性与第一高k杯62L和第二高k杯62U中电场的极性相反。这个结构中不存在现有技术中所看到的与性能变差机制有关的普通漏电流，这是因为两个绝缘体中(第一和第二高k杯62L与62U)不存在任何自由载流子，还因为阻止了场分布电流载流子流入铁电元件64。箭头82代表上电极66上部那里的电压V0。在本发明的结构中，存储器性能变差的唯一来源是由于去极化场的存在。
在将本发明铁电存储晶体管编程为它的高阈值电压状态时，铁电元件64和第一及第二高k杯62L及62U两者中的电荷和电场极性都要改变方向。不存在与漏电流有关的电荷俘获，而电荷俘获有可能引起存储保持性能变差。
下面参照附图6-10描述本发明制造铁电存储晶体管的方法。
图6描述本发明制造铁电存储晶体管方法中的一个步骤。通过任何用于衬底制备的当前技术水平的技术制备衬底52。利用阱离子注入法形成各有源区，其中包括衬底52中的源区54、和漏区56和栅区58。器件隔离法包括形成氧化物隔离区90的步骤，该氧化物隔离区90在存储晶体管周边的周围延伸。
在源区54、漏区56、栅区58和氧化物隔离区90上生长将要废弃的栅极氧化物层(准备去除的氧化物层)92，使其厚度约为2nm到5nm之间，并在准备去除的栅极氧化物层92上淀积一层氮化硅94，使其厚度在约100nm到600nm之间。遮盖所述栅区58上的氮化硅层94和准备去除的栅极氧化物层92，并且除去源区54、漏区56、栅区58和氧化物隔离区90上的氮化硅膜层94以及准备去除的栅极氧化物层92。于是，由氮化硅层94构成的栅极定位层保持在栅区58上。可以使用多晶硅替代氮化硅层。
在图6中，可以除去源区54、漏区56和氧化物隔离区90上的准备去除的氧化物层92。但是，可以不除去这个准备去除的氧化物层92，代之以随氧化硅层96一起使用。
可以通过源/漏注入法制备各有效区(源区54和漏区56)，这包括LDD、Halo和N+或P+注入法—如果这时是这样期望的话。于是，得到如图6所示的结构。
图7描述本发明制造铁电存储晶体管方法中的一个步骤。淀积硅氧化物层96，使其厚度约在200nm到1200nm之间。这个硅氧化物层96的厚度最好约为栅极定位层厚度的两倍。通过CMP使这个结构变得平滑，以使硅氧化物层96平整，停止在氮化硅层94(或者栅极定位层)的水平。于是得到如图7所示的结构。
图8描述本发明制造铁电存储晶体管方法中的一个步骤。如图8所示，使所述这个结构受到蚀刻，并除去氮化硅层94(栅极定位层)，形成栅极定位结构800。最好通过湿法蚀刻过程对于这个氮化硅层94(栅极定位层)进行蚀刻。接下去，通过BHF蚀刻整个结构，以除去栅区58中的准备去除的氧化物层92。
然后，在整个结构上淀积栅极绝缘体62。如上所述，栅极绝缘体62是从包括HfO2、ZrO2、和HfZrOx的一组材料中选出来的。栅极绝缘体62由高k绝缘体构成，这是先前描述过并且经过核实的，厚度在约2nm到10nm之间。用62L代表栅极绝缘体62与对应于栅区58并且覆盖栅极定位结构800的硅衬底52接触的部分。这里将所述的部分62L称为第一高k杯或高k下部。
图9描述本发明制造铁电存储晶体管方法中的一个步骤。淀积铁电薄膜(铁电元件)64，以填充栅极定位结构800。铁电薄膜64是从包括PGO、PZT、BTO、SBTO和SBTN的一组材料中选出的。铁电薄膜64填充由第一高k杯L形成的“杯”。
接下去，使铁电薄膜64变得平滑，并停止在硅氧化物层96的水平。可以通过化学机械抛光(CMP)或其它公知的平面深蚀刻方法实现所述平滑过程。于是，得到如图9所示的结构。
图10描述本发明制造铁电存储晶体管方法中的一个步骤。在图9所示的结构上，通过CVD淀积厚度约在2nm到10nm之间的另一个高k绝缘体，这个绝缘体就是高k绝缘体的另一部分62U，这里称为高k上部或第二高k杯。所选的另一个高k绝缘体材料具有漏电流小的特性。这之后，在此另一个高k绝缘体上形成上电极66。上电极选自包括铜、铝、铂、和铱的一组材料。
对于上电极和另一个高k绝缘体进行蚀刻，形成如图10所示的上电极66和第二高k杯62U，最终产生控制栅极和栅极叠层60。铁电元件64由高k绝缘体(第一高k杯62L和第二高k杯62U)封闭包围。通过CVD淀积钝化氧化物层68(图4)，蚀刻这个结构并使其金属化，以形成接触通路，从而可以得到如图4所示的结构。
于是，已经公开了用于制造具有长存储保持时间特性的铁电存储晶体管的方法和***。可以看出，在由所附权利要求书限定的本发明范围内，还可能进行其它的改型和变化。
如以上所述，本发明的铁电存储晶体管包括：具有源区、栅区、和漏区的衬底；位于栅区的栅极叠层，所述栅极叠层包括：包含第一高k杯和第二高k杯在内的高k绝缘体元件、封闭在所述高k绝缘体元件内的铁电元件，以及位于所述高k绝缘体元件上部的上电极；定位在所述衬底和栅极叠层上方的钝化氧化物层；以及喷涂金属，用于为源区、漏区和栅极叠层形成相应的触点。由于铁电元件由高k绝缘体封闭，所以电子和空穴不会从上电极流到铁电元件内。于是，不会发生与漏电流相关的电荷俘获，而那是可能引起存储保持性能变劣的。因此，不会使铁电存储晶体管的存储保持性能下降。

Claims (13)

1.一种铁电存储晶体管，它包括：
具有源区、栅区、和漏区的衬底；
位于栅区上在源区和漏区之间的栅极叠层，该栅极叠层包括：
包含第一高k杯和第二高k杯在内的高k绝缘体元件；
铁电元件，其中所述铁电元件封闭在所述高k绝缘体元件内；以及
位于所述高k绝缘体元件上部的上电极；
位于所述衬底和栅极叠层上方的钝化氧化物层；和
与源区、漏区和栅极叠层接触的金属触点。
2.根据权利要求1所述的铁电存储晶体管，其中，所述高k绝缘体元件可由一组材料HfO2、ZrO2和HfZrOx中选出一种材料形成。
3.根据权利要求1所述的铁电存储晶体管，其中，所述高k绝缘体元件的厚度在2nm到10nm之间。
4.根据权利要求1所述的铁电存储晶体管，其中，所述铁电元件可由一组材料PGO、PZT、BTO、SBTO和SBTN中选出的一种材料形成。
5.根据权利要求1所述的铁电存储晶体管，其中，所述铁电元件的厚度在100nm到600nm之间。
6.根据权利要求1所述的铁电存储晶体管，其中，所述上电极可由一组材料铜、铝、铱、和铂中选出的一种材料形成。
7.一种形成铁电存储晶体管的方法，其中，它包括如下步骤：
a)制备衬底，包括形成源区、栅区、漏区、和氧化物器件隔离区；
b)在衬底上淀积准备去除的氧化物层；
c)在准备去除的氧化物层上淀积栅极定位层；
d)遮挡位于栅区上的栅极定位层和准备去除的氧化物层，并在源区、漏区、氧化物器件隔离区上除去栅极定位层和准备去除的氧化物层；
e)在由步骤a)到d)所得的结构上方淀积氧化物层，该氧化物层的厚度为栅极定位层厚度的两倍；
f)使由步骤a)到e)所得的结构变得平滑至栅极定位层的水平；
g)在栅区中除去栅极定位层和准备去除的氧化物层，形成栅极定位层结构；
h)在由步骤a)-g)所得结构上淀积高k绝缘体层，形成第一高k杯；
i)用铁电材料填充第一高k杯，形成铁电元件；
j)使铁电元件成为与氧化物层的上部水平面相平；
k)在由步骤a)到j)所得的结构上淀积另一高k绝缘体层，以在铁电元件上方形成第二高k杯；
l)在第二高k杯上淀积上电极，形成栅极和栅极叠层；
m)在由步骤a)到l)所得的结构上淀积一层钝化氧化物；
n)蚀刻钝化氧化物，以形成至源区、漏区和栅极叠层的对应触点通路；
o)使由步骤a)到n)所得的结构金属化。
8.根据权利要求7所述的方法，其中，所述淀积高k绝缘体层和淀积第一高k杯的步骤h)包括由一组材料HfO2、ZrO2、和HfZrOx中选出一种高k绝缘体材料。
9.根据权利要求7所述的方法，其中，所述淀积高k绝缘体层和淀积第一高k杯的步骤h)包括淀积一层高k材料，其厚度在2nm到10nm之间。
10.根据权利要求7所述的方法，其中，所述用铁电材料填充第一高k杯的步骤i)包括从一组PGO、PZT、BTO、SBTO、和SBTN中选出一种铁电材料。
11.根据权利要求7所述的方法，其中，所述用铁电材料填充第一高k杯的步骤i)包括用铁电材料填充第一高k杯，所述铁电材料的厚度在100nm到600nm之间。
12.根据权利要求7所述的方法，其中，在第二高k杯上方淀积上电极，形成栅极和栅极叠层的步骤k)包括可由一组材料铜、铝、铱、和铂中选出一种上电极材料。
13.根据权利要求7所述的方法，其中，所述淀积栅极定位层的步骤c)包括淀积从包括氮化硅和多晶硅在内的一组材料中选出的一层材料。
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US6531325B1 (en) 2003-03-11
US20030222291A1 (en) 2003-12-04
US6703655B2 (en) 2004-03-09
TW200308095A (en) 2003-12-16
TWI223452B (en) 2004-11-01
CN1497735A (zh) 2004-05-19
KR20030094499A (ko) 2003-12-12
JP4179900B2 (ja) 2008-11-12

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