CN106444964A - Clock system for FPGA, and server - Google Patents
Clock system for FPGA, and server Download PDFInfo
- Publication number
- CN106444964A CN106444964A CN201610876447.4A CN201610876447A CN106444964A CN 106444964 A CN106444964 A CN 106444964A CN 201610876447 A CN201610876447 A CN 201610876447A CN 106444964 A CN106444964 A CN 106444964A
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- clock
- fpga
- homology
- logic module
- chip
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a clock system for an FPGA, and a server. The clock system for the FPGA comprises a global clock generator of external equipment and a variable clock generator, wherein the global clock generator of the external equipment is used for generating multi-path homogenous clocks, transmitting the clocks to logic modules of FPGA chips in an FPGA board card correspondingly and performing data transmission with the logic modules; the external equipment comprises a CPU and/or other FPGA board cards; the variable clock generator is connected with the logic modules and is used for generating frequency and/or phase position variable clocks and transmitting the clocks to the logic modules. The clock system provided by the invention can change the clock provided for the FPGA according to the requirement of the external clock; when the logic modules need to perform data transmission with the external equipment and if a connecting bus needs the FPGA and the external equipment to adopt the homogenous clock design, the logic modules of the FPGA can select the homogenous clock provided by the clock system to serve as a reference clock, thus the clock system provided by the invention enables the FPGA to meet more logic verification and the flexibility of the FPGA is improved.
Description
Technical field
The present invention relates to clock technology field, particularly relate to a kind of clock system for FPGA and server.
Background technology
High-end fpga chip be often used as ASIC (Application Specific Integrated Circuit, specially
With integrated circuit) produce before logic checking, when building a FPGA verification platform, in order to as much as possible taking into account is patrolled
Collecting the various external clock demands being likely to occur in exploitation, the external clock hardware design of FPGA will cover various as far as possible
Situation.
Several parameters that clock demand is paid close attention to mostly are that frequency, shake size, multiple chip clock whether homology, level are big
Little and classification etc..And after fpga chip is selected, the level classification of required clock and level i.e. can determine that, upon selection
The shake size of clock is can determine that during clock generator, so when fpga logic change causes external clock changes in demand, outward
Frequency that what portion's reference clock generally required change is and whether homology.
And clock that clock system of the prior art provides for the logic module in FPGA is generally more single, so that
The logic checking that is capable of of FPGA is less so that the very flexible of FPGA.
Therefore, a kind of scheme solving above-mentioned technical problem how is provided to be that those skilled in the art are presently required solution
Problem.
Content of the invention
It is an object of the invention to provide a kind of clock system for FPGA, more patrol so that FPGA disclosure satisfy that
Collect checking, improve the flexibility of FPGA；It is a further object of the present invention to provide the service of a kind of clock system for FPGA
Device.
For solving above-mentioned technical problem, the invention provides a kind of clock system for FPGA, including：
For generate logic module in multichannel homology clock the fpga chip that is respectively sent in FPGA board and
With the global clock generator of the external equipment that described logic module carries out data transmission, described external equipment include CPU and/or
Other FPGA boards；
Be connected with described logic module, for generating the clock of frequency and/or phase variable and sending extremely described logic mould
The variable clock generator of block.
Preferably, when described logic module is multiple, described clock system also includes：
Input is connected with described global clock generator, the clock pulses that output is connected with multiple described logic modules
Driving chip, for receiving the described homology clock of described global clock generator output and described homology clock being carried out homophase
Position, the fan-out of same frequency, the output multi-channel clock identical with described homology clock to multiple described logic modules.
Preferably, described variable clock generator is Si5338 chip.
Preferably, the input of described Si5338 chip receives described homology clock, to described homology clock division or
After frequency multiplication, output is to described logic module.
Preferably, an output of described Si5338 chip feeds back to the input of described Si5338 chip.
Preferably, the input of described Si5338 chip is connected with default clock generator, output to described default when
The clock of clock generator output carries out dividing or output extremely described logic module after frequency multiplication.
Preferably, described default clock generator is crystal oscillator.
Preferably, described global clock generator is CK420BQ, and described homology clock is the homology clock of 100MHz.
Preferably, described clock pulses driving chip is DB5338.
For solving above-mentioned technical problem, present invention also offers a kind of server, including the use as described in above-mentioned any one
Clock system in FPGA.
The invention provides a kind of clock system for FPGA and server, including for generating multichannel homology clock simultaneously
The logic module being respectively sent in the fpga chip in FPGA board and the outside carrying out data transmission with logic module set
Standby global clock generator, external equipment includes CPU and/or other FPGA boards；It is connected with logic module, be used for generating frequency
The clock of rate and/or phase variable simultaneously sends to the variable clock generator of logic module.
Visible, the present invention includes global clock generator and variable clock generator, and wherein, global clock generator is
Logic module in FPGA and the external equipment offer homology clock that can carry out output transmission with logic module, V-CLK is sent out
Raw device provides the clock of frequency and/or phase variable for logic module, and based on this, this clock system can be according to external clock need
Asking and change into the clock that FPGA provides, when logic module needs to carry out data transmission with external equipment, needing if connecting bus
FPGA and external equipment is wanted to use the design of homology clock, then when the logic module of FPGA can select the homology that clock system provides
Clock is as reference clock, it is seen then that the clock system that the present invention provides, so that FPGA disclosure satisfy that more logic checking, carries
The high flexibility of FPGA.
Brief description
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, below will be to institute in prior art and embodiment
The accompanying drawing using is needed to be briefly described, it should be apparent that, the accompanying drawing in describing below is only some enforcements of the present invention
Example, for those of ordinary skill in the art, on the premise of not paying creative work, can also obtain according to these accompanying drawings
Obtain other accompanying drawing.
The structural representation of a kind of clock system for FPGA that Fig. 1 provides for the present invention；
Fig. 2 is used for the structural representation of the clock system of FPGA for the another kind that the present invention provides.
Detailed description of the invention
The core of the present invention is to provide a kind of clock system for FPGA, more patrols so that FPGA disclosure satisfy that
Collect checking, improve the flexibility of FPGA；Another core of the present invention is to provide the service of a kind of clock system for FPGA
Device.
Purpose, technical scheme and advantage for making the embodiment of the present invention are clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
The a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment being obtained under the premise of not making creative work, broadly falls into the scope of protection of the invention.
Embodiment one
Refer to Fig. 1, the structural representation of a kind of clock system for FPGA that Fig. 1 provides for the present invention, this clock
System includes：
For generate logic module in multichannel homology clock the fpga chip that is respectively sent in FPGA board and
With the global clock generator 1 of the external equipment that logic module carries out data transmission, external equipment include CPU and/or other
FPGA board；
It is understood that the logic module in fpga chip is usually multiple, some of them logic module is by connecting
Bus is connected with external equipment and realizes that data are transmitted, when this connection bus requirements FPGA and external equipment use homology clock to set
Timing, then when the logic module in fpga chip selects the outside homology clock source of global clock generator 1 output as reference
Clock.
Be connected with logic module, for generate the clock of frequency and/or phase variable and send to logic module variable
Clock generator 2.
It is homology clock when the logic module of FPGA does not has requirement and demand frequency with other external equipment clock homologies
Frequency outside other frequencies, then make logic module select the clock source that produced by variable clock generator 2, regulation can simultaneously
Become output frequency and/or the phase place of the clock source of clock generator 2 output.
Specifically, variable clock generator 2 also provides the clock of frequency and/or phase variable for logic module, with completely
Change to outside clock demand when the logic of foot logic module changes.
In addition, the number of variable clock generator 2 here can be multiple, to realize that logic module needs multiple difference
The demand of the clock of frequency, concrete number is determined according to actual conditions.
The invention provides a kind of clock system for FPGA, including for generating multichannel homology clock and sending respectively
The logic module in fpga chip to FPGA board and the overall situation of the external equipment carrying out data transmission with logic module
Clock generator, external equipment includes CPU and/or other FPGA boards；Be connected with logic module, be used for generating frequency and/or
The clock of phase variable simultaneously sends to the variable clock generator of logic module.
Visible, the present invention includes global clock generator and variable clock generator, and wherein, global clock generator is
Logic module in FPGA and the external equipment offer homology clock that can carry out output transmission with logic module, V-CLK is sent out
Raw device provides the clock of frequency and/or phase variable for logic module, and based on this, this clock system can be according to external clock need
Asking and change into the clock that FPGA provides, when logic module needs to carry out data transmission with external equipment, needing if connecting bus
FPGA and external equipment is wanted to use the design of homology clock, then when the logic module of FPGA can select the homology that clock system provides
Clock is as reference clock, it is seen then that the clock system that the present invention provides, so that FPGA disclosure satisfy that more logic checking, carries
The high flexibility of FPGA.
Embodiment two
Refer to Fig. 2, the another kind that Fig. 2 provides for the present invention for the structural representation of the clock system of FPGA, this when
Master slave system is on the basis of embodiment one：
As preferably, when logic module is multiple, clock system also includes：
Input is connected with global clock generator 1, and the clock pulses that output is connected with multiple logic modules drives core
Piece 3, for receiving the homology clock of global clock generator 1 output the fan-out that homology clock is carried out same-phase, same frequency,
The output multi-channel clock identical with homology clock is to multiple logic modules.
Specifically, because the output port of global clock generator 1 is limited, therefore, for meeting in fpga chip
The needs of multiple logic modules, can arrange clock pulses driving chip 3 between global clock generator 1 and logic module,
Thus realize exporting global clock generator 1 to a road homology clock of clock pulses driving chip 3 become multichannel homology when
Clock is supplied to multiple logic module.
As preferably, clock pulses driving chip 3 is DB5338.
Certainly, the clock pulses driving chip 3 in the application can also be the clock pulses driving chip of other models, this
Invention is not particularly limited at this, can realize the purpose of the present invention.
As preferably, variable clock generator 2 is Si5338 chip.
Certainly, the variable clock generator 2 in the application can also be the clock generator of other models, and the present invention is at this
It is not particularly limited, the purpose of the present invention can be realized.
As preferably, the input of Si5338 chip receives homology clock, to defeated after homology clock division or frequency multiplication
Go out to logic module.
As preferably, an output of Si5338 chip feeds back to the input of Si5338 chip.
As preferably, the input of Si5338 chip is connected with default clock generator, and default clock is sent out by output
The clock of raw device output carries out dividing or exporting to logic module after frequency multiplication.
Specifically, Si5338 chip is clock generator chip, has two kinds of use patterns, respectively synchronizing frequency transmission mode
(such as Si5338_0 in Fig. 2) and free-running operation pattern (such as Si5338_1 in Fig. 2).During synchronizing frequency transmission mode, Si5338 core
Piece input clock is overall situation homology clock, and output clock is by overall situation homology clock multiplier or frequency dividing change, thus causes
The output clock of this chip and input clock have certain correlation in phase place.
Furthermore it is possible to 3 output channels of Si5338_0 are fed back to the input of Si5338_0, thus realize Si5338_0
Output and input phase zero-lag.
When using free-running operation pattern, the four tunnels output clocks of Si5338_1 are adjustable frequency, now clock with complete
Office clock is unrelated, only relevant with the clock of default clock generator output.
As preferably, default clock generator is crystal oscillator.
Certainly, default clock generator here can also be the clock generator of other models, and the present invention does not does at this
Particularly limit, the purpose of the present invention can be realized.
As preferably, global clock generator 1 is CK420BQ 11, and homology clock is the homology clock of 100MHz.
It is understood that because current server is mostly intel server, it is same that a lot of chips therein make
The frequency of source clock is 100MHz, and therefore, the present invention selects CK420BQ 11 as global clock generator 1, and output frequency
Homology clock for 100MHz.
The four tunnel homology clocks that this chip produces are separately input to two FPGA boards and two CPU board cards, thus make
Clock on this four boards with homology, now can use the 100MHz clock of global clock generator generation on four boards
Chip works under identical step.
For solving above-mentioned technical problem, present invention also offers a kind of server, including as described above for FPGA
Clock system.
Said system be refer to for the introduction for the clock system of FPGA in the server that the present invention provides implement
Example, the present invention does not repeats them here.
It should be noted that in this manual, term " includes ", "comprising" or its any other variant are intended to
Comprising of nonexcludability, so that include that the process of a series of key element, method, article or equipment not only include that those are wanted
Element, but also include other key elements being not expressly set out, or also include for this process, method, article or equipment
Intrinsic key element.In the case of there is no more restriction, the key element being limited by statement " including ... ", it is not excluded that
Including the process of described key element, method, article or equipment there is also other identical element.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses the present invention.
Multiple modifications to these embodiments will be apparent from for those skilled in the art, as defined herein
General Principle can realize without departing from the spirit or scope of the present invention in other embodiments.Therefore, the present invention
It is not intended to be limited to the embodiments shown herein, and be to fit to and principles disclosed herein and features of novelty phase one
The scope the widest causing.
Claims (10)
1. the clock system for FPGA, it is characterised in that include：
For generate logic module in multichannel homology clock the fpga chip that is respectively sent in FPGA board and with institute
State the global clock generator of the external equipment that logic module carries out data transmission, described external equipment include CPU and/or other
FPGA board；
Be connected with described logic module, for generating the clock of frequency and/or phase variable and sending extremely described logic module
Variable clock generator.
2. the clock system for FPGA as claimed in claim 1, it is characterised in that when described logic module is multiple,
Described clock system also includes：
Input is connected with described global clock generator, and the clock pulses that output is connected with multiple described logic modules drives
Chip, for receive described global clock generator output described homology clock and described homology clock is carried out same-phase,
The fan-out of same frequency, the output multi-channel clock identical with described homology clock to multiple described logic modules.
3. the clock system for FPGA as claimed in claim 1 or 2, it is characterised in that described variable clock generator is
Si5338 chip.
4. the clock system for FPGA as claimed in claim 3, it is characterised in that the input termination of described Si5338 chip
Receive described homology clock, to output after described homology clock division or frequency multiplication to described logic module.
5. the clock system for FPGA as claimed in claim 4 a, it is characterised in that output of described Si5338 chip
End feeds back to the input of described Si5338 chip.
6. the clock system for FPGA as claimed in claim 3, it is characterised in that the input of described Si5338 chip with
Presetting clock generator to connect, the clock that described default clock generator exports is carried out dividing or exports after frequency multiplication by output
To described logic module.
7. the clock system for FPGA as claimed in claim 6, it is characterised in that described default clock generator is crystalline substance
Shake.
8. the clock system for FPGA as claimed in claim 1, it is characterised in that described global clock generator is
CK420BQ, described homology clock is the homology clock of 100MHz.
9. the clock system for FPGA as claimed in claim 2, it is characterised in that described clock pulses driving chip is
DB5338.
10. a server, it is characterised in that include the clock system for FPGA as described in any one of claim 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610876447.4A CN106444964A (en) | 2016-10-08 | 2016-10-08 | Clock system for FPGA, and server |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610876447.4A CN106444964A (en) | 2016-10-08 | 2016-10-08 | Clock system for FPGA, and server |
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| Publication Number | Publication Date |
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| CN106444964A true CN106444964A (en) | 2017-02-22 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610876447.4A Pending CN106444964A (en) | 2016-10-08 | 2016-10-08 | Clock system for FPGA, and server |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107991553A (en) * | 2017-11-21 | 2018-05-04 | 中国电子科技集团公司第四十研究所 | A kind of vector network analyzer clock system and its optimization method |
| CN109901664A (en) * | 2019-02-27 | 2019-06-18 | 苏州浪潮智能科技有限公司 | Method, apparatus, system, equipment and the readable storage medium storing program for executing of clock signal are provided |
| CN114063704A (en) * | 2021-08-30 | 2022-02-18 | 浪潮电子信息产业股份有限公司 | RTC clock circuit |
| CN114115438A (en) * | 2020-08-31 | 2022-03-01 | 超聚变数字技术有限公司 | FPGA prototype verification clock device |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107991553A (en) * | 2017-11-21 | 2018-05-04 | 中国电子科技集团公司第四十研究所 | A kind of vector network analyzer clock system and its optimization method |
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| CN109901664A (en) * | 2019-02-27 | 2019-06-18 | 苏州浪潮智能科技有限公司 | Method, apparatus, system, equipment and the readable storage medium storing program for executing of clock signal are provided |
| CN109901664B (en) * | 2019-02-27 | 2020-03-27 | 苏州浪潮智能科技有限公司 | Method, apparatus, system, device and readable storage medium for providing clock signal |
| CN114115438A (en) * | 2020-08-31 | 2022-03-01 | 超聚变数字技术有限公司 | FPGA prototype verification clock device |
| CN114115438B (en) * | 2020-08-31 | 2023-07-04 | 超聚变数字技术有限公司 | FPGA prototype verification clock device |
| CN114063704A (en) * | 2021-08-30 | 2022-02-18 | 浪潮电子信息产业股份有限公司 | RTC clock circuit |
| CN114063704B (en) * | 2021-08-30 | 2023-11-03 | 浪潮电子信息产业股份有限公司 | RTC clock circuit |
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