CN1216405C - 半导体衬底、场效应晶体管、锗化硅层形成方法及其制造方法 - Google Patents
半导体衬底、场效应晶体管、锗化硅层形成方法及其制造方法 Download PDFInfo
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- CN1216405C CN1216405C CN011247398A CN01124739A CN1216405C CN 1216405 C CN1216405 C CN 1216405C CN 011247398 A CN011247398 A CN 011247398A CN 01124739 A CN01124739 A CN 01124739A CN 1216405 C CN1216405 C CN 1216405C
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 108
- 239000000758 substrate Substances 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title claims abstract description 56
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 230000005669 field effect Effects 0.000 title claims abstract description 27
- 239000000203 mixture Substances 0.000 claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 36
- 239000011248 coating agent Substances 0.000 claims description 26
- 238000000576 coating method Methods 0.000 claims description 26
- 230000003746 surface roughness Effects 0.000 abstract description 22
- 238000007598 dipping method Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000026267 regulation of growth Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000116 mitigating effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000006837 decompression Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/0251—Graded layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
- H01L29/66916—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN heterojunction gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
Claims (10)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000233640 | 2000-08-01 | ||
JP233640/2000 | 2000-08-01 | ||
JP2001165695A JP4269541B2 (ja) | 2000-08-01 | 2001-05-31 | 半導体基板と電界効果型トランジスタ並びにSiGe層の形成方法及びこれを用いた歪みSi層の形成方法と電界効果型トランジスタの製造方法 |
JP165695/2001 | 2001-05-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1336684A CN1336684A (zh) | 2002-02-20 |
CN1216405C true CN1216405C (zh) | 2005-08-24 |
Family
ID=26597197
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN011247398A Expired - Fee Related CN1216405C (zh) | 2000-08-01 | 2001-08-01 | 半导体衬底、场效应晶体管、锗化硅层形成方法及其制造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6525338B2 (zh) |
JP (1) | JP4269541B2 (zh) |
KR (1) | KR100650454B1 (zh) |
CN (1) | CN1216405C (zh) |
DE (1) | DE10137369B4 (zh) |
TW (1) | TW517284B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105047748A (zh) * | 2015-05-28 | 2015-11-11 | 中山大学 | 一种硅锗异质结太阳电池及其制备方法 |
Families Citing this family (69)
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US6503773B2 (en) * | 2000-01-20 | 2003-01-07 | Amberwave Systems Corporation | Low threading dislocation density relaxed mismatched epilayers without high temperature growth |
JP4207548B2 (ja) * | 2002-11-28 | 2009-01-14 | 株式会社Sumco | 半導体基板の製造方法及び電界効果型トランジスタの製造方法並びに半導体基板及び電界効果型トランジスタ |
US6855649B2 (en) * | 2001-06-12 | 2005-02-15 | International Business Machines Corporation | Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing |
US6515335B1 (en) * | 2002-01-04 | 2003-02-04 | International Business Machines Corporation | Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same |
KR100460201B1 (ko) * | 2002-04-08 | 2004-12-08 | 한국전자통신연구원 | SiGe/Si 이종 접합 전계 효과 트랜지스터 제조용 기판의 형성 방법 |
JP2003347229A (ja) | 2002-05-31 | 2003-12-05 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
GB0212616D0 (en) * | 2002-05-31 | 2002-07-10 | Univ Warwick | Formation of lattice-tuning semiconductor substrates |
US6995430B2 (en) * | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US20030227057A1 (en) | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
WO2004019391A2 (en) * | 2002-08-23 | 2004-03-04 | Amberwave Systems Corporation | Semiconductor heterostructures having reduced dislocation pile-ups and related methods |
US7594967B2 (en) * | 2002-08-30 | 2009-09-29 | Amberwave Systems Corporation | Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy |
GB0220438D0 (en) * | 2002-09-03 | 2002-10-09 | Univ Warwick | Formation of lattice-turning semiconductor substrates |
US7071014B2 (en) * | 2002-10-30 | 2006-07-04 | Amberwave Systems Corporation | Methods for preserving strained semiconductor substrate layers during CMOS processing |
JP3851950B2 (ja) * | 2002-11-19 | 2006-11-29 | 国立大学法人名古屋大学 | シリコンゲルマニウム膜の作製方法、エピタキシャル成長用基板、多層膜構造体及びヘテロ接合電界効果トランジスタ |
US6730576B1 (en) * | 2002-12-31 | 2004-05-04 | Advanced Micro Devices, Inc. | Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer |
DE602004020181D1 (de) * | 2003-01-07 | 2009-05-07 | Soitec Silicon On Insulator | Recycling eines wafers mit einer mehrschichtstruktur nach dem abnehmen einer dünnen schicht |
EP1439570A1 (en) * | 2003-01-14 | 2004-07-21 | Interuniversitair Microelektronica Centrum ( Imec) | SiGe strain relaxed buffer for high mobility devices and a method of fabricating it |
EP1588406B1 (en) * | 2003-01-27 | 2019-07-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures with structural homogeneity |
US6995427B2 (en) | 2003-01-29 | 2006-02-07 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same |
JP4306266B2 (ja) | 2003-02-04 | 2009-07-29 | 株式会社Sumco | 半導体基板の製造方法 |
DE10310740A1 (de) * | 2003-03-10 | 2004-09-30 | Forschungszentrum Jülich GmbH | Verfahren zur Herstellung einer spannungsrelaxierten Schichtstruktur auf einem nicht gitterangepassten Substrat, sowie Verwendung eines solchen Schichtsystems in elektronischen und/oder optoelektronischen Bauelementen |
US7026249B2 (en) * | 2003-05-30 | 2006-04-11 | International Business Machines Corporation | SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowth |
US20050196925A1 (en) * | 2003-12-22 | 2005-09-08 | Kim Sang H. | Method of forming stress-relaxed SiGe buffer layer |
US7247583B2 (en) | 2004-01-30 | 2007-07-24 | Toshiba Ceramics Co., Ltd. | Manufacturing method for strained silicon wafer |
JP2005244187A (ja) * | 2004-01-30 | 2005-09-08 | Toshiba Ceramics Co Ltd | 歪みシリコンウエハおよびその製造方法 |
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KR101216541B1 (ko) | 2008-09-19 | 2012-12-31 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 에피텍셜층 과성장에 의한 장치의 형성 |
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US9171715B2 (en) | 2012-09-05 | 2015-10-27 | Asm Ip Holding B.V. | Atomic layer deposition of GeO2 |
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US9218963B2 (en) | 2013-12-19 | 2015-12-22 | Asm Ip Holding B.V. | Cyclical deposition of germanium |
US9607990B2 (en) | 2015-08-28 | 2017-03-28 | International Business Machines Corporation | Method to form strained nFET and strained pFET nanowires on a same substrate |
US9666669B1 (en) | 2015-12-22 | 2017-05-30 | International Business Machines Corporation | Superlattice lateral bipolar junction transistor |
US10170660B2 (en) * | 2015-12-22 | 2019-01-01 | International Business Machines Corporation | Digital alloy germanium heterojunction solar cell |
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US5442205A (en) | 1991-04-24 | 1995-08-15 | At&T Corp. | Semiconductor heterostructure devices with strained semiconductor layers |
US5221413A (en) | 1991-04-24 | 1993-06-22 | At&T Bell Laboratories | Method for making low defect density semiconductor heterostructure and devices made thereby |
JPH0982944A (ja) * | 1995-09-18 | 1997-03-28 | Toshiba Corp | 歪シリコン電界効果トランジスタ及びその製造方法 |
US6039803A (en) | 1996-06-28 | 2000-03-21 | Massachusetts Institute Of Technology | Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon |
-
2001
- 2001-05-31 JP JP2001165695A patent/JP4269541B2/ja not_active Expired - Lifetime
- 2001-07-20 TW TW090117828A patent/TW517284B/zh not_active IP Right Cessation
- 2001-07-31 KR KR1020010046230A patent/KR100650454B1/ko active IP Right Grant
- 2001-07-31 US US09/917,923 patent/US6525338B2/en not_active Expired - Lifetime
- 2001-07-31 DE DE10137369A patent/DE10137369B4/de not_active Expired - Fee Related
- 2001-08-01 CN CN011247398A patent/CN1216405C/zh not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105047748A (zh) * | 2015-05-28 | 2015-11-11 | 中山大学 | 一种硅锗异质结太阳电池及其制备方法 |
CN105047748B (zh) * | 2015-05-28 | 2017-08-11 | 中山大学 | 一种硅锗异质结太阳电池及其制备方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20020011338A (ko) | 2002-02-08 |
TW517284B (en) | 2003-01-11 |
KR100650454B1 (ko) | 2006-11-28 |
CN1336684A (zh) | 2002-02-20 |
US6525338B2 (en) | 2003-02-25 |
DE10137369A1 (de) | 2002-04-25 |
JP4269541B2 (ja) | 2009-05-27 |
US20020017642A1 (en) | 2002-02-14 |
DE10137369B4 (de) | 2012-08-09 |
JP2002118254A (ja) | 2002-04-19 |
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