CN1199273C - 半导体装置及其设计方法和设计装置 - Google Patents
半导体装置及其设计方法和设计装置 Download PDFInfo
- Publication number
- CN1199273C CN1199273C CNB011243597A CN01124359A CN1199273C CN 1199273 C CN1199273 C CN 1199273C CN B011243597 A CNB011243597 A CN B011243597A CN 01124359 A CN01124359 A CN 01124359A CN 1199273 C CN1199273 C CN 1199273C
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- wiring
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000000034 method Methods 0.000 title claims description 40
- 238000013461 design Methods 0.000 title claims description 39
- 239000010410 layer Substances 0.000 claims description 85
- 230000004087 circulation Effects 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 17
- 238000010586 diagram Methods 0.000 claims description 7
- 240000000233 Melia azedarach Species 0.000 claims description 3
- 238000013440 design planning Methods 0.000 claims description 3
- 238000007689 inspection Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 22
- 229920005591 polysilicon Polymers 0.000 description 22
- 238000012938 design process Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 5
- 238000012937 correction Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000009931 harmful effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000011960 computer-aided design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Geometry (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (5)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000251861A JP4553461B2 (ja) | 2000-08-23 | 2000-08-23 | 半導体装置、その設計方法および設計装置 |
JP231861/00 | 2000-08-23 | ||
JP251861/2000 | 2000-08-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1339825A CN1339825A (zh) | 2002-03-13 |
CN1199273C true CN1199273C (zh) | 2005-04-27 |
Family
ID=18741207
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB011243597A Expired - Fee Related CN1199273C (zh) | 2000-08-23 | 2001-07-26 | 半导体装置及其设计方法和设计装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6838770B2 (zh) |
JP (1) | JP4553461B2 (zh) |
KR (1) | KR100429112B1 (zh) |
CN (1) | CN1199273C (zh) |
TW (1) | TW502373B (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4684911B2 (ja) * | 2000-12-08 | 2011-05-18 | 富士通株式会社 | シールド配線を行うためのlsi |
US6748579B2 (en) * | 2002-08-30 | 2004-06-08 | Lsi Logic Corporation | Method of using filler metal for implementing changes in an integrated circuit design |
US6924552B2 (en) * | 2002-10-21 | 2005-08-02 | Hrl Laboratories, Llc | Multilayered integrated circuit with extraneous conductive traces |
DE10253626A1 (de) * | 2002-11-15 | 2004-06-03 | Infineon Technologies Ag | Teststruktur zur Bestimmung der elektrischen Belastbarkeit von Kontakten |
JP2007528121A (ja) * | 2003-07-11 | 2007-10-04 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 機密性を要する半導体製品、特にスマートカード・チップ |
TWI234835B (en) * | 2003-09-08 | 2005-06-21 | Realtek Semiconductor Corp | Method for checking via density in IC layout |
DE102004007661B4 (de) * | 2004-02-17 | 2006-07-27 | Infineon Technologies Ag | Verfahren, Vorrichtung und Computerprogrammprodukt zur Optimierung eines Layouts von Versorgungsleitungen |
KR100734507B1 (ko) * | 2005-05-12 | 2007-07-03 | 하이맥스 테크놀로지스, 인코포레이션 | 고전압 소자의 전류 누설을 방지하기 위한 구조 |
WO2008068805A1 (ja) * | 2006-11-30 | 2008-06-12 | Fujitsu Microelectronics Limited | 半導体装置、半導体装置の製造方法および多層配線の設計方法 |
KR100862870B1 (ko) * | 2007-05-10 | 2008-10-09 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조방법 |
JP2009151433A (ja) * | 2007-12-19 | 2009-07-09 | Nec Electronics Corp | 半導体集積回路のレイアウト設計装置及びレイアウト設計方法 |
US7999361B1 (en) * | 2010-02-19 | 2011-08-16 | Altera Corporation | Shielding structure for transmission lines |
US11334703B2 (en) * | 2017-06-29 | 2022-05-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit layouts with fill feature shapes |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0834251B2 (ja) | 1988-08-03 | 1996-03-29 | 富士通株式会社 | 論理モジュール間配線方法 |
JP3079545B2 (ja) | 1990-08-09 | 2000-08-21 | 日本電気株式会社 | 半導体記憶装置 |
JP3390875B2 (ja) * | 1992-11-12 | 2003-03-31 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置 |
JPH06216247A (ja) * | 1993-01-14 | 1994-08-05 | Hitachi Ltd | 半導体集積回路、及びその配線パターンの修正方法 |
JPH09115905A (ja) * | 1995-10-23 | 1997-05-02 | Matsushita Electric Ind Co Ltd | ダミーパターンの設計方法 |
JPH09293721A (ja) * | 1995-12-15 | 1997-11-11 | Lsi Logic Corp | 集積回路構造の処理のためにパターンデザインを改善するための方法 |
KR0185298B1 (ko) * | 1995-12-30 | 1999-04-15 | 김주용 | 반도체 소자의 콘택홀 매립용 플러그 형성방법 |
JPH09289251A (ja) | 1996-04-23 | 1997-11-04 | Matsushita Electric Ind Co Ltd | 半導体集積回路のレイアウト構造およびその検証方法 |
KR19980054477A (ko) | 1996-12-27 | 1998-09-25 | 김영환 | 반도체 장치 제조 방법 |
JP3180729B2 (ja) * | 1997-08-20 | 2001-06-25 | 日本電気株式会社 | 半導体装置 |
JPH11297841A (ja) | 1998-04-14 | 1999-10-29 | Iwate Toshiba Electronics Kk | 半導体集積回路およびその製造方法 |
KR100290477B1 (ko) * | 1998-10-27 | 2001-08-07 | 박종섭 | 반도체 소자의 금속 배선 구조 및 그 형성 방법 |
JP2001068635A (ja) | 1999-08-27 | 2001-03-16 | Mitsubishi Electric Corp | 半導体装置 |
KR100498441B1 (ko) * | 2001-04-17 | 2005-07-01 | 삼성전자주식회사 | 광근접 효과의 보정을 위한 마스크와 그 제조 방법 |
-
2000
- 2000-08-23 JP JP2000251861A patent/JP4553461B2/ja not_active Expired - Fee Related
-
2001
- 2001-06-27 US US09/891,356 patent/US6838770B2/en not_active Expired - Lifetime
- 2001-07-17 TW TW090117415A patent/TW502373B/zh not_active IP Right Cessation
- 2001-07-26 CN CNB011243597A patent/CN1199273C/zh not_active Expired - Fee Related
- 2001-07-26 KR KR10-2001-0045116A patent/KR100429112B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100429112B1 (ko) | 2004-04-29 |
US20020024148A1 (en) | 2002-02-28 |
JP4553461B2 (ja) | 2010-09-29 |
TW502373B (en) | 2002-09-11 |
CN1339825A (zh) | 2002-03-13 |
US6838770B2 (en) | 2005-01-04 |
KR20020015941A (ko) | 2002-03-02 |
JP2002076118A (ja) | 2002-03-15 |
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C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: RENESAS ELECTRONICS CORPORATION Free format text: FORMER OWNER: MISSUBISHI ELECTRIC CORP. Effective date: 20141029 |
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C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20141029 Address after: Kawasaki, Kanagawa, Japan Patentee after: Renesas Electronics Corporation Address before: Tokyo, Japan, Japan Patentee before: Missubishi Electric Co., Ltd. |
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CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050427 Termination date: 20200726 |
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CF01 | Termination of patent right due to non-payment of annual fee |